developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 1 | /dts-v1/; |
| 2 | #include "mt7986a.dtsi" |
| 3 | #include "mt7986a-pinctrl.dtsi" |
| 4 | / { |
| 5 | model = "MediaTek MT7986a RFB"; |
developer | 8262b0d | 2021-11-12 09:02:17 +0800 | [diff] [blame] | 6 | compatible = "mediatek,mt7986a-emmc-rfb"; |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 7 | chosen { |
| 8 | bootargs = "console=ttyS0,115200n1 loglevel=8 \ |
| 9 | earlycon=uart8250,mmio32,0x11002000 \ |
developer | 8262b0d | 2021-11-12 09:02:17 +0800 | [diff] [blame] | 10 | root=PARTLABEL=rootfs rootwait rootfstype=squashfs,f2fs"; |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 11 | }; |
| 12 | |
| 13 | memory { |
| 14 | reg = <0 0x40000000 0 0x10000000>; |
| 15 | }; |
| 16 | |
| 17 | reg_1p8v: regulator-1p8v { |
| 18 | compatible = "regulator-fixed"; |
| 19 | regulator-name = "fixed-1.8V"; |
| 20 | regulator-min-microvolt = <1800000>; |
| 21 | regulator-max-microvolt = <1800000>; |
| 22 | regulator-boot-on; |
| 23 | regulator-always-on; |
| 24 | }; |
| 25 | |
| 26 | reg_3p3v: regulator-3p3v { |
| 27 | compatible = "regulator-fixed"; |
| 28 | regulator-name = "fixed-3.3V"; |
| 29 | regulator-min-microvolt = <3300000>; |
| 30 | regulator-max-microvolt = <3300000>; |
| 31 | regulator-boot-on; |
| 32 | regulator-always-on; |
| 33 | }; |
| 34 | |
| 35 | sound { |
| 36 | compatible = "mediatek,mt7986-wm8960-machine"; |
| 37 | mediatek,platform = <&afe>; |
| 38 | audio-routing = "Headphone", "HP_L", |
| 39 | "Headphone", "HP_R", |
| 40 | "LINPUT1", "AMIC", |
| 41 | "RINPUT1", "AMIC"; |
| 42 | mediatek,audio-codec = <&wm8960>; |
| 43 | status = "okay"; |
| 44 | }; |
| 45 | }; |
| 46 | |
developer | 209e52d | 2022-06-30 11:32:57 +0800 | [diff] [blame] | 47 | &fan { |
| 48 | pwms = <&pwm 1 50000 0>; |
| 49 | status = "disabled"; |
| 50 | }; |
| 51 | |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 52 | &pwm { |
| 53 | pinctrl-names = "default"; |
| 54 | pinctrl-0 = <&pwm0_pin &pwm1_pin_g1>; |
| 55 | status = "okay"; |
| 56 | }; |
| 57 | |
| 58 | &uart0 { |
| 59 | status = "okay"; |
| 60 | }; |
| 61 | |
| 62 | &uart1 { |
| 63 | pinctrl-names = "default"; |
| 64 | pinctrl-0 = <&uart1_pins>; |
| 65 | status = "okay"; |
| 66 | }; |
| 67 | |
| 68 | &uart2 { |
| 69 | pinctrl-names = "default"; |
| 70 | pinctrl-0 = <&uart2_pins>; |
developer | 2f7d2b3 | 2022-09-21 22:41:12 +0800 | [diff] [blame] | 71 | status = "okay"; |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 72 | }; |
| 73 | |
| 74 | &i2c0 { |
| 75 | pinctrl-names = "default"; |
| 76 | pinctrl-0 = <&i2c_pins>; |
| 77 | status = "okay"; |
| 78 | |
| 79 | wm8960: wm8960@1a { |
| 80 | compatible = "wlf,wm8960"; |
| 81 | reg = <0x1a>; |
| 82 | }; |
| 83 | }; |
| 84 | |
| 85 | &auxadc { |
| 86 | status = "okay"; |
| 87 | }; |
| 88 | |
| 89 | &watchdog { |
| 90 | status = "okay"; |
| 91 | }; |
| 92 | |
| 93 | ð { |
| 94 | status = "okay"; |
| 95 | |
| 96 | gmac0: mac@0 { |
| 97 | compatible = "mediatek,eth-mac"; |
| 98 | reg = <0>; |
| 99 | phy-mode = "2500base-x"; |
developer | 283fc45 | 2022-08-18 19:50:33 +0800 | [diff] [blame] | 100 | |
| 101 | fixed-link { |
| 102 | speed = <2500>; |
| 103 | full-duplex; |
| 104 | pause; |
developer | 283fc45 | 2022-08-18 19:50:33 +0800 | [diff] [blame] | 105 | }; |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 106 | }; |
| 107 | |
| 108 | gmac1: mac@1 { |
| 109 | compatible = "mediatek,eth-mac"; |
| 110 | reg = <1>; |
| 111 | phy-mode = "2500base-x"; |
developer | 2f7d2b3 | 2022-09-21 22:41:12 +0800 | [diff] [blame] | 112 | phy-handle = <&phy6>; |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 113 | }; |
| 114 | |
| 115 | mdio: mdio-bus { |
| 116 | #address-cells = <1>; |
| 117 | #size-cells = <0>; |
| 118 | |
developer | f0a1e45 | 2022-08-15 12:06:11 +0800 | [diff] [blame] | 119 | reset-gpios = <&pio 6 1>; |
| 120 | reset-delay-us = <600>; |
| 121 | |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 122 | phy5: phy@5 { |
developer | 2f7d2b3 | 2022-09-21 22:41:12 +0800 | [diff] [blame] | 123 | compatible = "ethernet-phy-ieee802.3-c45"; |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 124 | reg = <5>; |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 125 | }; |
| 126 | |
| 127 | phy6: phy@6 { |
developer | 2f7d2b3 | 2022-09-21 22:41:12 +0800 | [diff] [blame] | 128 | compatible = "ethernet-phy-ieee802.3-c45"; |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 129 | reg = <6>; |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 130 | }; |
| 131 | |
| 132 | switch@0 { |
| 133 | compatible = "mediatek,mt7531"; |
| 134 | reg = <31>; |
| 135 | reset-gpios = <&pio 5 0>; |
| 136 | |
| 137 | ports { |
| 138 | #address-cells = <1>; |
| 139 | #size-cells = <0>; |
| 140 | |
| 141 | port@0 { |
| 142 | reg = <0>; |
| 143 | label = "lan0"; |
| 144 | }; |
| 145 | |
| 146 | port@1 { |
| 147 | reg = <1>; |
| 148 | label = "lan1"; |
| 149 | }; |
| 150 | |
| 151 | port@2 { |
| 152 | reg = <2>; |
| 153 | label = "lan2"; |
| 154 | }; |
| 155 | |
| 156 | port@3 { |
| 157 | reg = <3>; |
| 158 | label = "lan3"; |
| 159 | }; |
| 160 | |
| 161 | port@4 { |
| 162 | reg = <4>; |
| 163 | label = "lan4"; |
| 164 | }; |
| 165 | |
| 166 | port@5 { |
| 167 | reg = <5>; |
| 168 | label = "lan5"; |
| 169 | phy-mode = "2500base-x"; |
developer | 2f7d2b3 | 2022-09-21 22:41:12 +0800 | [diff] [blame] | 170 | phy-handle = <&phy5>; |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 171 | }; |
| 172 | |
| 173 | port@6 { |
| 174 | reg = <6>; |
| 175 | label = "cpu"; |
| 176 | ethernet = <&gmac0>; |
| 177 | phy-mode = "2500base-x"; |
| 178 | |
| 179 | fixed-link { |
| 180 | speed = <2500>; |
| 181 | full-duplex; |
| 182 | pause; |
| 183 | }; |
| 184 | }; |
| 185 | }; |
| 186 | }; |
| 187 | }; |
| 188 | }; |
| 189 | |
| 190 | &hnat { |
| 191 | mtketh-wan = "eth1"; |
| 192 | mtketh-lan = "lan"; |
| 193 | mtketh-max-gmac = <2>; |
| 194 | status = "okay"; |
| 195 | }; |
| 196 | |
| 197 | &spi1 { |
| 198 | pinctrl-names = "default"; |
| 199 | pinctrl-0 = <&spic_pins_g2>; |
| 200 | status = "okay"; |
| 201 | }; |
| 202 | |
| 203 | &mmc0 { |
| 204 | pinctrl-names = "default", "state_uhs"; |
| 205 | pinctrl-0 = <&mmc0_pins_default>; |
| 206 | pinctrl-1 = <&mmc0_pins_uhs>; |
| 207 | bus-width = <8>; |
| 208 | max-frequency = <200000000>; |
| 209 | cap-mmc-highspeed; |
| 210 | mmc-hs200-1_8v; |
| 211 | mmc-hs400-1_8v; |
| 212 | hs400-ds-delay = <0x14014>; |
| 213 | vmmc-supply = <®_3p3v>; |
| 214 | vqmmc-supply = <®_1p8v>; |
| 215 | non-removable; |
| 216 | no-sd; |
| 217 | no-sdio; |
| 218 | status = "okay"; |
| 219 | }; |
| 220 | |
| 221 | &pcie0 { |
| 222 | pinctrl-names = "default"; |
| 223 | pinctrl-0 = <&pcie0_pins>; |
| 224 | status = "okay"; |
| 225 | }; |
| 226 | |
| 227 | &wbsys { |
| 228 | mediatek,mtd-eeprom = <&factory 0x0000>; |
| 229 | status = "okay"; |
| 230 | }; |
| 231 | |
| 232 | &pio { |
| 233 | mmc0_pins_default: mmc0-pins-50-to-61-default { |
| 234 | mux { |
| 235 | function = "flash"; |
| 236 | groups = "emmc_51"; |
| 237 | }; |
| 238 | conf-cmd-dat { |
| 239 | pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", |
| 240 | "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", |
| 241 | "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; |
| 242 | input-enable; |
| 243 | drive-strength = <MTK_DRIVE_4mA>; |
| 244 | mediatek,pull-up-adv = <1>; /* pull-up 10K */ |
| 245 | }; |
| 246 | conf-clk { |
| 247 | pins = "EMMC_CK"; |
| 248 | drive-strength = <MTK_DRIVE_6mA>; |
| 249 | mediatek,pull-down-adv = <2>; /* pull-down 50K */ |
| 250 | }; |
| 251 | conf-ds { |
| 252 | pins = "EMMC_DSL"; |
| 253 | mediatek,pull-down-adv = <2>; /* pull-down 50K */ |
| 254 | }; |
| 255 | conf-rst { |
| 256 | pins = "EMMC_RSTB"; |
| 257 | drive-strength = <MTK_DRIVE_4mA>; |
| 258 | mediatek,pull-up-adv = <1>; /* pull-up 10K */ |
| 259 | }; |
| 260 | }; |
| 261 | |
| 262 | mmc0_pins_uhs: mmc0-pins-50-to-61-uhs { |
| 263 | mux { |
| 264 | function = "flash"; |
| 265 | groups = "emmc_51"; |
| 266 | }; |
| 267 | conf-cmd-dat { |
| 268 | pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", |
| 269 | "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", |
| 270 | "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; |
| 271 | input-enable; |
| 272 | drive-strength = <MTK_DRIVE_4mA>; |
| 273 | mediatek,pull-up-adv = <1>; /* pull-up 10K */ |
| 274 | }; |
| 275 | conf-clk { |
| 276 | pins = "EMMC_CK"; |
| 277 | drive-strength = <MTK_DRIVE_6mA>; |
| 278 | mediatek,pull-down-adv = <2>; /* pull-down 50K */ |
| 279 | }; |
| 280 | conf-ds { |
| 281 | pins = "EMMC_DSL"; |
| 282 | mediatek,pull-down-adv = <2>; /* pull-down 50K */ |
| 283 | }; |
| 284 | conf-rst { |
| 285 | pins = "EMMC_RSTB"; |
| 286 | drive-strength = <MTK_DRIVE_4mA>; |
| 287 | mediatek,pull-up-adv = <1>; /* pull-up 10K */ |
| 288 | }; |
| 289 | }; |
| 290 | }; |