blob: d1908727f10dc1222f028a2327d1bdb364837b26 [file] [log] [blame]
developer565bacb2021-09-28 21:26:32 +08001/dts-v1/;
2#include "mt7986a.dtsi"
3#include "mt7986a-pinctrl.dtsi"
4/ {
5 model = "MediaTek MT7986a RFB";
developer8262b0d2021-11-12 09:02:17 +08006 compatible = "mediatek,mt7986a-emmc-rfb";
developer565bacb2021-09-28 21:26:32 +08007 chosen {
8 bootargs = "console=ttyS0,115200n1 loglevel=8 \
9 earlycon=uart8250,mmio32,0x11002000 \
developer8262b0d2021-11-12 09:02:17 +080010 root=PARTLABEL=rootfs rootwait rootfstype=squashfs,f2fs";
developer565bacb2021-09-28 21:26:32 +080011 };
12
13 memory {
14 reg = <0 0x40000000 0 0x10000000>;
15 };
16
17 reg_1p8v: regulator-1p8v {
18 compatible = "regulator-fixed";
19 regulator-name = "fixed-1.8V";
20 regulator-min-microvolt = <1800000>;
21 regulator-max-microvolt = <1800000>;
22 regulator-boot-on;
23 regulator-always-on;
24 };
25
26 reg_3p3v: regulator-3p3v {
27 compatible = "regulator-fixed";
28 regulator-name = "fixed-3.3V";
29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <3300000>;
31 regulator-boot-on;
32 regulator-always-on;
33 };
34
35 sound {
36 compatible = "mediatek,mt7986-wm8960-machine";
37 mediatek,platform = <&afe>;
38 audio-routing = "Headphone", "HP_L",
39 "Headphone", "HP_R",
40 "LINPUT1", "AMIC",
41 "RINPUT1", "AMIC";
42 mediatek,audio-codec = <&wm8960>;
43 status = "okay";
44 };
45};
46
developer209e52d2022-06-30 11:32:57 +080047&fan {
48 pwms = <&pwm 1 50000 0>;
49 status = "disabled";
50};
51
developer565bacb2021-09-28 21:26:32 +080052&pwm {
53 pinctrl-names = "default";
54 pinctrl-0 = <&pwm0_pin &pwm1_pin_g1>;
55 status = "okay";
56};
57
58&uart0 {
59 status = "okay";
60};
61
62&uart1 {
63 pinctrl-names = "default";
64 pinctrl-0 = <&uart1_pins>;
65 status = "okay";
66};
67
68&uart2 {
69 pinctrl-names = "default";
70 pinctrl-0 = <&uart2_pins>;
71 status = "okay";
72};
73
74&i2c0 {
75 pinctrl-names = "default";
76 pinctrl-0 = <&i2c_pins>;
77 status = "okay";
78
79 wm8960: wm8960@1a {
80 compatible = "wlf,wm8960";
81 reg = <0x1a>;
82 };
83};
84
85&auxadc {
86 status = "okay";
87};
88
89&watchdog {
90 status = "okay";
91};
92
93&eth {
94 status = "okay";
95
96 gmac0: mac@0 {
97 compatible = "mediatek,eth-mac";
98 reg = <0>;
99 phy-mode = "2500base-x";
100
101 fixed-link {
102 speed = <2500>;
103 full-duplex;
104 pause;
105 };
106 };
107
108 gmac1: mac@1 {
109 compatible = "mediatek,eth-mac";
110 reg = <1>;
111 phy-mode = "2500base-x";
112
113 fixed-link {
114 speed = <2500>;
115 full-duplex;
116 pause;
117 };
118 };
119
120 mdio: mdio-bus {
121 #address-cells = <1>;
122 #size-cells = <0>;
123
124 phy5: phy@5 {
125 compatible = "ethernet-phy-id67c9.de0a";
126 reg = <5>;
127 reset-gpios = <&pio 6 1>;
developer8c5a08b2022-05-06 09:10:38 +0800128 reset-assert-us = <600>;
developer565bacb2021-09-28 21:26:32 +0800129 reset-deassert-us = <20000>;
130 phy-mode = "2500base-x";
131 };
132
133 phy6: phy@6 {
134 compatible = "ethernet-phy-id67c9.de0a";
135 reg = <6>;
136 phy-mode = "2500base-x";
137 };
138
139 switch@0 {
140 compatible = "mediatek,mt7531";
141 reg = <31>;
142 reset-gpios = <&pio 5 0>;
143
144 ports {
145 #address-cells = <1>;
146 #size-cells = <0>;
147
148 port@0 {
149 reg = <0>;
150 label = "lan0";
151 };
152
153 port@1 {
154 reg = <1>;
155 label = "lan1";
156 };
157
158 port@2 {
159 reg = <2>;
160 label = "lan2";
161 };
162
163 port@3 {
164 reg = <3>;
165 label = "lan3";
166 };
167
168 port@4 {
169 reg = <4>;
170 label = "lan4";
171 };
172
173 port@5 {
174 reg = <5>;
175 label = "lan5";
176 phy-mode = "2500base-x";
177
178 fixed-link {
179 speed = <2500>;
180 full-duplex;
181 pause;
182 };
183 };
184
185 port@6 {
186 reg = <6>;
187 label = "cpu";
188 ethernet = <&gmac0>;
189 phy-mode = "2500base-x";
190
191 fixed-link {
192 speed = <2500>;
193 full-duplex;
194 pause;
195 };
196 };
197 };
198 };
199 };
200};
201
202&hnat {
203 mtketh-wan = "eth1";
204 mtketh-lan = "lan";
205 mtketh-max-gmac = <2>;
206 status = "okay";
207};
208
209&spi1 {
210 pinctrl-names = "default";
211 pinctrl-0 = <&spic_pins_g2>;
212 status = "okay";
213};
214
215&mmc0 {
216 pinctrl-names = "default", "state_uhs";
217 pinctrl-0 = <&mmc0_pins_default>;
218 pinctrl-1 = <&mmc0_pins_uhs>;
219 bus-width = <8>;
220 max-frequency = <200000000>;
221 cap-mmc-highspeed;
222 mmc-hs200-1_8v;
223 mmc-hs400-1_8v;
224 hs400-ds-delay = <0x14014>;
225 vmmc-supply = <&reg_3p3v>;
226 vqmmc-supply = <&reg_1p8v>;
227 non-removable;
228 no-sd;
229 no-sdio;
230 status = "okay";
231};
232
233&pcie0 {
234 pinctrl-names = "default";
235 pinctrl-0 = <&pcie0_pins>;
236 status = "okay";
237};
238
239&wbsys {
240 mediatek,mtd-eeprom = <&factory 0x0000>;
241 status = "okay";
242};
243
244&pio {
245 mmc0_pins_default: mmc0-pins-50-to-61-default {
246 mux {
247 function = "flash";
248 groups = "emmc_51";
249 };
250 conf-cmd-dat {
251 pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
252 "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
253 "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
254 input-enable;
255 drive-strength = <MTK_DRIVE_4mA>;
256 mediatek,pull-up-adv = <1>; /* pull-up 10K */
257 };
258 conf-clk {
259 pins = "EMMC_CK";
260 drive-strength = <MTK_DRIVE_6mA>;
261 mediatek,pull-down-adv = <2>; /* pull-down 50K */
262 };
263 conf-ds {
264 pins = "EMMC_DSL";
265 mediatek,pull-down-adv = <2>; /* pull-down 50K */
266 };
267 conf-rst {
268 pins = "EMMC_RSTB";
269 drive-strength = <MTK_DRIVE_4mA>;
270 mediatek,pull-up-adv = <1>; /* pull-up 10K */
271 };
272 };
273
274 mmc0_pins_uhs: mmc0-pins-50-to-61-uhs {
275 mux {
276 function = "flash";
277 groups = "emmc_51";
278 };
279 conf-cmd-dat {
280 pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
281 "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
282 "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
283 input-enable;
284 drive-strength = <MTK_DRIVE_4mA>;
285 mediatek,pull-up-adv = <1>; /* pull-up 10K */
286 };
287 conf-clk {
288 pins = "EMMC_CK";
289 drive-strength = <MTK_DRIVE_6mA>;
290 mediatek,pull-down-adv = <2>; /* pull-down 50K */
291 };
292 conf-ds {
293 pins = "EMMC_DSL";
294 mediatek,pull-down-adv = <2>; /* pull-down 50K */
295 };
296 conf-rst {
297 pins = "EMMC_RSTB";
298 drive-strength = <MTK_DRIVE_4mA>;
299 mediatek,pull-up-adv = <1>; /* pull-up 10K */
300 };
301 };
302};