developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 1 | /dts-v1/; |
| 2 | #include "mt7986a.dtsi" |
| 3 | #include "mt7986a-pinctrl.dtsi" |
| 4 | / { |
| 5 | model = "MediaTek MT7986a RFB"; |
developer | 8262b0d | 2021-11-12 09:02:17 +0800 | [diff] [blame] | 6 | compatible = "mediatek,mt7986a-emmc-rfb"; |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 7 | chosen { |
| 8 | bootargs = "console=ttyS0,115200n1 loglevel=8 \ |
| 9 | earlycon=uart8250,mmio32,0x11002000 \ |
developer | 8262b0d | 2021-11-12 09:02:17 +0800 | [diff] [blame] | 10 | root=PARTLABEL=rootfs rootwait rootfstype=squashfs,f2fs"; |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 11 | }; |
| 12 | |
| 13 | memory { |
| 14 | reg = <0 0x40000000 0 0x10000000>; |
| 15 | }; |
| 16 | |
| 17 | reg_1p8v: regulator-1p8v { |
| 18 | compatible = "regulator-fixed"; |
| 19 | regulator-name = "fixed-1.8V"; |
| 20 | regulator-min-microvolt = <1800000>; |
| 21 | regulator-max-microvolt = <1800000>; |
| 22 | regulator-boot-on; |
| 23 | regulator-always-on; |
| 24 | }; |
| 25 | |
| 26 | reg_3p3v: regulator-3p3v { |
| 27 | compatible = "regulator-fixed"; |
| 28 | regulator-name = "fixed-3.3V"; |
| 29 | regulator-min-microvolt = <3300000>; |
| 30 | regulator-max-microvolt = <3300000>; |
| 31 | regulator-boot-on; |
| 32 | regulator-always-on; |
| 33 | }; |
| 34 | |
| 35 | sound { |
| 36 | compatible = "mediatek,mt7986-wm8960-machine"; |
| 37 | mediatek,platform = <&afe>; |
| 38 | audio-routing = "Headphone", "HP_L", |
| 39 | "Headphone", "HP_R", |
| 40 | "LINPUT1", "AMIC", |
| 41 | "RINPUT1", "AMIC"; |
| 42 | mediatek,audio-codec = <&wm8960>; |
| 43 | status = "okay"; |
| 44 | }; |
| 45 | }; |
| 46 | |
developer | 209e52d | 2022-06-30 11:32:57 +0800 | [diff] [blame] | 47 | &fan { |
| 48 | pwms = <&pwm 1 50000 0>; |
| 49 | status = "disabled"; |
| 50 | }; |
| 51 | |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 52 | &pwm { |
| 53 | pinctrl-names = "default"; |
| 54 | pinctrl-0 = <&pwm0_pin &pwm1_pin_g1>; |
| 55 | status = "okay"; |
| 56 | }; |
| 57 | |
| 58 | &uart0 { |
| 59 | status = "okay"; |
| 60 | }; |
| 61 | |
| 62 | &uart1 { |
| 63 | pinctrl-names = "default"; |
| 64 | pinctrl-0 = <&uart1_pins>; |
| 65 | status = "okay"; |
| 66 | }; |
| 67 | |
| 68 | &uart2 { |
| 69 | pinctrl-names = "default"; |
| 70 | pinctrl-0 = <&uart2_pins>; |
developer | a2613e6 | 2022-07-01 18:29:37 +0800 | [diff] [blame] | 71 | status = "disabled"; |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 72 | }; |
| 73 | |
| 74 | &i2c0 { |
| 75 | pinctrl-names = "default"; |
| 76 | pinctrl-0 = <&i2c_pins>; |
| 77 | status = "okay"; |
| 78 | |
| 79 | wm8960: wm8960@1a { |
| 80 | compatible = "wlf,wm8960"; |
| 81 | reg = <0x1a>; |
| 82 | }; |
| 83 | }; |
| 84 | |
| 85 | &auxadc { |
| 86 | status = "okay"; |
| 87 | }; |
| 88 | |
| 89 | &watchdog { |
| 90 | status = "okay"; |
| 91 | }; |
| 92 | |
| 93 | ð { |
| 94 | status = "okay"; |
| 95 | |
| 96 | gmac0: mac@0 { |
| 97 | compatible = "mediatek,eth-mac"; |
| 98 | reg = <0>; |
| 99 | phy-mode = "2500base-x"; |
developer | 283fc45 | 2022-08-18 19:50:33 +0800 | [diff] [blame^] | 100 | |
| 101 | fixed-link { |
| 102 | speed = <2500>; |
| 103 | full-duplex; |
| 104 | pause; |
| 105 | link-gpio = <&pio 47 0>; |
| 106 | phy-handle = <&phy5>; |
| 107 | label = "lan5"; |
| 108 | }; |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 109 | }; |
| 110 | |
| 111 | gmac1: mac@1 { |
| 112 | compatible = "mediatek,eth-mac"; |
| 113 | reg = <1>; |
| 114 | phy-mode = "2500base-x"; |
developer | f0a1e45 | 2022-08-15 12:06:11 +0800 | [diff] [blame] | 115 | phy-handle = <&phy6>; |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 116 | }; |
| 117 | |
| 118 | mdio: mdio-bus { |
| 119 | #address-cells = <1>; |
| 120 | #size-cells = <0>; |
| 121 | |
developer | f0a1e45 | 2022-08-15 12:06:11 +0800 | [diff] [blame] | 122 | reset-gpios = <&pio 6 1>; |
| 123 | reset-delay-us = <600>; |
| 124 | |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 125 | phy5: phy@5 { |
developer | 283fc45 | 2022-08-18 19:50:33 +0800 | [diff] [blame^] | 126 | compatible = "ethernet-phy-id67c9.de0a"; |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 127 | reg = <5>; |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 128 | }; |
| 129 | |
| 130 | phy6: phy@6 { |
developer | f0a1e45 | 2022-08-15 12:06:11 +0800 | [diff] [blame] | 131 | compatible = "ethernet-phy-ieee802.3-c45"; |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 132 | reg = <6>; |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 133 | }; |
| 134 | |
| 135 | switch@0 { |
| 136 | compatible = "mediatek,mt7531"; |
| 137 | reg = <31>; |
| 138 | reset-gpios = <&pio 5 0>; |
| 139 | |
| 140 | ports { |
| 141 | #address-cells = <1>; |
| 142 | #size-cells = <0>; |
| 143 | |
| 144 | port@0 { |
| 145 | reg = <0>; |
| 146 | label = "lan0"; |
| 147 | }; |
| 148 | |
| 149 | port@1 { |
| 150 | reg = <1>; |
| 151 | label = "lan1"; |
| 152 | }; |
| 153 | |
| 154 | port@2 { |
| 155 | reg = <2>; |
| 156 | label = "lan2"; |
| 157 | }; |
| 158 | |
| 159 | port@3 { |
| 160 | reg = <3>; |
| 161 | label = "lan3"; |
| 162 | }; |
| 163 | |
| 164 | port@4 { |
| 165 | reg = <4>; |
| 166 | label = "lan4"; |
| 167 | }; |
| 168 | |
| 169 | port@5 { |
| 170 | reg = <5>; |
| 171 | label = "lan5"; |
| 172 | phy-mode = "2500base-x"; |
| 173 | |
| 174 | fixed-link { |
| 175 | speed = <2500>; |
| 176 | full-duplex; |
| 177 | pause; |
| 178 | }; |
| 179 | }; |
| 180 | |
| 181 | port@6 { |
| 182 | reg = <6>; |
| 183 | label = "cpu"; |
| 184 | ethernet = <&gmac0>; |
| 185 | phy-mode = "2500base-x"; |
| 186 | |
| 187 | fixed-link { |
| 188 | speed = <2500>; |
| 189 | full-duplex; |
| 190 | pause; |
| 191 | }; |
| 192 | }; |
| 193 | }; |
| 194 | }; |
| 195 | }; |
| 196 | }; |
| 197 | |
| 198 | &hnat { |
| 199 | mtketh-wan = "eth1"; |
| 200 | mtketh-lan = "lan"; |
| 201 | mtketh-max-gmac = <2>; |
| 202 | status = "okay"; |
| 203 | }; |
| 204 | |
| 205 | &spi1 { |
| 206 | pinctrl-names = "default"; |
| 207 | pinctrl-0 = <&spic_pins_g2>; |
| 208 | status = "okay"; |
| 209 | }; |
| 210 | |
| 211 | &mmc0 { |
| 212 | pinctrl-names = "default", "state_uhs"; |
| 213 | pinctrl-0 = <&mmc0_pins_default>; |
| 214 | pinctrl-1 = <&mmc0_pins_uhs>; |
| 215 | bus-width = <8>; |
| 216 | max-frequency = <200000000>; |
| 217 | cap-mmc-highspeed; |
| 218 | mmc-hs200-1_8v; |
| 219 | mmc-hs400-1_8v; |
| 220 | hs400-ds-delay = <0x14014>; |
| 221 | vmmc-supply = <®_3p3v>; |
| 222 | vqmmc-supply = <®_1p8v>; |
| 223 | non-removable; |
| 224 | no-sd; |
| 225 | no-sdio; |
| 226 | status = "okay"; |
| 227 | }; |
| 228 | |
| 229 | &pcie0 { |
| 230 | pinctrl-names = "default"; |
| 231 | pinctrl-0 = <&pcie0_pins>; |
| 232 | status = "okay"; |
| 233 | }; |
| 234 | |
| 235 | &wbsys { |
| 236 | mediatek,mtd-eeprom = <&factory 0x0000>; |
| 237 | status = "okay"; |
| 238 | }; |
| 239 | |
| 240 | &pio { |
| 241 | mmc0_pins_default: mmc0-pins-50-to-61-default { |
| 242 | mux { |
| 243 | function = "flash"; |
| 244 | groups = "emmc_51"; |
| 245 | }; |
| 246 | conf-cmd-dat { |
| 247 | pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", |
| 248 | "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", |
| 249 | "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; |
| 250 | input-enable; |
| 251 | drive-strength = <MTK_DRIVE_4mA>; |
| 252 | mediatek,pull-up-adv = <1>; /* pull-up 10K */ |
| 253 | }; |
| 254 | conf-clk { |
| 255 | pins = "EMMC_CK"; |
| 256 | drive-strength = <MTK_DRIVE_6mA>; |
| 257 | mediatek,pull-down-adv = <2>; /* pull-down 50K */ |
| 258 | }; |
| 259 | conf-ds { |
| 260 | pins = "EMMC_DSL"; |
| 261 | mediatek,pull-down-adv = <2>; /* pull-down 50K */ |
| 262 | }; |
| 263 | conf-rst { |
| 264 | pins = "EMMC_RSTB"; |
| 265 | drive-strength = <MTK_DRIVE_4mA>; |
| 266 | mediatek,pull-up-adv = <1>; /* pull-up 10K */ |
| 267 | }; |
| 268 | }; |
| 269 | |
| 270 | mmc0_pins_uhs: mmc0-pins-50-to-61-uhs { |
| 271 | mux { |
| 272 | function = "flash"; |
| 273 | groups = "emmc_51"; |
| 274 | }; |
| 275 | conf-cmd-dat { |
| 276 | pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", |
| 277 | "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", |
| 278 | "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; |
| 279 | input-enable; |
| 280 | drive-strength = <MTK_DRIVE_4mA>; |
| 281 | mediatek,pull-up-adv = <1>; /* pull-up 10K */ |
| 282 | }; |
| 283 | conf-clk { |
| 284 | pins = "EMMC_CK"; |
| 285 | drive-strength = <MTK_DRIVE_6mA>; |
| 286 | mediatek,pull-down-adv = <2>; /* pull-down 50K */ |
| 287 | }; |
| 288 | conf-ds { |
| 289 | pins = "EMMC_DSL"; |
| 290 | mediatek,pull-down-adv = <2>; /* pull-down 50K */ |
| 291 | }; |
| 292 | conf-rst { |
| 293 | pins = "EMMC_RSTB"; |
| 294 | drive-strength = <MTK_DRIVE_4mA>; |
| 295 | mediatek,pull-up-adv = <1>; /* pull-up 10K */ |
| 296 | }; |
| 297 | }; |
| 298 | }; |