blob: a050c885c2dd9ab5fd32738c09744f20975cbb1e [file] [log] [blame]
developer565bacb2021-09-28 21:26:32 +08001/dts-v1/;
2#include "mt7986a.dtsi"
3#include "mt7986a-pinctrl.dtsi"
4/ {
5 model = "MediaTek MT7986a RFB";
developer8262b0d2021-11-12 09:02:17 +08006 compatible = "mediatek,mt7986a-emmc-rfb";
developer565bacb2021-09-28 21:26:32 +08007 chosen {
8 bootargs = "console=ttyS0,115200n1 loglevel=8 \
9 earlycon=uart8250,mmio32,0x11002000 \
developer8262b0d2021-11-12 09:02:17 +080010 root=PARTLABEL=rootfs rootwait rootfstype=squashfs,f2fs";
developer565bacb2021-09-28 21:26:32 +080011 };
12
13 memory {
14 reg = <0 0x40000000 0 0x10000000>;
15 };
16
17 reg_1p8v: regulator-1p8v {
18 compatible = "regulator-fixed";
19 regulator-name = "fixed-1.8V";
20 regulator-min-microvolt = <1800000>;
21 regulator-max-microvolt = <1800000>;
22 regulator-boot-on;
23 regulator-always-on;
24 };
25
26 reg_3p3v: regulator-3p3v {
27 compatible = "regulator-fixed";
28 regulator-name = "fixed-3.3V";
29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <3300000>;
31 regulator-boot-on;
32 regulator-always-on;
33 };
34
35 sound {
36 compatible = "mediatek,mt7986-wm8960-machine";
37 mediatek,platform = <&afe>;
38 audio-routing = "Headphone", "HP_L",
39 "Headphone", "HP_R",
40 "LINPUT1", "AMIC",
41 "RINPUT1", "AMIC";
42 mediatek,audio-codec = <&wm8960>;
43 status = "okay";
44 };
45};
46
developer209e52d2022-06-30 11:32:57 +080047&fan {
48 pwms = <&pwm 1 50000 0>;
49 status = "disabled";
50};
51
developer565bacb2021-09-28 21:26:32 +080052&pwm {
53 pinctrl-names = "default";
54 pinctrl-0 = <&pwm0_pin &pwm1_pin_g1>;
55 status = "okay";
56};
57
58&uart0 {
59 status = "okay";
60};
61
62&uart1 {
63 pinctrl-names = "default";
64 pinctrl-0 = <&uart1_pins>;
65 status = "okay";
66};
67
68&uart2 {
69 pinctrl-names = "default";
70 pinctrl-0 = <&uart2_pins>;
developera2613e62022-07-01 18:29:37 +080071 status = "disabled";
developer565bacb2021-09-28 21:26:32 +080072};
73
74&i2c0 {
75 pinctrl-names = "default";
76 pinctrl-0 = <&i2c_pins>;
77 status = "okay";
78
79 wm8960: wm8960@1a {
80 compatible = "wlf,wm8960";
81 reg = <0x1a>;
82 };
83};
84
85&auxadc {
86 status = "okay";
87};
88
89&watchdog {
90 status = "okay";
91};
92
93&eth {
94 status = "okay";
95
96 gmac0: mac@0 {
97 compatible = "mediatek,eth-mac";
98 reg = <0>;
99 phy-mode = "2500base-x";
100
101 fixed-link {
102 speed = <2500>;
103 full-duplex;
104 pause;
developera2613e62022-07-01 18:29:37 +0800105 link-gpio = <&pio 47 0>;
106 phy-handle = <&phy5>;
107 label = "lan5";
developer565bacb2021-09-28 21:26:32 +0800108 };
109 };
110
111 gmac1: mac@1 {
112 compatible = "mediatek,eth-mac";
113 reg = <1>;
114 phy-mode = "2500base-x";
115
116 fixed-link {
117 speed = <2500>;
118 full-duplex;
119 pause;
developera2613e62022-07-01 18:29:37 +0800120 link-gpio = <&pio 46 0>;
121 phy-handle = <&phy6>;
developer565bacb2021-09-28 21:26:32 +0800122 };
123 };
124
125 mdio: mdio-bus {
126 #address-cells = <1>;
127 #size-cells = <0>;
128
129 phy5: phy@5 {
130 compatible = "ethernet-phy-id67c9.de0a";
131 reg = <5>;
132 reset-gpios = <&pio 6 1>;
developer8c5a08b2022-05-06 09:10:38 +0800133 reset-assert-us = <600>;
developer565bacb2021-09-28 21:26:32 +0800134 reset-deassert-us = <20000>;
135 phy-mode = "2500base-x";
136 };
137
138 phy6: phy@6 {
139 compatible = "ethernet-phy-id67c9.de0a";
140 reg = <6>;
141 phy-mode = "2500base-x";
142 };
143
144 switch@0 {
145 compatible = "mediatek,mt7531";
146 reg = <31>;
147 reset-gpios = <&pio 5 0>;
148
149 ports {
150 #address-cells = <1>;
151 #size-cells = <0>;
152
153 port@0 {
154 reg = <0>;
155 label = "lan0";
156 };
157
158 port@1 {
159 reg = <1>;
160 label = "lan1";
161 };
162
163 port@2 {
164 reg = <2>;
165 label = "lan2";
166 };
167
168 port@3 {
169 reg = <3>;
170 label = "lan3";
171 };
172
173 port@4 {
174 reg = <4>;
175 label = "lan4";
176 };
177
178 port@5 {
179 reg = <5>;
180 label = "lan5";
181 phy-mode = "2500base-x";
182
183 fixed-link {
184 speed = <2500>;
185 full-duplex;
186 pause;
187 };
188 };
189
190 port@6 {
191 reg = <6>;
192 label = "cpu";
193 ethernet = <&gmac0>;
194 phy-mode = "2500base-x";
195
196 fixed-link {
197 speed = <2500>;
198 full-duplex;
199 pause;
200 };
201 };
202 };
203 };
204 };
205};
206
207&hnat {
208 mtketh-wan = "eth1";
209 mtketh-lan = "lan";
210 mtketh-max-gmac = <2>;
211 status = "okay";
212};
213
214&spi1 {
215 pinctrl-names = "default";
216 pinctrl-0 = <&spic_pins_g2>;
217 status = "okay";
218};
219
220&mmc0 {
221 pinctrl-names = "default", "state_uhs";
222 pinctrl-0 = <&mmc0_pins_default>;
223 pinctrl-1 = <&mmc0_pins_uhs>;
224 bus-width = <8>;
225 max-frequency = <200000000>;
226 cap-mmc-highspeed;
227 mmc-hs200-1_8v;
228 mmc-hs400-1_8v;
229 hs400-ds-delay = <0x14014>;
230 vmmc-supply = <&reg_3p3v>;
231 vqmmc-supply = <&reg_1p8v>;
232 non-removable;
233 no-sd;
234 no-sdio;
235 status = "okay";
236};
237
238&pcie0 {
239 pinctrl-names = "default";
240 pinctrl-0 = <&pcie0_pins>;
241 status = "okay";
242};
243
244&wbsys {
245 mediatek,mtd-eeprom = <&factory 0x0000>;
246 status = "okay";
247};
248
249&pio {
250 mmc0_pins_default: mmc0-pins-50-to-61-default {
251 mux {
252 function = "flash";
253 groups = "emmc_51";
254 };
255 conf-cmd-dat {
256 pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
257 "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
258 "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
259 input-enable;
260 drive-strength = <MTK_DRIVE_4mA>;
261 mediatek,pull-up-adv = <1>; /* pull-up 10K */
262 };
263 conf-clk {
264 pins = "EMMC_CK";
265 drive-strength = <MTK_DRIVE_6mA>;
266 mediatek,pull-down-adv = <2>; /* pull-down 50K */
267 };
268 conf-ds {
269 pins = "EMMC_DSL";
270 mediatek,pull-down-adv = <2>; /* pull-down 50K */
271 };
272 conf-rst {
273 pins = "EMMC_RSTB";
274 drive-strength = <MTK_DRIVE_4mA>;
275 mediatek,pull-up-adv = <1>; /* pull-up 10K */
276 };
277 };
278
279 mmc0_pins_uhs: mmc0-pins-50-to-61-uhs {
280 mux {
281 function = "flash";
282 groups = "emmc_51";
283 };
284 conf-cmd-dat {
285 pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
286 "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
287 "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
288 input-enable;
289 drive-strength = <MTK_DRIVE_4mA>;
290 mediatek,pull-up-adv = <1>; /* pull-up 10K */
291 };
292 conf-clk {
293 pins = "EMMC_CK";
294 drive-strength = <MTK_DRIVE_6mA>;
295 mediatek,pull-down-adv = <2>; /* pull-down 50K */
296 };
297 conf-ds {
298 pins = "EMMC_DSL";
299 mediatek,pull-down-adv = <2>; /* pull-down 50K */
300 };
301 conf-rst {
302 pins = "EMMC_RSTB";
303 drive-strength = <MTK_DRIVE_4mA>;
304 mediatek,pull-up-adv = <1>; /* pull-up 10K */
305 };
306 };
307};