blob: c06aaae5f0dac25d8bc5f70ab944ef8db0e25a39 [file] [log] [blame]
developer565bacb2021-09-28 21:26:32 +08001/dts-v1/;
2#include "mt7986a.dtsi"
3#include "mt7986a-pinctrl.dtsi"
4/ {
5 model = "MediaTek MT7986a RFB";
developer8262b0d2021-11-12 09:02:17 +08006 compatible = "mediatek,mt7986a-emmc-rfb";
developer565bacb2021-09-28 21:26:32 +08007 chosen {
8 bootargs = "console=ttyS0,115200n1 loglevel=8 \
9 earlycon=uart8250,mmio32,0x11002000 \
developer8262b0d2021-11-12 09:02:17 +080010 root=PARTLABEL=rootfs rootwait rootfstype=squashfs,f2fs";
developer565bacb2021-09-28 21:26:32 +080011 };
12
13 memory {
14 reg = <0 0x40000000 0 0x10000000>;
15 };
16
17 reg_1p8v: regulator-1p8v {
18 compatible = "regulator-fixed";
19 regulator-name = "fixed-1.8V";
20 regulator-min-microvolt = <1800000>;
21 regulator-max-microvolt = <1800000>;
22 regulator-boot-on;
23 regulator-always-on;
24 };
25
26 reg_3p3v: regulator-3p3v {
27 compatible = "regulator-fixed";
28 regulator-name = "fixed-3.3V";
29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <3300000>;
31 regulator-boot-on;
32 regulator-always-on;
33 };
34
35 sound {
36 compatible = "mediatek,mt7986-wm8960-machine";
37 mediatek,platform = <&afe>;
38 audio-routing = "Headphone", "HP_L",
39 "Headphone", "HP_R",
40 "LINPUT1", "AMIC",
41 "RINPUT1", "AMIC";
42 mediatek,audio-codec = <&wm8960>;
43 status = "okay";
44 };
45};
46
developer209e52d2022-06-30 11:32:57 +080047&fan {
48 pwms = <&pwm 1 50000 0>;
49 status = "disabled";
50};
51
developer565bacb2021-09-28 21:26:32 +080052&pwm {
53 pinctrl-names = "default";
54 pinctrl-0 = <&pwm0_pin &pwm1_pin_g1>;
55 status = "okay";
56};
57
58&uart0 {
59 status = "okay";
60};
61
62&uart1 {
63 pinctrl-names = "default";
64 pinctrl-0 = <&uart1_pins>;
65 status = "okay";
66};
67
68&uart2 {
69 pinctrl-names = "default";
70 pinctrl-0 = <&uart2_pins>;
developera2613e62022-07-01 18:29:37 +080071 status = "disabled";
developer565bacb2021-09-28 21:26:32 +080072};
73
74&i2c0 {
75 pinctrl-names = "default";
76 pinctrl-0 = <&i2c_pins>;
77 status = "okay";
78
79 wm8960: wm8960@1a {
80 compatible = "wlf,wm8960";
81 reg = <0x1a>;
82 };
83};
84
85&auxadc {
86 status = "okay";
87};
88
89&watchdog {
90 status = "okay";
91};
92
93&eth {
94 status = "okay";
95
96 gmac0: mac@0 {
97 compatible = "mediatek,eth-mac";
98 reg = <0>;
99 phy-mode = "2500base-x";
developerf0a1e452022-08-15 12:06:11 +0800100 phy-handle = <&phy5>;
developer565bacb2021-09-28 21:26:32 +0800101 };
102
103 gmac1: mac@1 {
104 compatible = "mediatek,eth-mac";
105 reg = <1>;
106 phy-mode = "2500base-x";
developerf0a1e452022-08-15 12:06:11 +0800107 phy-handle = <&phy6>;
developer565bacb2021-09-28 21:26:32 +0800108 };
109
110 mdio: mdio-bus {
111 #address-cells = <1>;
112 #size-cells = <0>;
113
developerf0a1e452022-08-15 12:06:11 +0800114 reset-gpios = <&pio 6 1>;
115 reset-delay-us = <600>;
116
developer565bacb2021-09-28 21:26:32 +0800117 phy5: phy@5 {
developerf0a1e452022-08-15 12:06:11 +0800118 compatible = "ethernet-phy-ieee802.3-c45";
developer565bacb2021-09-28 21:26:32 +0800119 reg = <5>;
developer565bacb2021-09-28 21:26:32 +0800120 };
121
122 phy6: phy@6 {
developerf0a1e452022-08-15 12:06:11 +0800123 compatible = "ethernet-phy-ieee802.3-c45";
developer565bacb2021-09-28 21:26:32 +0800124 reg = <6>;
developer565bacb2021-09-28 21:26:32 +0800125 };
126
127 switch@0 {
128 compatible = "mediatek,mt7531";
129 reg = <31>;
130 reset-gpios = <&pio 5 0>;
131
132 ports {
133 #address-cells = <1>;
134 #size-cells = <0>;
135
136 port@0 {
137 reg = <0>;
138 label = "lan0";
139 };
140
141 port@1 {
142 reg = <1>;
143 label = "lan1";
144 };
145
146 port@2 {
147 reg = <2>;
148 label = "lan2";
149 };
150
151 port@3 {
152 reg = <3>;
153 label = "lan3";
154 };
155
156 port@4 {
157 reg = <4>;
158 label = "lan4";
159 };
160
161 port@5 {
162 reg = <5>;
163 label = "lan5";
164 phy-mode = "2500base-x";
165
166 fixed-link {
167 speed = <2500>;
168 full-duplex;
169 pause;
170 };
171 };
172
173 port@6 {
174 reg = <6>;
175 label = "cpu";
176 ethernet = <&gmac0>;
177 phy-mode = "2500base-x";
178
179 fixed-link {
180 speed = <2500>;
181 full-duplex;
182 pause;
183 };
184 };
185 };
186 };
187 };
188};
189
190&hnat {
191 mtketh-wan = "eth1";
192 mtketh-lan = "lan";
193 mtketh-max-gmac = <2>;
194 status = "okay";
195};
196
197&spi1 {
198 pinctrl-names = "default";
199 pinctrl-0 = <&spic_pins_g2>;
200 status = "okay";
201};
202
203&mmc0 {
204 pinctrl-names = "default", "state_uhs";
205 pinctrl-0 = <&mmc0_pins_default>;
206 pinctrl-1 = <&mmc0_pins_uhs>;
207 bus-width = <8>;
208 max-frequency = <200000000>;
209 cap-mmc-highspeed;
210 mmc-hs200-1_8v;
211 mmc-hs400-1_8v;
212 hs400-ds-delay = <0x14014>;
213 vmmc-supply = <&reg_3p3v>;
214 vqmmc-supply = <&reg_1p8v>;
215 non-removable;
216 no-sd;
217 no-sdio;
218 status = "okay";
219};
220
221&pcie0 {
222 pinctrl-names = "default";
223 pinctrl-0 = <&pcie0_pins>;
224 status = "okay";
225};
226
227&wbsys {
228 mediatek,mtd-eeprom = <&factory 0x0000>;
229 status = "okay";
230};
231
232&pio {
233 mmc0_pins_default: mmc0-pins-50-to-61-default {
234 mux {
235 function = "flash";
236 groups = "emmc_51";
237 };
238 conf-cmd-dat {
239 pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
240 "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
241 "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
242 input-enable;
243 drive-strength = <MTK_DRIVE_4mA>;
244 mediatek,pull-up-adv = <1>; /* pull-up 10K */
245 };
246 conf-clk {
247 pins = "EMMC_CK";
248 drive-strength = <MTK_DRIVE_6mA>;
249 mediatek,pull-down-adv = <2>; /* pull-down 50K */
250 };
251 conf-ds {
252 pins = "EMMC_DSL";
253 mediatek,pull-down-adv = <2>; /* pull-down 50K */
254 };
255 conf-rst {
256 pins = "EMMC_RSTB";
257 drive-strength = <MTK_DRIVE_4mA>;
258 mediatek,pull-up-adv = <1>; /* pull-up 10K */
259 };
260 };
261
262 mmc0_pins_uhs: mmc0-pins-50-to-61-uhs {
263 mux {
264 function = "flash";
265 groups = "emmc_51";
266 };
267 conf-cmd-dat {
268 pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
269 "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
270 "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
271 input-enable;
272 drive-strength = <MTK_DRIVE_4mA>;
273 mediatek,pull-up-adv = <1>; /* pull-up 10K */
274 };
275 conf-clk {
276 pins = "EMMC_CK";
277 drive-strength = <MTK_DRIVE_6mA>;
278 mediatek,pull-down-adv = <2>; /* pull-down 50K */
279 };
280 conf-ds {
281 pins = "EMMC_DSL";
282 mediatek,pull-down-adv = <2>; /* pull-down 50K */
283 };
284 conf-rst {
285 pins = "EMMC_RSTB";
286 drive-strength = <MTK_DRIVE_4mA>;
287 mediatek,pull-up-adv = <1>; /* pull-up 10K */
288 };
289 };
290};