developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1 | /* This program is free software; you can redistribute it and/or modify |
| 2 | * it under the terms of the GNU General Public License as published by |
| 3 | * the Free Software Foundation; version 2 of the License |
| 4 | * |
| 5 | * This program is distributed in the hope that it will be useful, |
| 6 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 7 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 8 | * GNU General Public License for more details. |
| 9 | * |
| 10 | * Copyright (C) 2014-2016 Sean Wang <sean.wang@mediatek.com> |
| 11 | * Copyright (C) 2016-2017 John Crispin <blogic@openwrt.org> |
| 12 | */ |
| 13 | |
| 14 | #include <linux/debugfs.h> |
| 15 | #include <linux/string.h> |
| 16 | #include <linux/if.h> |
| 17 | #include <linux/if_ether.h> |
| 18 | #include <net/netevent.h> |
| 19 | #include <linux/mod_devicetable.h> |
| 20 | #include "hnat_mcast.h" |
developer | e8b7dfa | 2023-04-20 10:16:44 +0800 | [diff] [blame] | 21 | #include "nf_hnat_mtk.h" |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 22 | |
| 23 | /*--------------------------------------------------------------------------*/ |
| 24 | /* Register Offset*/ |
| 25 | /*--------------------------------------------------------------------------*/ |
| 26 | #define PPE_GLO_CFG 0x00 |
| 27 | #define PPE_FLOW_CFG 0x04 |
| 28 | #define PPE_IP_PROT_CHK 0x08 |
| 29 | #define PPE_IP_PROT_0 0x0C |
| 30 | #define PPE_IP_PROT_1 0x10 |
| 31 | #define PPE_IP_PROT_2 0x14 |
| 32 | #define PPE_IP_PROT_3 0x18 |
| 33 | #define PPE_TB_CFG 0x1C |
| 34 | #define PPE_TB_BASE 0x20 |
| 35 | #define PPE_TB_USED 0x24 |
| 36 | #define PPE_BNDR 0x28 |
| 37 | #define PPE_BIND_LMT_0 0x2C |
| 38 | #define PPE_BIND_LMT_1 0x30 |
| 39 | #define PPE_KA 0x34 |
| 40 | #define PPE_UNB_AGE 0x38 |
| 41 | #define PPE_BND_AGE_0 0x3C |
| 42 | #define PPE_BND_AGE_1 0x40 |
| 43 | #define PPE_HASH_SEED 0x44 |
| 44 | #define PPE_DFT_CPORT 0x48 |
| 45 | #define PPE_DFT_CPORT1 0x4C |
| 46 | #define PPE_MCAST_PPSE 0x84 |
| 47 | #define PPE_MCAST_L_0 0x88 |
| 48 | #define PPE_MCAST_H_0 0x8C |
| 49 | #define PPE_MCAST_L_1 0x90 |
| 50 | #define PPE_MCAST_H_1 0x94 |
| 51 | #define PPE_MCAST_L_2 0x98 |
| 52 | #define PPE_MCAST_H_2 0x9C |
| 53 | #define PPE_MCAST_L_3 0xA0 |
| 54 | #define PPE_MCAST_H_3 0xA4 |
| 55 | #define PPE_MCAST_L_4 0xA8 |
| 56 | #define PPE_MCAST_H_4 0xAC |
| 57 | #define PPE_MCAST_L_5 0xB0 |
| 58 | #define PPE_MCAST_H_5 0xB4 |
| 59 | #define PPE_MCAST_L_6 0xBC |
| 60 | #define PPE_MCAST_H_6 0xC0 |
| 61 | #define PPE_MCAST_L_7 0xC4 |
| 62 | #define PPE_MCAST_H_7 0xC8 |
| 63 | #define PPE_MCAST_L_8 0xCC |
| 64 | #define PPE_MCAST_H_8 0xD0 |
| 65 | #define PPE_MCAST_L_9 0xD4 |
| 66 | #define PPE_MCAST_H_9 0xD8 |
| 67 | #define PPE_MCAST_L_A 0xDC |
| 68 | #define PPE_MCAST_H_A 0xE0 |
| 69 | #define PPE_MCAST_L_B 0xE4 |
| 70 | #define PPE_MCAST_H_B 0xE8 |
| 71 | #define PPE_MCAST_L_C 0xEC |
| 72 | #define PPE_MCAST_H_C 0xF0 |
| 73 | #define PPE_MCAST_L_D 0xF4 |
| 74 | #define PPE_MCAST_H_D 0xF8 |
| 75 | #define PPE_MCAST_L_E 0xFC |
| 76 | #define PPE_MCAST_H_E 0xE0 |
| 77 | #define PPE_MCAST_L_F 0x100 |
| 78 | #define PPE_MCAST_H_F 0x104 |
| 79 | #define PPE_MCAST_L_10 0xC00 |
| 80 | #define PPE_MCAST_H_10 0xC04 |
| 81 | #define PPE_MTU_DRP 0x108 |
| 82 | #define PPE_MTU_VLYR_0 0x10C |
| 83 | #define PPE_MTU_VLYR_1 0x110 |
| 84 | #define PPE_MTU_VLYR_2 0x114 |
| 85 | #define PPE_VPM_TPID 0x118 |
| 86 | #define PPE_CAH_CTRL 0x120 |
| 87 | #define PPE_CAH_TAG_SRH 0x124 |
| 88 | #define PPE_CAH_LINE_RW 0x128 |
| 89 | #define PPE_CAH_WDATA 0x12C |
| 90 | #define PPE_CAH_RDATA 0x130 |
| 91 | |
| 92 | #define PPE_MIB_CFG 0X134 |
| 93 | #define PPE_MIB_TB_BASE 0X138 |
| 94 | #define PPE_MIB_SER_CR 0X13C |
| 95 | #define PPE_MIB_SER_R0 0X140 |
| 96 | #define PPE_MIB_SER_R1 0X144 |
| 97 | #define PPE_MIB_SER_R2 0X148 |
developer | d35bbcc | 2022-09-28 22:46:01 +0800 | [diff] [blame] | 98 | #define PPE_MIB_SER_R3 0X14C |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 99 | #define PPE_MIB_CAH_CTRL 0X150 |
| 100 | #define PPE_MIB_CAH_TAG_SRH 0X154 |
| 101 | #define PPE_MIB_CAH_LINE_RW 0X158 |
| 102 | #define PPE_MIB_CAH_WDATA 0X15C |
| 103 | #define PPE_MIB_CAH_RDATA 0X160 |
developer | d35bbcc | 2022-09-28 22:46:01 +0800 | [diff] [blame] | 104 | #define PPE_SB_FIFO_DBG 0x170 |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 105 | #define PPE_SBW_CTRL 0x174 |
| 106 | |
| 107 | #define GDMA1_FWD_CFG 0x500 |
| 108 | #define GDMA2_FWD_CFG 0x1500 |
developer | d35bbcc | 2022-09-28 22:46:01 +0800 | [diff] [blame] | 109 | #define GDMA3_FWD_CFG 0x540 |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 110 | |
developer | 2494820 | 2021-11-24 17:38:27 +0800 | [diff] [blame] | 111 | /* QDMA Tx queue configuration */ |
developer | 70cdf6e | 2021-12-07 18:58:35 +0800 | [diff] [blame] | 112 | #define QTX_CFG(x) (QDMA_BASE + ((x) * 0x10)) |
| 113 | #define QTX_CFG_HW_RESV_CNT_OFFSET (8) |
| 114 | #define QTX_CFG_SW_RESV_CNT_OFFSET (0) |
| 115 | |
| 116 | #define QTX_SCH(x) (QDMA_BASE + 0x4 + ((x) * 0x10)) |
| 117 | #define QTX_SCH_MIN_RATE_EN BIT(27) |
| 118 | #define QTX_SCH_MAX_RATE_EN BIT(11) |
| 119 | #define QTX_SCH_MIN_RATE_MAN_OFFSET (20) |
| 120 | #define QTX_SCH_MIN_RATE_EXP_OFFSET (16) |
| 121 | #define QTX_SCH_MAX_RATE_WGHT_OFFSET (12) |
| 122 | #define QTX_SCH_MAX_RATE_MAN_OFFSET (4) |
| 123 | #define QTX_SCH_MAX_RATE_EXP_OFFSET (0) |
developer | 2494820 | 2021-11-24 17:38:27 +0800 | [diff] [blame] | 124 | |
| 125 | /* QDMA Tx scheduler configuration */ |
developer | 70cdf6e | 2021-12-07 18:58:35 +0800 | [diff] [blame] | 126 | #define QDMA_PAGE (QDMA_BASE + 0x1f0) |
| 127 | #define QDMA_TX_2SCH_BASE (QDMA_BASE + 0x214) |
| 128 | #define QTX_MIB_IF (QDMA_BASE + 0x2bc) |
| 129 | #define QDMA_TX_4SCH_BASE(x) (QDMA_BASE + 0x398 + (((x) >> 1) * 0x4)) |
developer | 34028fb | 2022-01-11 13:51:29 +0800 | [diff] [blame] | 130 | #define QDMA_TX_SCH_WFQ_EN BIT(15) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 131 | |
| 132 | /*--------------------------------------------------------------------------*/ |
| 133 | /* Register Mask*/ |
| 134 | /*--------------------------------------------------------------------------*/ |
| 135 | /* PPE_TB_CFG mask */ |
| 136 | #define TB_ETRY_NUM (0x7 << 0) /* RW */ |
| 137 | #define TB_ENTRY_SIZE (0x1 << 3) /* RW */ |
| 138 | #define SMA (0x3 << 4) /* RW */ |
| 139 | #define NTU_AGE (0x1 << 7) /* RW */ |
| 140 | #define UNBD_AGE (0x1 << 8) /* RW */ |
| 141 | #define TCP_AGE (0x1 << 9) /* RW */ |
| 142 | #define UDP_AGE (0x1 << 10) /* RW */ |
| 143 | #define FIN_AGE (0x1 << 11) /* RW */ |
| 144 | #define KA_CFG (0x3 << 12) |
| 145 | #define HASH_MODE (0x3 << 14) /* RW */ |
| 146 | #define SCAN_MODE (0x3 << 16) /* RW */ |
| 147 | #define XMODE (0x3 << 18) /* RW */ |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 148 | #define TICK_SEL (0x1 << 24) /* RW */ |
developer | 1a2d776 | 2023-09-21 22:15:12 +0800 | [diff] [blame] | 149 | #define DSCP_TRFC_ECN_EN (0x1 << 25) /* RW */ |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 150 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 151 | |
| 152 | /*PPE_CAH_CTRL mask*/ |
| 153 | #define CAH_EN (0x1 << 0) /* RW */ |
| 154 | #define CAH_X_MODE (0x1 << 9) /* RW */ |
| 155 | |
| 156 | /*PPE_UNB_AGE mask*/ |
| 157 | #define UNB_DLTA (0xff << 0) /* RW */ |
| 158 | #define UNB_MNP (0xffff << 16) /* RW */ |
| 159 | |
| 160 | /*PPE_BND_AGE_0 mask*/ |
| 161 | #define UDP_DLTA (0xffff << 0) /* RW */ |
| 162 | #define NTU_DLTA (0xffff << 16) /* RW */ |
| 163 | |
| 164 | /*PPE_BND_AGE_1 mask*/ |
| 165 | #define TCP_DLTA (0xffff << 0) /* RW */ |
| 166 | #define FIN_DLTA (0xffff << 16) /* RW */ |
| 167 | |
| 168 | /*PPE_KA mask*/ |
| 169 | #define KA_T (0xffff << 0) /* RW */ |
| 170 | #define TCP_KA (0xff << 16) /* RW */ |
| 171 | #define UDP_KA (0xff << 24) /* RW */ |
| 172 | |
| 173 | /*PPE_BIND_LMT_0 mask*/ |
| 174 | #define QURT_LMT (0x3ff << 0) /* RW */ |
| 175 | #define HALF_LMT (0x3ff << 16) /* RW */ |
| 176 | |
| 177 | /*PPE_BIND_LMT_1 mask*/ |
| 178 | #define FULL_LMT (0x3fff << 0) /* RW */ |
| 179 | #define NTU_KA (0xff << 16) /* RW */ |
| 180 | |
| 181 | /*PPE_BNDR mask*/ |
| 182 | #define BIND_RATE (0xffff << 0) /* RW */ |
| 183 | #define PBND_RD_PRD (0xffff << 16) /* RW */ |
| 184 | |
| 185 | /*PPE_GLO_CFG mask*/ |
| 186 | #define PPE_EN (0x1 << 0) /* RW */ |
developer | 1a2d776 | 2023-09-21 22:15:12 +0800 | [diff] [blame] | 187 | #define TSID_EN (0x1 << 1) /* RW */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 188 | #define TTL0_DRP (0x1 << 4) /* RW */ |
| 189 | #define MCAST_TB_EN (0x1 << 7) /* RW */ |
| 190 | #define MCAST_HASH (0x3 << 12) /* RW */ |
| 191 | |
| 192 | #define MC_P3_PPSE (0xf << 12) /* RW */ |
| 193 | #define MC_P2_PPSE (0xf << 8) /* RW */ |
| 194 | #define MC_P1_PPSE (0xf << 4) /* RW */ |
| 195 | #define MC_P0_PPSE (0xf << 0) /* RW */ |
| 196 | |
| 197 | #define MIB_EN (0x1 << 0) /* RW */ |
| 198 | #define MIB_READ_CLEAR (0X1 << 1) /* RW */ |
| 199 | #define MIB_CAH_EN (0X1 << 0) /* RW */ |
| 200 | |
| 201 | /*GDMA_FWD_CFG mask */ |
developer | d35bbcc | 2022-09-28 22:46:01 +0800 | [diff] [blame] | 202 | #define GDM_UFRC_MASK (0xF << 12) /* RW */ |
| 203 | #define GDM_BFRC_MASK (0xF << 8) /*RW*/ |
| 204 | #define GDM_MFRC_MASK (0xF << 4) /*RW*/ |
| 205 | #define GDM_OFRC_MASK (0xF << 0) /*RW*/ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 206 | #define GDM_ALL_FRC_MASK \ |
| 207 | (GDM_UFRC_MASK | GDM_BFRC_MASK | GDM_MFRC_MASK | GDM_OFRC_MASK) |
| 208 | |
| 209 | /*QDMA_PAGE mask*/ |
| 210 | #define QTX_CFG_PAGE (0xf << 0) /* RW */ |
| 211 | |
| 212 | /*QTX_MIB_IF mask*/ |
| 213 | #define MIB_ON_QTX_CFG (0x1 << 31) /* RW */ |
| 214 | #define VQTX_MIB_EN (0x1 << 28) /* RW */ |
| 215 | |
developer | d35bbcc | 2022-09-28 22:46:01 +0800 | [diff] [blame] | 216 | /* PPE Side Band FIFO Debug Mask */ |
| 217 | #define SB_MED_FULL_DRP_EN (0x1 << 11) |
| 218 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 219 | /*--------------------------------------------------------------------------*/ |
| 220 | /* Descriptor Structure */ |
| 221 | /*--------------------------------------------------------------------------*/ |
developer | d35bbcc | 2022-09-28 22:46:01 +0800 | [diff] [blame] | 222 | #if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 223 | struct hnat_unbind_info_blk { |
| 224 | u32 time_stamp : 8; |
| 225 | u32 sp : 4; |
| 226 | u32 pcnt : 8; |
| 227 | u32 ilgf : 1; |
| 228 | u32 mc : 1; |
| 229 | u32 preb : 1; |
| 230 | u32 pkt_type : 5; |
| 231 | u32 state : 2; |
| 232 | u32 udp : 1; |
| 233 | u32 sta : 1; /* static entry */ |
| 234 | } __packed; |
| 235 | |
| 236 | struct hnat_bind_info_blk { |
| 237 | u32 time_stamp : 8; |
| 238 | u32 sp : 4; |
| 239 | u32 mc : 1; |
| 240 | u32 ka : 1; /* keep alive */ |
| 241 | u32 vlan_layer : 3; |
| 242 | u32 psn : 1; /* egress packet has PPPoE session */ |
| 243 | u32 vpm : 1; /* 0:ethertype remark, 1:0x8100(CR default) */ |
| 244 | u32 ps : 1; /* packet sampling */ |
| 245 | u32 cah : 1; /* cacheable flag */ |
| 246 | u32 rmt : 1; /* remove tunnel ip header (6rd/dslite only) */ |
| 247 | u32 ttl : 1; |
| 248 | u32 pkt_type : 5; |
| 249 | u32 state : 2; |
| 250 | u32 udp : 1; |
| 251 | u32 sta : 1; /* static entry */ |
| 252 | } __packed; |
| 253 | |
| 254 | struct hnat_info_blk2 { |
| 255 | u32 qid : 7; /* QID in Qos Port */ |
| 256 | u32 port_mg : 1; |
| 257 | u32 fqos : 1; /* force to PSE QoS port */ |
| 258 | u32 dp : 4; /* force to PSE port x */ |
| 259 | u32 mcast : 1; /* multicast this packet to CPU */ |
| 260 | u32 pcpl : 1; /* OSBN */ |
| 261 | u32 mibf : 1; |
| 262 | u32 alen : 1; |
| 263 | u32 rxid : 2; |
| 264 | u32 winfoi : 1; |
| 265 | u32 port_ag : 4; |
| 266 | u32 dscp : 8; /* DSCP value */ |
| 267 | } __packed; |
| 268 | |
developer | d35bbcc | 2022-09-28 22:46:01 +0800 | [diff] [blame] | 269 | #if defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 270 | struct hnat_winfo { |
| 271 | u32 wcid : 16; /* WiFi wtable Idx */ |
| 272 | u32 bssid : 8; /* WiFi Bssidx */ |
| 273 | u32 resv : 8; |
| 274 | } __packed; |
| 275 | |
| 276 | struct hnat_winfo_pao { |
| 277 | u32 usr_info : 16; |
| 278 | u32 tid : 4; |
| 279 | u32 is_fixedrate : 1; |
| 280 | u32 is_prior : 1; |
| 281 | u32 is_sp : 1; |
| 282 | u32 hf : 1; |
| 283 | u32 amsdu : 1; |
| 284 | u32 resv : 7; |
| 285 | } __packed; |
| 286 | #elif defined(CONFIG_MEDIATEK_NETSYS_V2) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 287 | struct hnat_winfo { |
| 288 | u32 bssid : 6; /* WiFi Bssidx */ |
| 289 | u32 wcid : 10; /* WiFi wtable Idx */ |
| 290 | } __packed; |
developer | d35bbcc | 2022-09-28 22:46:01 +0800 | [diff] [blame] | 291 | #endif |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 292 | |
| 293 | #else |
| 294 | struct hnat_unbind_info_blk { |
| 295 | u32 time_stamp : 8; |
| 296 | u32 pcnt : 16; /* packet count */ |
| 297 | u32 preb : 1; |
| 298 | u32 pkt_type : 3; |
| 299 | u32 state : 2; |
| 300 | u32 udp : 1; |
| 301 | u32 sta : 1; /* static entry */ |
| 302 | } __packed; |
| 303 | |
| 304 | struct hnat_bind_info_blk { |
| 305 | u32 time_stamp : 15; |
| 306 | u32 ka : 1; /* keep alive */ |
| 307 | u32 vlan_layer : 3; |
| 308 | u32 psn : 1; /* egress packet has PPPoE session */ |
| 309 | u32 vpm : 1; /* 0:ethertype remark, 1:0x8100(CR default) */ |
| 310 | u32 ps : 1; /* packet sampling */ |
| 311 | u32 cah : 1; /* cacheable flag */ |
| 312 | u32 rmt : 1; /* remove tunnel ip header (6rd/dslite only) */ |
| 313 | u32 ttl : 1; |
| 314 | u32 pkt_type : 3; |
| 315 | u32 state : 2; |
| 316 | u32 udp : 1; |
| 317 | u32 sta : 1; /* static entry */ |
| 318 | } __packed; |
| 319 | |
| 320 | struct hnat_info_blk2 { |
| 321 | u32 qid : 4; /* QID in Qos Port */ |
| 322 | u32 fqos : 1; /* force to PSE QoS port */ |
| 323 | u32 dp : 3; /* force to PSE port x |
| 324 | * 0:PSE,1:GSW, 2:GMAC,4:PPE,5:QDMA,7=DROP |
| 325 | */ |
| 326 | u32 mcast : 1; /* multicast this packet to CPU */ |
| 327 | u32 pcpl : 1; /* OSBN */ |
| 328 | u32 mibf : 1; /* 0:off 1:on PPE MIB counter */ |
| 329 | u32 alen : 1; /* 0:post 1:pre packet length in accounting */ |
| 330 | u32 port_mg : 6; /* port meter group */ |
| 331 | u32 port_ag : 6; /* port account group */ |
| 332 | u32 dscp : 8; /* DSCP value */ |
| 333 | } __packed; |
| 334 | |
| 335 | struct hnat_winfo { |
| 336 | u32 bssid : 6; /* WiFi Bssidx */ |
| 337 | u32 wcid : 8; /* WiFi wtable Idx */ |
| 338 | u32 rxid : 2; /* WiFi Ring idx */ |
| 339 | } __packed; |
| 340 | #endif |
| 341 | |
| 342 | /* info blk2 for WHNAT */ |
| 343 | struct hnat_info_blk2_whnat { |
| 344 | u32 qid : 4; /* QID[3:0] in Qos Port */ |
| 345 | u32 fqos : 1; /* force to PSE QoS port */ |
| 346 | u32 dp : 3; /* force to PSE port x |
| 347 | * 0:PSE,1:GSW, 2:GMAC,4:PPE,5:QDMA,7=DROP |
| 348 | */ |
| 349 | u32 mcast : 1; /* multicast this packet to CPU */ |
| 350 | u32 pcpl : 1; /* OSBN */ |
| 351 | u32 mibf : 1; /* 0:off 1:on PPE MIB counter */ |
| 352 | u32 alen : 1; /* 0:post 1:pre packet length in accounting */ |
| 353 | u32 qid2 : 2; /* QID[5:4] in Qos Port */ |
| 354 | u32 resv : 2; |
| 355 | u32 wdmaid : 1; /* 0:to pcie0 dev 1:to pcie1 dev */ |
| 356 | u32 winfoi : 1; /* 0:off 1:on Wi-Fi hwnat support */ |
| 357 | u32 port_ag : 6; /* port account group */ |
| 358 | u32 dscp : 8; /* DSCP value */ |
| 359 | } __packed; |
| 360 | |
| 361 | struct hnat_ipv4_hnapt { |
| 362 | union { |
| 363 | struct hnat_bind_info_blk bfib1; |
| 364 | struct hnat_unbind_info_blk udib1; |
| 365 | u32 info_blk1; |
| 366 | }; |
| 367 | u32 sip; |
| 368 | u32 dip; |
| 369 | u16 dport; |
| 370 | u16 sport; |
| 371 | union { |
| 372 | struct hnat_info_blk2 iblk2; |
| 373 | struct hnat_info_blk2_whnat iblk2w; |
| 374 | u32 info_blk2; |
| 375 | }; |
| 376 | u32 new_sip; |
| 377 | u32 new_dip; |
| 378 | u16 new_dport; |
| 379 | u16 new_sport; |
| 380 | u16 m_timestamp; /* For mcast*/ |
| 381 | u16 resv1; |
| 382 | u32 resv2; |
developer | 1a2d776 | 2023-09-21 22:15:12 +0800 | [diff] [blame] | 383 | #if defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 384 | u32 resv3_1 : 9; |
| 385 | u32 eg_keep_ecn : 1; |
| 386 | u32 eg_keep_dscp : 1; |
| 387 | u32 resv3_2:15; |
| 388 | #else |
| 389 | u32 resv3:26; |
| 390 | #endif |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 391 | u32 act_dp : 6; /* UDF */ |
| 392 | u16 vlan1; |
| 393 | u16 etype; |
| 394 | u32 dmac_hi; |
| 395 | union { |
developer | d35bbcc | 2022-09-28 22:46:01 +0800 | [diff] [blame] | 396 | #if !defined(CONFIG_MEDIATEK_NETSYS_V2) && !defined(CONFIG_MEDIATEK_NETSYS_V3) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 397 | struct hnat_winfo winfo; |
| 398 | #endif |
| 399 | u16 vlan2; |
| 400 | }; |
| 401 | u16 dmac_lo; |
| 402 | u32 smac_hi; |
| 403 | u16 pppoe_id; |
| 404 | u16 smac_lo; |
developer | 22fd771 | 2022-10-06 14:13:52 +0800 | [diff] [blame] | 405 | #if defined(CONFIG_MEDIATEK_NETSYS_V3) |
developer | d35bbcc | 2022-09-28 22:46:01 +0800 | [diff] [blame] | 406 | u16 minfo; |
| 407 | u16 resv4; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 408 | struct hnat_winfo winfo; |
developer | d35bbcc | 2022-09-28 22:46:01 +0800 | [diff] [blame] | 409 | struct hnat_winfo_pao winfo_pao; |
| 410 | u32 cdrt_id : 8; |
| 411 | u32 tops_entry : 6; |
| 412 | u32 resv5 : 2; |
| 413 | u32 tport_id : 4; |
| 414 | u32 resv6 : 12; |
developer | 22fd771 | 2022-10-06 14:13:52 +0800 | [diff] [blame] | 415 | #elif defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 416 | u16 minfo; |
| 417 | struct hnat_winfo winfo; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 418 | #endif |
| 419 | } __packed; |
| 420 | |
| 421 | struct hnat_ipv4_dslite { |
| 422 | union { |
| 423 | struct hnat_bind_info_blk bfib1; |
| 424 | struct hnat_unbind_info_blk udib1; |
| 425 | u32 info_blk1; |
| 426 | }; |
| 427 | u32 sip; |
| 428 | u32 dip; |
| 429 | u16 dport; |
| 430 | u16 sport; |
| 431 | |
| 432 | u32 tunnel_sipv6_0; |
| 433 | u32 tunnel_sipv6_1; |
| 434 | u32 tunnel_sipv6_2; |
| 435 | u32 tunnel_sipv6_3; |
| 436 | |
| 437 | u32 tunnel_dipv6_0; |
| 438 | u32 tunnel_dipv6_1; |
| 439 | u32 tunnel_dipv6_2; |
| 440 | u32 tunnel_dipv6_3; |
| 441 | |
| 442 | u8 flow_lbl[3]; /* in order to consist with Linux kernel (should be 20bits) */ |
| 443 | u8 priority; /* in order to consist with Linux kernel (should be 8bits) */ |
| 444 | u32 hop_limit : 8; |
developer | 1a2d776 | 2023-09-21 22:15:12 +0800 | [diff] [blame] | 445 | #if defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 446 | u32 resv2_1 : 1; |
| 447 | u32 eg_keep_ecn : 1; |
| 448 | u32 eg_keep_cls : 1; |
| 449 | u32 resv2_2 : 15; |
| 450 | #else |
| 451 | u32 resv2 : 18; |
| 452 | #endif |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 453 | u32 act_dp : 6; /* UDF */ |
| 454 | |
| 455 | union { |
| 456 | struct hnat_info_blk2 iblk2; |
| 457 | struct hnat_info_blk2_whnat iblk2w; |
| 458 | u32 info_blk2; |
| 459 | }; |
| 460 | |
| 461 | u16 vlan1; |
| 462 | u16 etype; |
| 463 | u32 dmac_hi; |
| 464 | union { |
developer | d35bbcc | 2022-09-28 22:46:01 +0800 | [diff] [blame] | 465 | #if !defined(CONFIG_MEDIATEK_NETSYS_V2) && !defined(CONFIG_MEDIATEK_NETSYS_V3) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 466 | struct hnat_winfo winfo; |
| 467 | #endif |
| 468 | u16 vlan2; |
| 469 | }; |
| 470 | u16 dmac_lo; |
| 471 | u32 smac_hi; |
| 472 | u16 pppoe_id; |
| 473 | u16 smac_lo; |
developer | 22fd771 | 2022-10-06 14:13:52 +0800 | [diff] [blame] | 474 | #if defined(CONFIG_MEDIATEK_NETSYS_V3) |
developer | d35bbcc | 2022-09-28 22:46:01 +0800 | [diff] [blame] | 475 | u16 minfo; |
| 476 | u16 resv3; |
| 477 | struct hnat_winfo winfo; |
| 478 | struct hnat_winfo_pao winfo_pao; |
| 479 | u32 cdrt_id : 8; |
| 480 | u32 tops_entry : 6; |
| 481 | u32 resv4 : 2; |
| 482 | u32 tport_id : 4; |
| 483 | u32 resv5 : 12; |
developer | 22fd771 | 2022-10-06 14:13:52 +0800 | [diff] [blame] | 484 | #elif defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 485 | u16 minfo; |
| 486 | struct hnat_winfo winfo; |
developer | d35bbcc | 2022-09-28 22:46:01 +0800 | [diff] [blame] | 487 | #endif |
| 488 | } __packed; |
| 489 | |
| 490 | struct hnat_ipv4_mape { |
| 491 | union { |
| 492 | struct hnat_bind_info_blk bfib1; |
| 493 | struct hnat_unbind_info_blk udib1; |
| 494 | u32 info_blk1; |
| 495 | }; |
| 496 | u32 sip; |
| 497 | u32 dip; |
| 498 | u16 dport; |
| 499 | u16 sport; |
| 500 | |
| 501 | u32 tunnel_sipv6_0; |
| 502 | u32 tunnel_sipv6_1; |
| 503 | u32 tunnel_sipv6_2; |
| 504 | u32 tunnel_sipv6_3; |
| 505 | |
| 506 | u32 tunnel_dipv6_0; |
| 507 | u32 tunnel_dipv6_1; |
| 508 | u32 tunnel_dipv6_2; |
| 509 | u32 tunnel_dipv6_3; |
| 510 | |
| 511 | u8 flow_lbl[3]; /* in order to consist with Linux kernel (should be 20bits) */ |
| 512 | u8 priority; /* in order to consist with Linux kernel (should be 8bits) */ |
| 513 | u32 hop_limit : 8; |
developer | 1a2d776 | 2023-09-21 22:15:12 +0800 | [diff] [blame] | 514 | #if defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 515 | u32 resv2_1 : 1; |
| 516 | u32 eg_keep_ecn : 1; |
| 517 | u32 eg_keep_dscp : 1; |
| 518 | u32 resv2_2 : 15; |
| 519 | #else |
developer | d35bbcc | 2022-09-28 22:46:01 +0800 | [diff] [blame] | 520 | u32 resv2 : 18; |
developer | 1a2d776 | 2023-09-21 22:15:12 +0800 | [diff] [blame] | 521 | #endif |
developer | d35bbcc | 2022-09-28 22:46:01 +0800 | [diff] [blame] | 522 | u32 act_dp : 6; /* UDF */ |
| 523 | |
| 524 | union { |
| 525 | struct hnat_info_blk2 iblk2; |
| 526 | struct hnat_info_blk2_whnat iblk2w; |
| 527 | u32 info_blk2; |
| 528 | }; |
| 529 | |
| 530 | u16 vlan1; |
| 531 | u16 etype; |
| 532 | u32 dmac_hi; |
| 533 | union { |
| 534 | #if !defined(CONFIG_MEDIATEK_NETSYS_V2) && !defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 535 | struct hnat_winfo winfo; |
| 536 | #endif |
| 537 | u16 vlan2; |
| 538 | }; |
| 539 | u16 dmac_lo; |
| 540 | u32 smac_hi; |
| 541 | u16 pppoe_id; |
| 542 | u16 smac_lo; |
developer | 22fd771 | 2022-10-06 14:13:52 +0800 | [diff] [blame] | 543 | #if defined(CONFIG_MEDIATEK_NETSYS_V3) |
developer | d35bbcc | 2022-09-28 22:46:01 +0800 | [diff] [blame] | 544 | u16 minfo; |
| 545 | u16 resv3; |
| 546 | u32 new_sip; |
| 547 | u32 new_dip; |
| 548 | u16 new_dport; |
| 549 | u16 new_sport; |
| 550 | struct hnat_winfo winfo; |
| 551 | struct hnat_winfo_pao winfo_pao; |
| 552 | u32 cdrt_id : 8; |
| 553 | u32 tops_entry : 6; |
| 554 | u32 resv4 : 2; |
| 555 | u32 tport_id : 4; |
| 556 | u32 resv5 : 12; |
developer | 22fd771 | 2022-10-06 14:13:52 +0800 | [diff] [blame] | 557 | #elif defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 558 | u16 minfo; |
| 559 | struct hnat_winfo winfo; |
| 560 | u32 new_sip; |
| 561 | u32 new_dip; |
| 562 | u16 new_dport; |
| 563 | u16 new_sport; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 564 | #endif |
| 565 | } __packed; |
| 566 | |
| 567 | struct hnat_ipv6_3t_route { |
| 568 | union { |
| 569 | struct hnat_bind_info_blk bfib1; |
| 570 | struct hnat_unbind_info_blk udib1; |
| 571 | u32 info_blk1; |
| 572 | }; |
| 573 | u32 ipv6_sip0; |
| 574 | u32 ipv6_sip1; |
| 575 | u32 ipv6_sip2; |
| 576 | u32 ipv6_sip3; |
| 577 | u32 ipv6_dip0; |
| 578 | u32 ipv6_dip1; |
| 579 | u32 ipv6_dip2; |
| 580 | u32 ipv6_dip3; |
| 581 | u32 prot : 8; |
developer | 729f027 | 2021-06-09 17:28:38 +0800 | [diff] [blame] | 582 | u32 hph : 24; /* hash placeholder */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 583 | |
| 584 | u32 resv1; |
| 585 | u32 resv2; |
| 586 | u32 resv3; |
developer | 1a2d776 | 2023-09-21 22:15:12 +0800 | [diff] [blame] | 587 | #if defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 588 | u32 resv4_1 : 9; |
| 589 | u32 eg_keep_ecn : 1; |
| 590 | u32 eg_keep_cls : 1; |
| 591 | u32 resv4_2 : 15; |
| 592 | #else |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 593 | u32 resv4 : 26; |
developer | 1a2d776 | 2023-09-21 22:15:12 +0800 | [diff] [blame] | 594 | #endif |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 595 | u32 act_dp : 6; /* UDF */ |
| 596 | |
| 597 | union { |
| 598 | struct hnat_info_blk2 iblk2; |
| 599 | struct hnat_info_blk2_whnat iblk2w; |
| 600 | u32 info_blk2; |
| 601 | }; |
| 602 | u16 vlan1; |
| 603 | u16 etype; |
| 604 | u32 dmac_hi; |
| 605 | union { |
developer | d35bbcc | 2022-09-28 22:46:01 +0800 | [diff] [blame] | 606 | #if !defined(CONFIG_MEDIATEK_NETSYS_V2) && !defined(CONFIG_MEDIATEK_NETSYS_V3) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 607 | struct hnat_winfo winfo; |
| 608 | #endif |
| 609 | u16 vlan2; |
| 610 | }; |
| 611 | u16 dmac_lo; |
| 612 | u32 smac_hi; |
| 613 | u16 pppoe_id; |
| 614 | u16 smac_lo; |
developer | 22fd771 | 2022-10-06 14:13:52 +0800 | [diff] [blame] | 615 | #if defined(CONFIG_MEDIATEK_NETSYS_V3) |
developer | d35bbcc | 2022-09-28 22:46:01 +0800 | [diff] [blame] | 616 | u16 minfo; |
| 617 | u16 resv5; |
| 618 | struct hnat_winfo winfo; |
| 619 | struct hnat_winfo_pao winfo_pao; |
| 620 | u32 cdrt_id : 8; |
| 621 | u32 tops_entry : 6; |
| 622 | u32 resv6 : 2; |
| 623 | u32 tport_id : 4; |
| 624 | u32 resv7 : 12; |
developer | 22fd771 | 2022-10-06 14:13:52 +0800 | [diff] [blame] | 625 | #elif defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 626 | u16 minfo; |
| 627 | struct hnat_winfo winfo; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 628 | #endif |
| 629 | } __packed; |
| 630 | |
| 631 | struct hnat_ipv6_5t_route { |
| 632 | union { |
| 633 | struct hnat_bind_info_blk bfib1; |
| 634 | struct hnat_unbind_info_blk udib1; |
| 635 | u32 info_blk1; |
| 636 | }; |
| 637 | u32 ipv6_sip0; |
| 638 | u32 ipv6_sip1; |
| 639 | u32 ipv6_sip2; |
| 640 | u32 ipv6_sip3; |
| 641 | u32 ipv6_dip0; |
| 642 | u32 ipv6_dip1; |
| 643 | u32 ipv6_dip2; |
| 644 | u32 ipv6_dip3; |
| 645 | u16 dport; |
| 646 | u16 sport; |
| 647 | |
| 648 | u32 resv1; |
| 649 | u32 resv2; |
| 650 | u32 resv3; |
developer | 1a2d776 | 2023-09-21 22:15:12 +0800 | [diff] [blame] | 651 | #if defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 652 | u32 resv4_1 : 9; |
| 653 | u32 eg_keep_ecn : 1; |
| 654 | u32 eg_keep_cls : 1; |
| 655 | u32 resv4_2 : 15; |
| 656 | #else |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 657 | u32 resv4 : 26; |
developer | 1a2d776 | 2023-09-21 22:15:12 +0800 | [diff] [blame] | 658 | #endif |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 659 | u32 act_dp : 6; /* UDF */ |
| 660 | |
| 661 | union { |
| 662 | struct hnat_info_blk2 iblk2; |
| 663 | struct hnat_info_blk2_whnat iblk2w; |
| 664 | u32 info_blk2; |
| 665 | }; |
| 666 | |
| 667 | u16 vlan1; |
| 668 | u16 etype; |
| 669 | u32 dmac_hi; |
| 670 | union { |
developer | d35bbcc | 2022-09-28 22:46:01 +0800 | [diff] [blame] | 671 | #if !defined(CONFIG_MEDIATEK_NETSYS_V2) && !defined(CONFIG_MEDIATEK_NETSYS_V3) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 672 | struct hnat_winfo winfo; |
| 673 | #endif |
| 674 | u16 vlan2; |
| 675 | }; |
| 676 | u16 dmac_lo; |
| 677 | u32 smac_hi; |
| 678 | u16 pppoe_id; |
| 679 | u16 smac_lo; |
developer | 22fd771 | 2022-10-06 14:13:52 +0800 | [diff] [blame] | 680 | #if defined(CONFIG_MEDIATEK_NETSYS_V3) |
developer | d35bbcc | 2022-09-28 22:46:01 +0800 | [diff] [blame] | 681 | u16 minfo; |
| 682 | u16 resv5; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 683 | struct hnat_winfo winfo; |
developer | d35bbcc | 2022-09-28 22:46:01 +0800 | [diff] [blame] | 684 | struct hnat_winfo_pao winfo_pao; |
| 685 | u32 cdrt_id : 8; |
| 686 | u32 tops_entry : 6; |
| 687 | u32 resv6 : 2; |
| 688 | u32 tport_id : 4; |
| 689 | u32 resv7 : 12; |
developer | 22fd771 | 2022-10-06 14:13:52 +0800 | [diff] [blame] | 690 | #elif defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 691 | u16 minfo; |
| 692 | struct hnat_winfo winfo; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 693 | #endif |
| 694 | } __packed; |
| 695 | |
| 696 | struct hnat_ipv6_6rd { |
| 697 | union { |
| 698 | struct hnat_bind_info_blk bfib1; |
| 699 | struct hnat_unbind_info_blk udib1; |
| 700 | u32 info_blk1; |
| 701 | }; |
| 702 | u32 ipv6_sip0; |
| 703 | u32 ipv6_sip1; |
| 704 | u32 ipv6_sip2; |
| 705 | u32 ipv6_sip3; |
| 706 | u32 ipv6_dip0; |
| 707 | u32 ipv6_dip1; |
| 708 | u32 ipv6_dip2; |
| 709 | u32 ipv6_dip3; |
| 710 | u16 dport; |
| 711 | u16 sport; |
| 712 | |
| 713 | u32 tunnel_sipv4; |
| 714 | u32 tunnel_dipv4; |
| 715 | u32 hdr_chksum : 16; |
| 716 | u32 dscp : 8; |
| 717 | u32 ttl : 8; |
| 718 | u32 flag : 3; |
developer | 1a2d776 | 2023-09-21 22:15:12 +0800 | [diff] [blame] | 719 | #if defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 720 | u32 resv1_1 : 6; |
| 721 | u32 eg_keep_ecn : 1; |
| 722 | u32 eg_keep_cls : 1; |
| 723 | u32 eg_keep_tnl_qos : 1; |
| 724 | u32 resv1_2 : 4; |
| 725 | u32 per_flow_6rd_id : 1; |
| 726 | u32 resv2 : 9; |
| 727 | #else |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 728 | u32 resv1 : 13; |
| 729 | u32 per_flow_6rd_id : 1; |
| 730 | u32 resv2 : 9; |
developer | 1a2d776 | 2023-09-21 22:15:12 +0800 | [diff] [blame] | 731 | #endif |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 732 | u32 act_dp : 6; /* UDF */ |
| 733 | |
| 734 | union { |
| 735 | struct hnat_info_blk2 iblk2; |
| 736 | struct hnat_info_blk2_whnat iblk2w; |
| 737 | u32 info_blk2; |
| 738 | }; |
| 739 | |
| 740 | u16 vlan1; |
| 741 | u16 etype; |
| 742 | u32 dmac_hi; |
| 743 | union { |
developer | d35bbcc | 2022-09-28 22:46:01 +0800 | [diff] [blame] | 744 | #if !defined(CONFIG_MEDIATEK_NETSYS_V2) && !defined(CONFIG_MEDIATEK_NETSYS_V3) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 745 | struct hnat_winfo winfo; |
| 746 | #endif |
| 747 | u16 vlan2; |
| 748 | }; |
| 749 | u16 dmac_lo; |
| 750 | u32 smac_hi; |
| 751 | u16 pppoe_id; |
| 752 | u16 smac_lo; |
developer | 22fd771 | 2022-10-06 14:13:52 +0800 | [diff] [blame] | 753 | #if defined(CONFIG_MEDIATEK_NETSYS_V3) |
developer | d35bbcc | 2022-09-28 22:46:01 +0800 | [diff] [blame] | 754 | u16 minfo; |
| 755 | u16 resv3; |
| 756 | struct hnat_winfo winfo; |
| 757 | struct hnat_winfo_pao winfo_pao; |
| 758 | u32 cdrt_id : 8; |
| 759 | u32 tops_entry : 6; |
| 760 | u32 resv4 : 2; |
| 761 | u32 tport_id : 4; |
| 762 | u32 resv5 : 12; |
developer | 22fd771 | 2022-10-06 14:13:52 +0800 | [diff] [blame] | 763 | #elif defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 764 | u16 minfo; |
| 765 | struct hnat_winfo winfo; |
developer | 5ffc5f1 | 2022-10-25 18:51:46 +0800 | [diff] [blame] | 766 | #endif |
| 767 | } __packed; |
| 768 | |
| 769 | struct hnat_ipv6_hnapt { |
| 770 | union { |
| 771 | struct hnat_bind_info_blk bfib1; |
| 772 | struct hnat_unbind_info_blk udib1; |
| 773 | u32 info_blk1; |
| 774 | }; |
| 775 | u32 ipv6_sip0; |
| 776 | u32 ipv6_sip1; |
| 777 | u32 ipv6_sip2; |
| 778 | u32 ipv6_sip3; |
| 779 | u32 ipv6_dip0; |
| 780 | u32 ipv6_dip1; |
| 781 | u32 ipv6_dip2; |
| 782 | u32 ipv6_dip3; |
| 783 | u16 dport; |
| 784 | u16 sport; |
| 785 | |
| 786 | u32 resv1; |
| 787 | u32 resv2; |
developer | 22fd771 | 2022-10-06 14:13:52 +0800 | [diff] [blame] | 788 | u32 resv3; |
developer | 5ffc5f1 | 2022-10-25 18:51:46 +0800 | [diff] [blame] | 789 | u32 resv4 : 8; |
| 790 | u32 eg_ipv6_dir : 1; |
| 791 | u32 eg_keep_ecn : 1; |
| 792 | u32 eg_keep_cls : 1; |
| 793 | u32 resv5 : 15; |
| 794 | u32 act_dp : 6; /* UDF */ |
| 795 | |
| 796 | union { |
| 797 | struct hnat_info_blk2 iblk2; |
| 798 | struct hnat_info_blk2_whnat iblk2w; |
| 799 | u32 info_blk2; |
| 800 | }; |
| 801 | |
| 802 | u16 vlan1; |
| 803 | u16 etype; |
| 804 | u32 dmac_hi; |
| 805 | u16 vlan2; |
| 806 | u16 dmac_lo; |
| 807 | u32 smac_hi; |
| 808 | u16 pppoe_id; |
| 809 | u16 smac_lo; |
| 810 | #if defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 811 | u16 minfo; |
| 812 | u16 resv6; |
| 813 | u32 new_ipv6_ip0; |
| 814 | u32 new_ipv6_ip1; |
| 815 | u32 new_ipv6_ip2; |
| 816 | u32 new_ipv6_ip3; |
developer | 22fd771 | 2022-10-06 14:13:52 +0800 | [diff] [blame] | 817 | u16 new_dport; |
| 818 | u16 new_sport; |
developer | 5ffc5f1 | 2022-10-25 18:51:46 +0800 | [diff] [blame] | 819 | struct hnat_winfo winfo; |
| 820 | struct hnat_winfo_pao winfo_pao; |
| 821 | u32 cdrt_id : 8; |
| 822 | u32 tops_entry : 6; |
| 823 | u32 resv7 : 2; |
| 824 | u32 tport_id : 4; |
| 825 | u32 resv8 : 12; |
| 826 | u32 resv9; |
| 827 | u32 resv10; |
| 828 | u32 resv11; |
| 829 | #elif defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 830 | u16 minfo; |
| 831 | struct hnat_winfo winfo; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 832 | #endif |
| 833 | } __packed; |
| 834 | |
| 835 | struct foe_entry { |
| 836 | union { |
| 837 | struct hnat_unbind_info_blk udib1; |
| 838 | struct hnat_bind_info_blk bfib1; |
| 839 | struct hnat_ipv4_hnapt ipv4_hnapt; |
| 840 | struct hnat_ipv4_dslite ipv4_dslite; |
developer | d35bbcc | 2022-09-28 22:46:01 +0800 | [diff] [blame] | 841 | struct hnat_ipv4_mape ipv4_mape; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 842 | struct hnat_ipv6_3t_route ipv6_3t_route; |
| 843 | struct hnat_ipv6_5t_route ipv6_5t_route; |
| 844 | struct hnat_ipv6_6rd ipv6_6rd; |
developer | 5ffc5f1 | 2022-10-25 18:51:46 +0800 | [diff] [blame] | 845 | struct hnat_ipv6_hnapt ipv6_hnapt; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 846 | }; |
| 847 | }; |
| 848 | |
| 849 | /* If user wants to change default FOE entry number, both DEF_ETRY_NUM and |
| 850 | * DEF_ETRY_NUM_CFG need to be modified. |
| 851 | */ |
| 852 | #define DEF_ETRY_NUM 8192 |
developer | bc53e5f | 2021-05-21 10:07:17 +0800 | [diff] [blame] | 853 | /* feasible values : 32768, 16384, 8192, 4096, 2048, 1024 */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 854 | #define DEF_ETRY_NUM_CFG TABLE_8K |
developer | bc53e5f | 2021-05-21 10:07:17 +0800 | [diff] [blame] | 855 | /* corresponding values : TABLE_32K, TABLE_16K, TABLE_8K, TABLE_4K, TABLE_2K, |
| 856 | * TABLE_1K |
| 857 | */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 858 | #define MAX_EXT_DEVS (0x3fU) |
| 859 | #define MAX_IF_NUM 64 |
| 860 | |
developer | d35bbcc | 2022-09-28 22:46:01 +0800 | [diff] [blame] | 861 | #if defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 862 | #define MAX_PPE_NUM 3 |
| 863 | #elif defined(CONFIG_MEDIATEK_NETSYS_V2) |
developer | 471f656 | 2021-05-10 20:48:34 +0800 | [diff] [blame] | 864 | #define MAX_PPE_NUM 2 |
| 865 | #else |
| 866 | #define MAX_PPE_NUM 1 |
| 867 | #endif |
| 868 | #define CFG_PPE_NUM (hnat_priv->ppe_num) |
| 869 | |
developer | 0efc7d6 | 2023-11-15 16:26:42 +0800 | [diff] [blame] | 870 | /* If the user wants to set skb->mark to prevent hardware acceleration |
| 871 | * for the packet flow. |
| 872 | */ |
| 873 | #define HNAT_EXCEPTION_TAG 0x99 |
| 874 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 875 | struct mib_entry { |
| 876 | u32 byt_cnt_l; |
| 877 | u16 byt_cnt_h; |
| 878 | u32 pkt_cnt_l; |
| 879 | u8 pkt_cnt_h; |
| 880 | u8 resv0; |
| 881 | u32 resv1; |
| 882 | } __packed; |
| 883 | |
| 884 | struct hnat_accounting { |
| 885 | u64 bytes; |
| 886 | u64 packets; |
| 887 | }; |
| 888 | |
| 889 | enum mtk_hnat_version { |
developer | 4164cfe | 2022-12-01 11:27:41 +0800 | [diff] [blame] | 890 | MTK_HNAT_V1_1 = 1, /* version 1.1: mt7621, mt7623 */ |
| 891 | MTK_HNAT_V1_2, /* version 1.2: mt7622 */ |
| 892 | MTK_HNAT_V1_3, /* version 1.3: mt7629 */ |
| 893 | MTK_HNAT_V2, /* version 2: mt7981, mt7986 */ |
| 894 | MTK_HNAT_V3, /* version 3: mt7988 */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 895 | }; |
| 896 | |
| 897 | struct mtk_hnat_data { |
| 898 | u8 num_of_sch; |
| 899 | bool whnat; |
| 900 | bool per_flow_accounting; |
| 901 | bool mcast; |
| 902 | enum mtk_hnat_version version; |
| 903 | }; |
| 904 | |
developer | e8b7dfa | 2023-04-20 10:16:44 +0800 | [diff] [blame] | 905 | struct map46 { |
| 906 | u32 ipv4; |
| 907 | struct in6_addr ipv6; |
| 908 | struct list_head list; |
| 909 | }; |
| 910 | |
| 911 | struct xlat_conf { |
| 912 | struct list_head map_list; |
| 913 | struct in6_addr prefix; |
| 914 | int prefix_len; |
| 915 | }; |
| 916 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 917 | struct mtk_hnat { |
| 918 | struct device *dev; |
| 919 | void __iomem *fe_base; |
developer | 471f656 | 2021-05-10 20:48:34 +0800 | [diff] [blame] | 920 | void __iomem *ppe_base[MAX_PPE_NUM]; |
| 921 | struct foe_entry *foe_table_cpu[MAX_PPE_NUM]; |
| 922 | dma_addr_t foe_table_dev[MAX_PPE_NUM]; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 923 | u8 enable; |
| 924 | u8 enable1; |
| 925 | struct dentry *root; |
developer | 471f656 | 2021-05-10 20:48:34 +0800 | [diff] [blame] | 926 | struct debugfs_regset32 *regset[MAX_PPE_NUM]; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 927 | |
developer | 471f656 | 2021-05-10 20:48:34 +0800 | [diff] [blame] | 928 | struct mib_entry *foe_mib_cpu[MAX_PPE_NUM]; |
| 929 | dma_addr_t foe_mib_dev[MAX_PPE_NUM]; |
| 930 | struct hnat_accounting *acct[MAX_PPE_NUM]; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 931 | const struct mtk_hnat_data *data; |
| 932 | |
| 933 | /*devices we plays for*/ |
| 934 | char wan[IFNAMSIZ]; |
| 935 | char lan[IFNAMSIZ]; |
developer | d35bbcc | 2022-09-28 22:46:01 +0800 | [diff] [blame] | 936 | char lan2[IFNAMSIZ]; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 937 | char ppd[IFNAMSIZ]; |
| 938 | u16 lvid; |
| 939 | u16 wvid; |
| 940 | |
| 941 | struct reset_control *rstc; |
| 942 | |
developer | 471f656 | 2021-05-10 20:48:34 +0800 | [diff] [blame] | 943 | u8 ppe_num; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 944 | u8 gmac_num; |
| 945 | u8 wan_dsa_port; |
| 946 | struct ppe_mcast_table *pmcast; |
| 947 | |
| 948 | u32 foe_etry_num; |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 949 | u32 etry_num_cfg; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 950 | struct net_device *g_ppdev; |
developer | 8c9c0d0 | 2021-06-18 16:15:37 +0800 | [diff] [blame] | 951 | struct net_device *g_wandev; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 952 | struct net_device *wifi_hook_if[MAX_IF_NUM]; |
| 953 | struct extdev_entry *ext_if[MAX_EXT_DEVS]; |
| 954 | struct timer_list hnat_sma_build_entry_timer; |
| 955 | struct timer_list hnat_reset_timestamp_timer; |
| 956 | struct timer_list hnat_mcast_check_timer; |
developer | 30a4768 | 2021-11-02 17:06:14 +0800 | [diff] [blame] | 957 | bool nf_stat_en; |
developer | e8b7dfa | 2023-04-20 10:16:44 +0800 | [diff] [blame] | 958 | struct xlat_conf xlat; |
developer | 1a2d776 | 2023-09-21 22:15:12 +0800 | [diff] [blame] | 959 | spinlock_t entry_lock; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 960 | }; |
| 961 | |
| 962 | struct extdev_entry { |
| 963 | char name[IFNAMSIZ]; |
| 964 | struct net_device *dev; |
| 965 | }; |
| 966 | |
| 967 | struct tcpudphdr { |
| 968 | __be16 src; |
| 969 | __be16 dst; |
| 970 | }; |
| 971 | |
| 972 | enum FoeEntryState { INVALID = 0, UNBIND = 1, BIND = 2, FIN = 3 }; |
| 973 | |
| 974 | enum FoeIpAct { |
| 975 | IPV4_HNAPT = 0, |
| 976 | IPV4_HNAT = 1, |
| 977 | IPV4_DSLITE = 3, |
| 978 | IPV6_3T_ROUTE = 4, |
| 979 | IPV6_5T_ROUTE = 5, |
| 980 | IPV6_6RD = 7, |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 981 | IPV4_MAP_T = 8, |
| 982 | IPV4_MAP_E = 9, |
developer | 5ffc5f1 | 2022-10-25 18:51:46 +0800 | [diff] [blame] | 983 | IPV6_HNAPT = 10, |
| 984 | IPV6_HNAT = 11, |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 985 | }; |
| 986 | |
| 987 | /*--------------------------------------------------------------------------*/ |
| 988 | /* Common Definition*/ |
| 989 | /*--------------------------------------------------------------------------*/ |
| 990 | |
| 991 | #define HNAT_SW_VER "1.1.0" |
| 992 | #define HASH_SEED_KEY 0x12345678 |
| 993 | |
| 994 | /*PPE_TB_CFG value*/ |
developer | d35bbcc | 2022-09-28 22:46:01 +0800 | [diff] [blame] | 995 | #define ENTRY_128B 0 |
| 996 | #define ENTRY_96B 1 |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 997 | #define ENTRY_80B 1 |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 998 | #define TABLE_1K 0 |
| 999 | #define TABLE_2K 1 |
| 1000 | #define TABLE_4K 2 |
| 1001 | #define TABLE_8K 3 |
| 1002 | #define TABLE_16K 4 |
developer | bc53e5f | 2021-05-21 10:07:17 +0800 | [diff] [blame] | 1003 | #define TABLE_32K 5 |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1004 | #define SMA_DROP 0 /* Drop the packet */ |
| 1005 | #define SMA_DROP2 1 /* Drop the packet */ |
| 1006 | #define SMA_ONLY_FWD_CPU 2 /* Only Forward to CPU */ |
| 1007 | #define SMA_FWD_CPU_BUILD_ENTRY 3 /* Forward to CPU and build new FOE entry */ |
| 1008 | #define HASH_MODE_0 0 |
| 1009 | #define HASH_MODE_1 1 |
| 1010 | #define HASH_MODE_2 2 |
| 1011 | #define HASH_MODE_3 3 |
| 1012 | |
| 1013 | /*PPE_FLOW_CFG*/ |
| 1014 | #define BIT_FUC_FOE BIT(2) |
| 1015 | #define BIT_FMC_FOE BIT(1) |
| 1016 | #define BIT_FBC_FOE BIT(0) |
| 1017 | #define BIT_UDP_IP4F_NAT_EN BIT(7) /*Enable IPv4 fragment + UDP packet NAT*/ |
| 1018 | #define BIT_IPV6_3T_ROUTE_EN BIT(8) |
| 1019 | #define BIT_IPV6_5T_ROUTE_EN BIT(9) |
| 1020 | #define BIT_IPV6_6RD_EN BIT(10) |
developer | e8b7dfa | 2023-04-20 10:16:44 +0800 | [diff] [blame] | 1021 | #define BIT_IPV6_464XLAT_EN BIT(11) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1022 | #define BIT_IPV4_NAT_EN BIT(12) |
| 1023 | #define BIT_IPV4_NAPT_EN BIT(13) |
| 1024 | #define BIT_IPV4_DSL_EN BIT(14) |
| 1025 | #define BIT_MIB_BUSY BIT(16) |
| 1026 | #define BIT_IPV4_NAT_FRAG_EN BIT(17) |
| 1027 | #define BIT_IPV4_HASH_GREK BIT(19) |
| 1028 | #define BIT_IPV6_HASH_GREK BIT(20) |
| 1029 | #define BIT_IPV4_MAPE_EN BIT(21) |
| 1030 | #define BIT_IPV4_MAPT_EN BIT(22) |
developer | 5ffc5f1 | 2022-10-25 18:51:46 +0800 | [diff] [blame] | 1031 | #define BIT_IPV6_NAT_EN BIT(23) |
| 1032 | #define BIT_IPV6_NAPT_EN BIT(24) |
| 1033 | #define BIT_CS0_RM_ALL_IP6_IP_EN BIT(25) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1034 | |
| 1035 | /*GDMA_FWD_CFG value*/ |
developer | 471f656 | 2021-05-10 20:48:34 +0800 | [diff] [blame] | 1036 | #define BITS_GDM_UFRC_P_PPE (NR_PPE0_PORT << 12) |
| 1037 | #define BITS_GDM_BFRC_P_PPE (NR_PPE0_PORT << 8) |
| 1038 | #define BITS_GDM_MFRC_P_PPE (NR_PPE0_PORT << 4) |
| 1039 | #define BITS_GDM_OFRC_P_PPE (NR_PPE0_PORT << 0) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1040 | #define BITS_GDM_ALL_FRC_P_PPE \ |
| 1041 | (BITS_GDM_UFRC_P_PPE | BITS_GDM_BFRC_P_PPE | BITS_GDM_MFRC_P_PPE | \ |
| 1042 | BITS_GDM_OFRC_P_PPE) |
| 1043 | |
developer | d35bbcc | 2022-09-28 22:46:01 +0800 | [diff] [blame] | 1044 | #define BITS_GDM_UFRC_P_PPE1 (NR_PPE1_PORT << 12) |
| 1045 | #define BITS_GDM_BFRC_P_PPE1 (NR_PPE1_PORT << 8) |
| 1046 | #define BITS_GDM_MFRC_P_PPE1 (NR_PPE1_PORT << 4) |
| 1047 | #define BITS_GDM_OFRC_P_PPE1 (NR_PPE1_PORT << 0) |
| 1048 | #define BITS_GDM_ALL_FRC_P_PPE1 \ |
| 1049 | (BITS_GDM_UFRC_P_PPE1 | BITS_GDM_BFRC_P_PPE1 | \ |
| 1050 | BITS_GDM_MFRC_P_PPE1 | BITS_GDM_OFRC_P_PPE1) |
| 1051 | |
| 1052 | #define BITS_GDM_UFRC_P_PPE2 (NR_PPE2_PORT << 12) |
| 1053 | #define BITS_GDM_BFRC_P_PPE2 (NR_PPE2_PORT << 8) |
| 1054 | #define BITS_GDM_MFRC_P_PPE2 (NR_PPE2_PORT << 4) |
| 1055 | #define BITS_GDM_OFRC_P_PPE2 (NR_PPE2_PORT << 0) |
| 1056 | #define BITS_GDM_ALL_FRC_P_PPE2 \ |
| 1057 | (BITS_GDM_UFRC_P_PPE2 | BITS_GDM_BFRC_P_PPE2 | \ |
| 1058 | BITS_GDM_MFRC_P_PPE2 | BITS_GDM_OFRC_P_PPE2) |
| 1059 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1060 | #define BITS_GDM_UFRC_P_CPU_PDMA (NR_PDMA_PORT << 12) |
| 1061 | #define BITS_GDM_BFRC_P_CPU_PDMA (NR_PDMA_PORT << 8) |
| 1062 | #define BITS_GDM_MFRC_P_CPU_PDMA (NR_PDMA_PORT << 4) |
| 1063 | #define BITS_GDM_OFRC_P_CPU_PDMA (NR_PDMA_PORT << 0) |
| 1064 | #define BITS_GDM_ALL_FRC_P_CPU_PDMA \ |
| 1065 | (BITS_GDM_UFRC_P_CPU_PDMA | BITS_GDM_BFRC_P_CPU_PDMA | \ |
| 1066 | BITS_GDM_MFRC_P_CPU_PDMA | BITS_GDM_OFRC_P_CPU_PDMA) |
| 1067 | |
| 1068 | #define BITS_GDM_UFRC_P_CPU_QDMA (NR_QDMA_PORT << 12) |
| 1069 | #define BITS_GDM_BFRC_P_CPU_QDMA (NR_QDMA_PORT << 8) |
| 1070 | #define BITS_GDM_MFRC_P_CPU_QDMA (NR_QDMA_PORT << 4) |
| 1071 | #define BITS_GDM_OFRC_P_CPU_QDMA (NR_QDMA_PORT << 0) |
| 1072 | #define BITS_GDM_ALL_FRC_P_CPU_QDMA \ |
| 1073 | (BITS_GDM_UFRC_P_CPU_QDMA | BITS_GDM_BFRC_P_CPU_QDMA | \ |
| 1074 | BITS_GDM_MFRC_P_CPU_QDMA | BITS_GDM_OFRC_P_CPU_QDMA) |
| 1075 | |
| 1076 | #define BITS_GDM_UFRC_P_DISCARD (NR_DISCARD << 12) |
| 1077 | #define BITS_GDM_BFRC_P_DISCARD (NR_DISCARD << 8) |
| 1078 | #define BITS_GDM_MFRC_P_DISCARD (NR_DISCARD << 4) |
| 1079 | #define BITS_GDM_OFRC_P_DISCARD (NR_DISCARD << 0) |
| 1080 | #define BITS_GDM_ALL_FRC_P_DISCARD \ |
| 1081 | (BITS_GDM_UFRC_P_DISCARD | BITS_GDM_BFRC_P_DISCARD | \ |
| 1082 | BITS_GDM_MFRC_P_DISCARD | BITS_GDM_OFRC_P_DISCARD) |
| 1083 | |
| 1084 | #define hnat_is_enabled(hnat_priv) (hnat_priv->enable) |
| 1085 | #define hnat_enabled(hnat_priv) (hnat_priv->enable = 1) |
| 1086 | #define hnat_disabled(hnat_priv) (hnat_priv->enable = 0) |
| 1087 | #define hnat_is_enabled1(hnat_priv) (hnat_priv->enable1) |
| 1088 | #define hnat_enabled1(hnat_priv) (hnat_priv->enable1 = 1) |
| 1089 | #define hnat_disabled1(hnat_priv) (hnat_priv->enable1 = 0) |
| 1090 | |
| 1091 | #define entry_hnat_is_bound(e) (e->bfib1.state == BIND) |
| 1092 | #define entry_hnat_state(e) (e->bfib1.state) |
| 1093 | |
| 1094 | #define skb_hnat_is_hashed(skb) \ |
| 1095 | (skb_hnat_entry(skb) != 0x3fff && skb_hnat_entry(skb) < hnat_priv->foe_etry_num) |
developer | d35bbcc | 2022-09-28 22:46:01 +0800 | [diff] [blame] | 1096 | #define FROM_GE_LAN_GRP(skb) (FROM_GE_LAN(skb) | FROM_GE_LAN2(skb)) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1097 | #define FROM_GE_LAN(skb) (skb_hnat_iface(skb) == FOE_MAGIC_GE_LAN) |
developer | d35bbcc | 2022-09-28 22:46:01 +0800 | [diff] [blame] | 1098 | #define FROM_GE_LAN2(skb) (skb_hnat_iface(skb) == FOE_MAGIC_GE_LAN2) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1099 | #define FROM_GE_WAN(skb) (skb_hnat_iface(skb) == FOE_MAGIC_GE_WAN) |
| 1100 | #define FROM_GE_PPD(skb) (skb_hnat_iface(skb) == FOE_MAGIC_GE_PPD) |
| 1101 | #define FROM_GE_VIRTUAL(skb) (skb_hnat_iface(skb) == FOE_MAGIC_GE_VIRTUAL) |
| 1102 | #define FROM_EXT(skb) (skb_hnat_iface(skb) == FOE_MAGIC_EXT) |
developer | e567ad3 | 2021-05-25 17:16:17 +0800 | [diff] [blame] | 1103 | #define FROM_WED(skb) ((skb_hnat_iface(skb) == FOE_MAGIC_WED0) || \ |
developer | 7d468d7 | 2023-08-02 11:41:48 +0800 | [diff] [blame] | 1104 | (skb_hnat_iface(skb) == FOE_MAGIC_WED1) || \ |
| 1105 | (skb_hnat_iface(skb) == FOE_MAGIC_WED2)) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1106 | #define FOE_MAGIC_GE_LAN 0x1 |
| 1107 | #define FOE_MAGIC_GE_WAN 0x2 |
| 1108 | #define FOE_MAGIC_EXT 0x3 |
| 1109 | #define FOE_MAGIC_GE_VIRTUAL 0x4 |
| 1110 | #define FOE_MAGIC_GE_PPD 0x5 |
developer | d35bbcc | 2022-09-28 22:46:01 +0800 | [diff] [blame] | 1111 | #define FOE_MAGIC_GE_LAN2 0x6 |
developer | e567ad3 | 2021-05-25 17:16:17 +0800 | [diff] [blame] | 1112 | #define FOE_MAGIC_WED0 0x78 |
| 1113 | #define FOE_MAGIC_WED1 0x79 |
developer | d35bbcc | 2022-09-28 22:46:01 +0800 | [diff] [blame] | 1114 | #define FOE_MAGIC_WED2 0x7A |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1115 | #define FOE_INVALID 0xf |
| 1116 | #define index6b(i) (0x3fU - i) |
| 1117 | |
| 1118 | #define IPV4_HNAPT 0 |
| 1119 | #define IPV4_HNAT 1 |
| 1120 | #define IP_FORMAT(addr) \ |
| 1121 | (((unsigned char *)&addr)[3], ((unsigned char *)&addr)[2], \ |
| 1122 | ((unsigned char *)&addr)[1], ((unsigned char *)&addr)[0]) |
| 1123 | |
| 1124 | /*PSE Ports*/ |
| 1125 | #define NR_PDMA_PORT 0 |
| 1126 | #define NR_GMAC1_PORT 1 |
| 1127 | #define NR_GMAC2_PORT 2 |
developer | d35bbcc | 2022-09-28 22:46:01 +0800 | [diff] [blame] | 1128 | #if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3) |
developer | 471f656 | 2021-05-10 20:48:34 +0800 | [diff] [blame] | 1129 | #define NR_WHNAT_WDMA_PORT EINVAL |
| 1130 | #define NR_PPE0_PORT 3 |
| 1131 | #define NR_PPE1_PORT 4 |
developer | d35bbcc | 2022-09-28 22:46:01 +0800 | [diff] [blame] | 1132 | #define NR_PPE2_PORT 0xC |
developer | 471f656 | 2021-05-10 20:48:34 +0800 | [diff] [blame] | 1133 | #else |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1134 | #define NR_WHNAT_WDMA_PORT 3 |
developer | 471f656 | 2021-05-10 20:48:34 +0800 | [diff] [blame] | 1135 | #define NR_PPE0_PORT 4 |
| 1136 | #endif |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1137 | #define NR_QDMA_PORT 5 |
| 1138 | #define NR_DISCARD 7 |
| 1139 | #define NR_WDMA0_PORT 8 |
| 1140 | #define NR_WDMA1_PORT 9 |
developer | 7d468d7 | 2023-08-02 11:41:48 +0800 | [diff] [blame] | 1141 | #define NR_WDMA2_PORT 13 |
developer | d35bbcc | 2022-09-28 22:46:01 +0800 | [diff] [blame] | 1142 | #define NR_GMAC3_PORT 15 |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1143 | #define LAN_DEV_NAME hnat_priv->lan |
developer | d35bbcc | 2022-09-28 22:46:01 +0800 | [diff] [blame] | 1144 | #define LAN2_DEV_NAME hnat_priv->lan2 |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1145 | #define IS_WAN(dev) \ |
| 1146 | (!strncmp((dev)->name, hnat_priv->wan, strlen(hnat_priv->wan))) |
developer | d35bbcc | 2022-09-28 22:46:01 +0800 | [diff] [blame] | 1147 | #define IS_LAN_GRP(dev) (IS_LAN(dev) | IS_LAN2(dev)) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1148 | #define IS_LAN(dev) (!strncmp(dev->name, LAN_DEV_NAME, strlen(LAN_DEV_NAME))) |
developer | d35bbcc | 2022-09-28 22:46:01 +0800 | [diff] [blame] | 1149 | #define IS_LAN2(dev) (!strncmp(dev->name, LAN2_DEV_NAME, \ |
| 1150 | strlen(LAN2_DEV_NAME))) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1151 | #define IS_BR(dev) (!strncmp(dev->name, "br", 2)) |
| 1152 | #define IS_WHNAT(dev) \ |
| 1153 | ((hnat_priv->data->whnat && \ |
| 1154 | (get_wifi_hook_if_index_from_dev(dev) != 0)) ? 1 : 0) |
| 1155 | #define IS_EXT(dev) ((get_index_from_dev(dev) != 0) ? 1 : 0) |
| 1156 | #define IS_PPD(dev) (!strcmp(dev->name, hnat_priv->ppd)) |
| 1157 | #define IS_IPV4_HNAPT(x) (((x)->bfib1.pkt_type == IPV4_HNAPT) ? 1 : 0) |
| 1158 | #define IS_IPV4_HNAT(x) (((x)->bfib1.pkt_type == IPV4_HNAT) ? 1 : 0) |
| 1159 | #define IS_IPV4_GRP(x) (IS_IPV4_HNAPT(x) | IS_IPV4_HNAT(x)) |
| 1160 | #define IS_IPV4_DSLITE(x) (((x)->bfib1.pkt_type == IPV4_DSLITE) ? 1 : 0) |
| 1161 | #define IS_IPV4_MAPE(x) (((x)->bfib1.pkt_type == IPV4_MAP_E) ? 1 : 0) |
| 1162 | #define IS_IPV4_MAPT(x) (((x)->bfib1.pkt_type == IPV4_MAP_T) ? 1 : 0) |
| 1163 | #define IS_IPV6_3T_ROUTE(x) (((x)->bfib1.pkt_type == IPV6_3T_ROUTE) ? 1 : 0) |
| 1164 | #define IS_IPV6_5T_ROUTE(x) (((x)->bfib1.pkt_type == IPV6_5T_ROUTE) ? 1 : 0) |
| 1165 | #define IS_IPV6_6RD(x) (((x)->bfib1.pkt_type == IPV6_6RD) ? 1 : 0) |
developer | 5ffc5f1 | 2022-10-25 18:51:46 +0800 | [diff] [blame] | 1166 | #define IS_IPV6_HNAPT(x) (((x)->bfib1.pkt_type == IPV6_HNAPT) ? 1 : 0) |
| 1167 | #define IS_IPV6_HNAT(x) (((x)->bfib1.pkt_type == IPV6_HNAT) ? 1 : 0) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1168 | #define IS_IPV6_GRP(x) \ |
| 1169 | (IS_IPV6_3T_ROUTE(x) | IS_IPV6_5T_ROUTE(x) | IS_IPV6_6RD(x) | \ |
developer | 5ffc5f1 | 2022-10-25 18:51:46 +0800 | [diff] [blame] | 1170 | IS_IPV4_DSLITE(x) | IS_IPV4_MAPE(x) | IS_IPV4_MAPT(x) | \ |
| 1171 | IS_IPV6_HNAPT(x) | IS_IPV6_HNAT(x)) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1172 | #define IS_BOND_MODE (!strncmp(LAN_DEV_NAME, "bond", 4)) |
| 1173 | #define IS_GMAC1_MODE ((hnat_priv->gmac_num == 1) ? 1 : 0) |
developer | af07fad | 2021-11-19 17:53:42 +0800 | [diff] [blame] | 1174 | #define IS_HQOS_MODE (qos_toggle == 1) |
| 1175 | #define IS_PPPQ_MODE (qos_toggle == 2) /* Per Port Per Queue */ |
developer | 934756a | 2022-11-18 14:51:34 +0800 | [diff] [blame] | 1176 | #define IS_PPPQ_PATH(dev, skb) \ |
| 1177 | ((IS_DSA_1G_LAN(dev) || IS_DSA_WAN(dev)) || \ |
| 1178 | (FROM_WED(skb) && IS_DSA_LAN(dev))) |
developer | 47545a3 | 2022-11-15 16:06:58 +0800 | [diff] [blame] | 1179 | #define IS_HQOS_DL_MODE (IS_HQOS_MODE && qos_dl_toggle) |
| 1180 | #define IS_HQOS_UL_MODE (IS_HQOS_MODE && qos_ul_toggle) |
developer | 70cdf6e | 2021-12-07 18:58:35 +0800 | [diff] [blame] | 1181 | #define MAX_PPPQ_PORT_NUM 6 |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1182 | |
| 1183 | #define es(entry) (entry_state[entry->bfib1.state]) |
| 1184 | #define ei(entry, end) (hnat_priv->foe_etry_num - (int)(end - entry)) |
| 1185 | #define pt(entry) (packet_type[entry->ipv4_hnapt.bfib1.pkt_type]) |
| 1186 | #define ipv4_smac(mac, e) \ |
| 1187 | ({ \ |
| 1188 | mac[0] = e->ipv4_hnapt.smac_hi[3]; \ |
| 1189 | mac[1] = e->ipv4_hnapt.smac_hi[2]; \ |
| 1190 | mac[2] = e->ipv4_hnapt.smac_hi[1]; \ |
| 1191 | mac[3] = e->ipv4_hnapt.smac_hi[0]; \ |
| 1192 | mac[4] = e->ipv4_hnapt.smac_lo[1]; \ |
| 1193 | mac[5] = e->ipv4_hnapt.smac_lo[0]; \ |
| 1194 | }) |
| 1195 | #define ipv4_dmac(mac, e) \ |
| 1196 | ({ \ |
| 1197 | mac[0] = e->ipv4_hnapt.dmac_hi[3]; \ |
| 1198 | mac[1] = e->ipv4_hnapt.dmac_hi[2]; \ |
| 1199 | mac[2] = e->ipv4_hnapt.dmac_hi[1]; \ |
| 1200 | mac[3] = e->ipv4_hnapt.dmac_hi[0]; \ |
| 1201 | mac[4] = e->ipv4_hnapt.dmac_lo[1]; \ |
| 1202 | mac[5] = e->ipv4_hnapt.dmac_lo[0]; \ |
| 1203 | }) |
| 1204 | |
| 1205 | #define IS_DSA_LAN(dev) (!strncmp(dev->name, "lan", 3)) |
developer | 399ec07 | 2022-06-24 16:07:41 +0800 | [diff] [blame] | 1206 | #define IS_DSA_1G_LAN(dev) (!strncmp(dev->name, "lan", 3) && \ |
| 1207 | strcmp(dev->name, "lan5")) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1208 | #define IS_DSA_WAN(dev) (!strncmp(dev->name, "wan", 3)) |
| 1209 | #define NONE_DSA_PORT 0xff |
| 1210 | #define MAX_CRSN_NUM 32 |
| 1211 | #define IPV6_HDR_LEN 40 |
developer | 5ffc5f1 | 2022-10-25 18:51:46 +0800 | [diff] [blame] | 1212 | #define IPV6_SNAT 0 |
| 1213 | #define IPV6_DNAT 1 |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1214 | |
| 1215 | /*QDMA_PAGE value*/ |
| 1216 | #define NUM_OF_Q_PER_PAGE 16 |
| 1217 | |
| 1218 | /*IPv6 Header*/ |
| 1219 | #ifndef NEXTHDR_IPIP |
| 1220 | #define NEXTHDR_IPIP 4 |
| 1221 | #endif |
| 1222 | |
developer | b39bf72 | 2023-06-21 15:40:20 +0800 | [diff] [blame] | 1223 | #define UDF_PINGPONG_IFIDX GENMASK(3, 0) |
| 1224 | #define UDF_HNAT_PRE_FILLED BIT(4) |
| 1225 | |
developer | f630235 | 2023-11-23 16:07:30 +0800 | [diff] [blame^] | 1226 | #define HQOS_FLAG(dev, skb, qid) \ |
developer | 1afd9ce | 2023-10-11 10:57:06 +0800 | [diff] [blame] | 1227 | ((IS_HQOS_UL_MODE && IS_WAN(dev)) || \ |
| 1228 | (IS_HQOS_DL_MODE && IS_LAN_GRP(dev)) || \ |
developer | df16a6a | 2023-11-03 11:35:20 +0800 | [diff] [blame] | 1229 | (IS_PPPQ_MODE && (IS_PPPQ_PATH(dev, skb) || \ |
| 1230 | qid >= MAX_PPPQ_PORT_NUM))) |
developer | 1afd9ce | 2023-10-11 10:57:06 +0800 | [diff] [blame] | 1231 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1232 | extern const struct of_device_id of_hnat_match[]; |
| 1233 | extern struct mtk_hnat *hnat_priv; |
| 1234 | |
developer | b39bf72 | 2023-06-21 15:40:20 +0800 | [diff] [blame] | 1235 | static inline int is_hnat_pre_filled(struct foe_entry *entry) |
| 1236 | { |
| 1237 | u32 udf = 0; |
| 1238 | |
| 1239 | if (IS_IPV4_GRP(entry)) |
| 1240 | udf = entry->ipv4_hnapt.act_dp; |
| 1241 | else |
| 1242 | udf = entry->ipv6_5t_route.act_dp; |
| 1243 | |
| 1244 | return !!(udf & UDF_HNAT_PRE_FILLED); |
| 1245 | } |
| 1246 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1247 | #if defined(CONFIG_NET_DSA_MT7530) |
developer | af07fad | 2021-11-19 17:53:42 +0800 | [diff] [blame] | 1248 | u32 hnat_dsa_fill_stag(const struct net_device *netdev, |
| 1249 | struct foe_entry *entry, |
| 1250 | struct flow_offload_hw_path *hw_path, |
| 1251 | u16 eth_proto, int mape); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1252 | |
| 1253 | static inline bool hnat_dsa_is_enable(struct mtk_hnat *priv) |
| 1254 | { |
| 1255 | return (priv->wan_dsa_port != NONE_DSA_PORT); |
| 1256 | } |
| 1257 | #else |
developer | af07fad | 2021-11-19 17:53:42 +0800 | [diff] [blame] | 1258 | static inline u32 hnat_dsa_fill_stag(const struct net_device *netdev, |
| 1259 | struct foe_entry *entry, |
| 1260 | struct flow_offload_hw_path *hw_path, |
| 1261 | u16 eth_proto, int mape) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1262 | { |
developer | d35bbcc | 2022-09-28 22:46:01 +0800 | [diff] [blame] | 1263 | return 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1264 | } |
| 1265 | |
| 1266 | static inline bool hnat_dsa_is_enable(struct mtk_hnat *priv) |
| 1267 | { |
| 1268 | return false; |
| 1269 | } |
| 1270 | #endif |
| 1271 | |
| 1272 | void hnat_deinit_debugfs(struct mtk_hnat *h); |
| 1273 | int hnat_init_debugfs(struct mtk_hnat *h); |
| 1274 | int hnat_register_nf_hooks(void); |
| 1275 | void hnat_unregister_nf_hooks(void); |
| 1276 | int whnat_adjust_nf_hooks(void); |
| 1277 | int mtk_hqos_ptype_cb(struct sk_buff *skb, struct net_device *dev, |
| 1278 | struct packet_type *pt, struct net_device *unused); |
| 1279 | extern int dbg_cpu_reason; |
| 1280 | extern int debug_level; |
developer | e8b7dfa | 2023-04-20 10:16:44 +0800 | [diff] [blame] | 1281 | extern int xlat_toggle; |
| 1282 | extern struct hnat_desc headroom[DEF_ETRY_NUM]; |
developer | 47545a3 | 2022-11-15 16:06:58 +0800 | [diff] [blame] | 1283 | extern int qos_dl_toggle; |
| 1284 | extern int qos_ul_toggle; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1285 | extern int hook_toggle; |
| 1286 | extern int mape_toggle; |
developer | af07fad | 2021-11-19 17:53:42 +0800 | [diff] [blame] | 1287 | extern int qos_toggle; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1288 | |
| 1289 | int ext_if_add(struct extdev_entry *ext_entry); |
| 1290 | int ext_if_del(struct extdev_entry *ext_entry); |
| 1291 | void cr_set_field(void __iomem *reg, u32 field, u32 val); |
| 1292 | int mtk_sw_nat_hook_tx(struct sk_buff *skb, int gmac_no); |
| 1293 | int mtk_sw_nat_hook_rx(struct sk_buff *skb); |
developer | 5841dcc | 2023-07-06 19:43:58 +0800 | [diff] [blame] | 1294 | void foe_clear_all_bind_entries(void); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1295 | void mtk_ppe_dev_register_hook(struct net_device *dev); |
| 1296 | void mtk_ppe_dev_unregister_hook(struct net_device *dev); |
| 1297 | int nf_hnat_netdevice_event(struct notifier_block *unused, unsigned long event, |
| 1298 | void *ptr); |
| 1299 | int nf_hnat_netevent_handler(struct notifier_block *unused, unsigned long event, |
| 1300 | void *ptr); |
| 1301 | uint32_t foe_dump_pkt(struct sk_buff *skb); |
| 1302 | uint32_t hnat_cpu_reason_cnt(struct sk_buff *skb); |
| 1303 | int hnat_enable_hook(void); |
| 1304 | int hnat_disable_hook(void); |
| 1305 | void hnat_cache_ebl(int enable); |
developer | 70cdf6e | 2021-12-07 18:58:35 +0800 | [diff] [blame] | 1306 | void hnat_qos_shaper_ebl(u32 id, u32 enable); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1307 | void set_gmac_ppe_fwd(int gmac_no, int enable); |
developer | 4c32b7a | 2021-11-13 16:46:43 +0800 | [diff] [blame] | 1308 | int entry_detail(u32 ppe_id, int index); |
developer | 731b98f | 2021-09-17 17:44:37 +0800 | [diff] [blame] | 1309 | int entry_delete_by_mac(u8 *mac); |
developer | 4c32b7a | 2021-11-13 16:46:43 +0800 | [diff] [blame] | 1310 | int entry_delete(u32 ppe_id, int index); |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 1311 | int hnat_warm_init(void); |
developer | e8b7dfa | 2023-04-20 10:16:44 +0800 | [diff] [blame] | 1312 | u32 hnat_get_ppe_hash(struct foe_entry *entry); |
| 1313 | int mtk_ppe_get_xlat_v4_by_v6(struct in6_addr *ipv6, u32 *ipv4); |
| 1314 | int mtk_ppe_get_xlat_v6_by_v4(u32 *ipv4, struct in6_addr *ipv6, |
| 1315 | struct in6_addr *prefix); |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 1316 | |
developer | 4c32b7a | 2021-11-13 16:46:43 +0800 | [diff] [blame] | 1317 | struct hnat_accounting *hnat_get_count(struct mtk_hnat *h, u32 ppe_id, |
developer | 30a4768 | 2021-11-02 17:06:14 +0800 | [diff] [blame] | 1318 | u32 index, struct hnat_accounting *diff); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1319 | |
| 1320 | static inline u16 foe_timestamp(struct mtk_hnat *h) |
| 1321 | { |
| 1322 | return (readl(hnat_priv->fe_base + 0x0010)) & 0xffff; |
| 1323 | } |