blob: 8f5f37b33b970b274d37df6c0fa641411a39e81c [file] [log] [blame]
developerfd40db22021-04-29 10:08:25 +08001/* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
4 *
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
9 *
10 * Copyright (C) 2014-2016 Sean Wang <sean.wang@mediatek.com>
11 * Copyright (C) 2016-2017 John Crispin <blogic@openwrt.org>
12 */
13
14#include <linux/debugfs.h>
15#include <linux/string.h>
16#include <linux/if.h>
17#include <linux/if_ether.h>
18#include <net/netevent.h>
19#include <linux/mod_devicetable.h>
20#include "hnat_mcast.h"
developere8b7dfa2023-04-20 10:16:44 +080021#include "nf_hnat_mtk.h"
developerfd40db22021-04-29 10:08:25 +080022
23/*--------------------------------------------------------------------------*/
24/* Register Offset*/
25/*--------------------------------------------------------------------------*/
26#define PPE_GLO_CFG 0x00
27#define PPE_FLOW_CFG 0x04
28#define PPE_IP_PROT_CHK 0x08
29#define PPE_IP_PROT_0 0x0C
30#define PPE_IP_PROT_1 0x10
31#define PPE_IP_PROT_2 0x14
32#define PPE_IP_PROT_3 0x18
33#define PPE_TB_CFG 0x1C
34#define PPE_TB_BASE 0x20
35#define PPE_TB_USED 0x24
36#define PPE_BNDR 0x28
37#define PPE_BIND_LMT_0 0x2C
38#define PPE_BIND_LMT_1 0x30
39#define PPE_KA 0x34
40#define PPE_UNB_AGE 0x38
41#define PPE_BND_AGE_0 0x3C
42#define PPE_BND_AGE_1 0x40
43#define PPE_HASH_SEED 0x44
44#define PPE_DFT_CPORT 0x48
45#define PPE_DFT_CPORT1 0x4C
46#define PPE_MCAST_PPSE 0x84
47#define PPE_MCAST_L_0 0x88
48#define PPE_MCAST_H_0 0x8C
49#define PPE_MCAST_L_1 0x90
50#define PPE_MCAST_H_1 0x94
51#define PPE_MCAST_L_2 0x98
52#define PPE_MCAST_H_2 0x9C
53#define PPE_MCAST_L_3 0xA0
54#define PPE_MCAST_H_3 0xA4
55#define PPE_MCAST_L_4 0xA8
56#define PPE_MCAST_H_4 0xAC
57#define PPE_MCAST_L_5 0xB0
58#define PPE_MCAST_H_5 0xB4
59#define PPE_MCAST_L_6 0xBC
60#define PPE_MCAST_H_6 0xC0
61#define PPE_MCAST_L_7 0xC4
62#define PPE_MCAST_H_7 0xC8
63#define PPE_MCAST_L_8 0xCC
64#define PPE_MCAST_H_8 0xD0
65#define PPE_MCAST_L_9 0xD4
66#define PPE_MCAST_H_9 0xD8
67#define PPE_MCAST_L_A 0xDC
68#define PPE_MCAST_H_A 0xE0
69#define PPE_MCAST_L_B 0xE4
70#define PPE_MCAST_H_B 0xE8
71#define PPE_MCAST_L_C 0xEC
72#define PPE_MCAST_H_C 0xF0
73#define PPE_MCAST_L_D 0xF4
74#define PPE_MCAST_H_D 0xF8
75#define PPE_MCAST_L_E 0xFC
76#define PPE_MCAST_H_E 0xE0
77#define PPE_MCAST_L_F 0x100
78#define PPE_MCAST_H_F 0x104
79#define PPE_MCAST_L_10 0xC00
80#define PPE_MCAST_H_10 0xC04
81#define PPE_MTU_DRP 0x108
82#define PPE_MTU_VLYR_0 0x10C
83#define PPE_MTU_VLYR_1 0x110
84#define PPE_MTU_VLYR_2 0x114
85#define PPE_VPM_TPID 0x118
86#define PPE_CAH_CTRL 0x120
87#define PPE_CAH_TAG_SRH 0x124
88#define PPE_CAH_LINE_RW 0x128
89#define PPE_CAH_WDATA 0x12C
90#define PPE_CAH_RDATA 0x130
91
92#define PPE_MIB_CFG 0X134
93#define PPE_MIB_TB_BASE 0X138
94#define PPE_MIB_SER_CR 0X13C
95#define PPE_MIB_SER_R0 0X140
96#define PPE_MIB_SER_R1 0X144
97#define PPE_MIB_SER_R2 0X148
developerd35bbcc2022-09-28 22:46:01 +080098#define PPE_MIB_SER_R3 0X14C
developerfd40db22021-04-29 10:08:25 +080099#define PPE_MIB_CAH_CTRL 0X150
100#define PPE_MIB_CAH_TAG_SRH 0X154
101#define PPE_MIB_CAH_LINE_RW 0X158
102#define PPE_MIB_CAH_WDATA 0X15C
103#define PPE_MIB_CAH_RDATA 0X160
developerd35bbcc2022-09-28 22:46:01 +0800104#define PPE_SB_FIFO_DBG 0x170
developerfd40db22021-04-29 10:08:25 +0800105#define PPE_SBW_CTRL 0x174
106
107#define GDMA1_FWD_CFG 0x500
108#define GDMA2_FWD_CFG 0x1500
developerd35bbcc2022-09-28 22:46:01 +0800109#define GDMA3_FWD_CFG 0x540
developerfd40db22021-04-29 10:08:25 +0800110
developer24948202021-11-24 17:38:27 +0800111/* QDMA Tx queue configuration */
developer70cdf6e2021-12-07 18:58:35 +0800112#define QTX_CFG(x) (QDMA_BASE + ((x) * 0x10))
113#define QTX_CFG_HW_RESV_CNT_OFFSET (8)
114#define QTX_CFG_SW_RESV_CNT_OFFSET (0)
115
116#define QTX_SCH(x) (QDMA_BASE + 0x4 + ((x) * 0x10))
117#define QTX_SCH_MIN_RATE_EN BIT(27)
118#define QTX_SCH_MAX_RATE_EN BIT(11)
119#define QTX_SCH_MIN_RATE_MAN_OFFSET (20)
120#define QTX_SCH_MIN_RATE_EXP_OFFSET (16)
121#define QTX_SCH_MAX_RATE_WGHT_OFFSET (12)
122#define QTX_SCH_MAX_RATE_MAN_OFFSET (4)
123#define QTX_SCH_MAX_RATE_EXP_OFFSET (0)
developer24948202021-11-24 17:38:27 +0800124
125/* QDMA Tx scheduler configuration */
developer70cdf6e2021-12-07 18:58:35 +0800126#define QDMA_PAGE (QDMA_BASE + 0x1f0)
127#define QDMA_TX_2SCH_BASE (QDMA_BASE + 0x214)
128#define QTX_MIB_IF (QDMA_BASE + 0x2bc)
129#define QDMA_TX_4SCH_BASE(x) (QDMA_BASE + 0x398 + (((x) >> 1) * 0x4))
developer34028fb2022-01-11 13:51:29 +0800130#define QDMA_TX_SCH_WFQ_EN BIT(15)
developerfd40db22021-04-29 10:08:25 +0800131
132/*--------------------------------------------------------------------------*/
133/* Register Mask*/
134/*--------------------------------------------------------------------------*/
135/* PPE_TB_CFG mask */
136#define TB_ETRY_NUM (0x7 << 0) /* RW */
137#define TB_ENTRY_SIZE (0x1 << 3) /* RW */
138#define SMA (0x3 << 4) /* RW */
139#define NTU_AGE (0x1 << 7) /* RW */
140#define UNBD_AGE (0x1 << 8) /* RW */
141#define TCP_AGE (0x1 << 9) /* RW */
142#define UDP_AGE (0x1 << 10) /* RW */
143#define FIN_AGE (0x1 << 11) /* RW */
144#define KA_CFG (0x3 << 12)
145#define HASH_MODE (0x3 << 14) /* RW */
146#define SCAN_MODE (0x3 << 16) /* RW */
147#define XMODE (0x3 << 18) /* RW */
developer8051e042022-04-08 13:26:36 +0800148#define TICK_SEL (0x1 << 24) /* RW */
149
developerfd40db22021-04-29 10:08:25 +0800150
151/*PPE_CAH_CTRL mask*/
152#define CAH_EN (0x1 << 0) /* RW */
153#define CAH_X_MODE (0x1 << 9) /* RW */
154
155/*PPE_UNB_AGE mask*/
156#define UNB_DLTA (0xff << 0) /* RW */
157#define UNB_MNP (0xffff << 16) /* RW */
158
159/*PPE_BND_AGE_0 mask*/
160#define UDP_DLTA (0xffff << 0) /* RW */
161#define NTU_DLTA (0xffff << 16) /* RW */
162
163/*PPE_BND_AGE_1 mask*/
164#define TCP_DLTA (0xffff << 0) /* RW */
165#define FIN_DLTA (0xffff << 16) /* RW */
166
167/*PPE_KA mask*/
168#define KA_T (0xffff << 0) /* RW */
169#define TCP_KA (0xff << 16) /* RW */
170#define UDP_KA (0xff << 24) /* RW */
171
172/*PPE_BIND_LMT_0 mask*/
173#define QURT_LMT (0x3ff << 0) /* RW */
174#define HALF_LMT (0x3ff << 16) /* RW */
175
176/*PPE_BIND_LMT_1 mask*/
177#define FULL_LMT (0x3fff << 0) /* RW */
178#define NTU_KA (0xff << 16) /* RW */
179
180/*PPE_BNDR mask*/
181#define BIND_RATE (0xffff << 0) /* RW */
182#define PBND_RD_PRD (0xffff << 16) /* RW */
183
184/*PPE_GLO_CFG mask*/
185#define PPE_EN (0x1 << 0) /* RW */
186#define TTL0_DRP (0x1 << 4) /* RW */
187#define MCAST_TB_EN (0x1 << 7) /* RW */
188#define MCAST_HASH (0x3 << 12) /* RW */
189
190#define MC_P3_PPSE (0xf << 12) /* RW */
191#define MC_P2_PPSE (0xf << 8) /* RW */
192#define MC_P1_PPSE (0xf << 4) /* RW */
193#define MC_P0_PPSE (0xf << 0) /* RW */
194
195#define MIB_EN (0x1 << 0) /* RW */
196#define MIB_READ_CLEAR (0X1 << 1) /* RW */
197#define MIB_CAH_EN (0X1 << 0) /* RW */
198
199/*GDMA_FWD_CFG mask */
developerd35bbcc2022-09-28 22:46:01 +0800200#define GDM_UFRC_MASK (0xF << 12) /* RW */
201#define GDM_BFRC_MASK (0xF << 8) /*RW*/
202#define GDM_MFRC_MASK (0xF << 4) /*RW*/
203#define GDM_OFRC_MASK (0xF << 0) /*RW*/
developerfd40db22021-04-29 10:08:25 +0800204#define GDM_ALL_FRC_MASK \
205 (GDM_UFRC_MASK | GDM_BFRC_MASK | GDM_MFRC_MASK | GDM_OFRC_MASK)
206
207/*QDMA_PAGE mask*/
208#define QTX_CFG_PAGE (0xf << 0) /* RW */
209
210/*QTX_MIB_IF mask*/
211#define MIB_ON_QTX_CFG (0x1 << 31) /* RW */
212#define VQTX_MIB_EN (0x1 << 28) /* RW */
213
developerd35bbcc2022-09-28 22:46:01 +0800214/* PPE Side Band FIFO Debug Mask */
215#define SB_MED_FULL_DRP_EN (0x1 << 11)
216
developerfd40db22021-04-29 10:08:25 +0800217/*--------------------------------------------------------------------------*/
218/* Descriptor Structure */
219/*--------------------------------------------------------------------------*/
developerd35bbcc2022-09-28 22:46:01 +0800220#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3)
developerfd40db22021-04-29 10:08:25 +0800221struct hnat_unbind_info_blk {
222 u32 time_stamp : 8;
223 u32 sp : 4;
224 u32 pcnt : 8;
225 u32 ilgf : 1;
226 u32 mc : 1;
227 u32 preb : 1;
228 u32 pkt_type : 5;
229 u32 state : 2;
230 u32 udp : 1;
231 u32 sta : 1; /* static entry */
232} __packed;
233
234struct hnat_bind_info_blk {
235 u32 time_stamp : 8;
236 u32 sp : 4;
237 u32 mc : 1;
238 u32 ka : 1; /* keep alive */
239 u32 vlan_layer : 3;
240 u32 psn : 1; /* egress packet has PPPoE session */
241 u32 vpm : 1; /* 0:ethertype remark, 1:0x8100(CR default) */
242 u32 ps : 1; /* packet sampling */
243 u32 cah : 1; /* cacheable flag */
244 u32 rmt : 1; /* remove tunnel ip header (6rd/dslite only) */
245 u32 ttl : 1;
246 u32 pkt_type : 5;
247 u32 state : 2;
248 u32 udp : 1;
249 u32 sta : 1; /* static entry */
250} __packed;
251
252struct hnat_info_blk2 {
253 u32 qid : 7; /* QID in Qos Port */
254 u32 port_mg : 1;
255 u32 fqos : 1; /* force to PSE QoS port */
256 u32 dp : 4; /* force to PSE port x */
257 u32 mcast : 1; /* multicast this packet to CPU */
258 u32 pcpl : 1; /* OSBN */
259 u32 mibf : 1;
260 u32 alen : 1;
261 u32 rxid : 2;
262 u32 winfoi : 1;
263 u32 port_ag : 4;
264 u32 dscp : 8; /* DSCP value */
265} __packed;
266
developerd35bbcc2022-09-28 22:46:01 +0800267#if defined(CONFIG_MEDIATEK_NETSYS_V3)
268struct hnat_winfo {
269 u32 wcid : 16; /* WiFi wtable Idx */
270 u32 bssid : 8; /* WiFi Bssidx */
271 u32 resv : 8;
272} __packed;
273
274struct hnat_winfo_pao {
275 u32 usr_info : 16;
276 u32 tid : 4;
277 u32 is_fixedrate : 1;
278 u32 is_prior : 1;
279 u32 is_sp : 1;
280 u32 hf : 1;
281 u32 amsdu : 1;
282 u32 resv : 7;
283} __packed;
284#elif defined(CONFIG_MEDIATEK_NETSYS_V2)
developerfd40db22021-04-29 10:08:25 +0800285struct hnat_winfo {
286 u32 bssid : 6; /* WiFi Bssidx */
287 u32 wcid : 10; /* WiFi wtable Idx */
288} __packed;
developerd35bbcc2022-09-28 22:46:01 +0800289#endif
developerfd40db22021-04-29 10:08:25 +0800290
291#else
292struct hnat_unbind_info_blk {
293 u32 time_stamp : 8;
294 u32 pcnt : 16; /* packet count */
295 u32 preb : 1;
296 u32 pkt_type : 3;
297 u32 state : 2;
298 u32 udp : 1;
299 u32 sta : 1; /* static entry */
300} __packed;
301
302struct hnat_bind_info_blk {
303 u32 time_stamp : 15;
304 u32 ka : 1; /* keep alive */
305 u32 vlan_layer : 3;
306 u32 psn : 1; /* egress packet has PPPoE session */
307 u32 vpm : 1; /* 0:ethertype remark, 1:0x8100(CR default) */
308 u32 ps : 1; /* packet sampling */
309 u32 cah : 1; /* cacheable flag */
310 u32 rmt : 1; /* remove tunnel ip header (6rd/dslite only) */
311 u32 ttl : 1;
312 u32 pkt_type : 3;
313 u32 state : 2;
314 u32 udp : 1;
315 u32 sta : 1; /* static entry */
316} __packed;
317
318struct hnat_info_blk2 {
319 u32 qid : 4; /* QID in Qos Port */
320 u32 fqos : 1; /* force to PSE QoS port */
321 u32 dp : 3; /* force to PSE port x
322 * 0:PSE,1:GSW, 2:GMAC,4:PPE,5:QDMA,7=DROP
323 */
324 u32 mcast : 1; /* multicast this packet to CPU */
325 u32 pcpl : 1; /* OSBN */
326 u32 mibf : 1; /* 0:off 1:on PPE MIB counter */
327 u32 alen : 1; /* 0:post 1:pre packet length in accounting */
328 u32 port_mg : 6; /* port meter group */
329 u32 port_ag : 6; /* port account group */
330 u32 dscp : 8; /* DSCP value */
331} __packed;
332
333struct hnat_winfo {
334 u32 bssid : 6; /* WiFi Bssidx */
335 u32 wcid : 8; /* WiFi wtable Idx */
336 u32 rxid : 2; /* WiFi Ring idx */
337} __packed;
338#endif
339
340/* info blk2 for WHNAT */
341struct hnat_info_blk2_whnat {
342 u32 qid : 4; /* QID[3:0] in Qos Port */
343 u32 fqos : 1; /* force to PSE QoS port */
344 u32 dp : 3; /* force to PSE port x
345 * 0:PSE,1:GSW, 2:GMAC,4:PPE,5:QDMA,7=DROP
346 */
347 u32 mcast : 1; /* multicast this packet to CPU */
348 u32 pcpl : 1; /* OSBN */
349 u32 mibf : 1; /* 0:off 1:on PPE MIB counter */
350 u32 alen : 1; /* 0:post 1:pre packet length in accounting */
351 u32 qid2 : 2; /* QID[5:4] in Qos Port */
352 u32 resv : 2;
353 u32 wdmaid : 1; /* 0:to pcie0 dev 1:to pcie1 dev */
354 u32 winfoi : 1; /* 0:off 1:on Wi-Fi hwnat support */
355 u32 port_ag : 6; /* port account group */
356 u32 dscp : 8; /* DSCP value */
357} __packed;
358
359struct hnat_ipv4_hnapt {
360 union {
361 struct hnat_bind_info_blk bfib1;
362 struct hnat_unbind_info_blk udib1;
363 u32 info_blk1;
364 };
365 u32 sip;
366 u32 dip;
367 u16 dport;
368 u16 sport;
369 union {
370 struct hnat_info_blk2 iblk2;
371 struct hnat_info_blk2_whnat iblk2w;
372 u32 info_blk2;
373 };
374 u32 new_sip;
375 u32 new_dip;
376 u16 new_dport;
377 u16 new_sport;
378 u16 m_timestamp; /* For mcast*/
379 u16 resv1;
380 u32 resv2;
381 u32 resv3 : 26;
382 u32 act_dp : 6; /* UDF */
383 u16 vlan1;
384 u16 etype;
385 u32 dmac_hi;
386 union {
developerd35bbcc2022-09-28 22:46:01 +0800387#if !defined(CONFIG_MEDIATEK_NETSYS_V2) && !defined(CONFIG_MEDIATEK_NETSYS_V3)
developerfd40db22021-04-29 10:08:25 +0800388 struct hnat_winfo winfo;
389#endif
390 u16 vlan2;
391 };
392 u16 dmac_lo;
393 u32 smac_hi;
394 u16 pppoe_id;
395 u16 smac_lo;
developer22fd7712022-10-06 14:13:52 +0800396#if defined(CONFIG_MEDIATEK_NETSYS_V3)
developerd35bbcc2022-09-28 22:46:01 +0800397 u16 minfo;
398 u16 resv4;
developerfd40db22021-04-29 10:08:25 +0800399 struct hnat_winfo winfo;
developerd35bbcc2022-09-28 22:46:01 +0800400 struct hnat_winfo_pao winfo_pao;
401 u32 cdrt_id : 8;
402 u32 tops_entry : 6;
403 u32 resv5 : 2;
404 u32 tport_id : 4;
405 u32 resv6 : 12;
developer22fd7712022-10-06 14:13:52 +0800406#elif defined(CONFIG_MEDIATEK_NETSYS_V2)
407 u16 minfo;
408 struct hnat_winfo winfo;
developerfd40db22021-04-29 10:08:25 +0800409#endif
410} __packed;
411
412struct hnat_ipv4_dslite {
413 union {
414 struct hnat_bind_info_blk bfib1;
415 struct hnat_unbind_info_blk udib1;
416 u32 info_blk1;
417 };
418 u32 sip;
419 u32 dip;
420 u16 dport;
421 u16 sport;
422
423 u32 tunnel_sipv6_0;
424 u32 tunnel_sipv6_1;
425 u32 tunnel_sipv6_2;
426 u32 tunnel_sipv6_3;
427
428 u32 tunnel_dipv6_0;
429 u32 tunnel_dipv6_1;
430 u32 tunnel_dipv6_2;
431 u32 tunnel_dipv6_3;
432
433 u8 flow_lbl[3]; /* in order to consist with Linux kernel (should be 20bits) */
434 u8 priority; /* in order to consist with Linux kernel (should be 8bits) */
435 u32 hop_limit : 8;
436 u32 resv2 : 18;
437 u32 act_dp : 6; /* UDF */
438
439 union {
440 struct hnat_info_blk2 iblk2;
441 struct hnat_info_blk2_whnat iblk2w;
442 u32 info_blk2;
443 };
444
445 u16 vlan1;
446 u16 etype;
447 u32 dmac_hi;
448 union {
developerd35bbcc2022-09-28 22:46:01 +0800449#if !defined(CONFIG_MEDIATEK_NETSYS_V2) && !defined(CONFIG_MEDIATEK_NETSYS_V3)
developerfd40db22021-04-29 10:08:25 +0800450 struct hnat_winfo winfo;
451#endif
452 u16 vlan2;
453 };
454 u16 dmac_lo;
455 u32 smac_hi;
456 u16 pppoe_id;
457 u16 smac_lo;
developer22fd7712022-10-06 14:13:52 +0800458#if defined(CONFIG_MEDIATEK_NETSYS_V3)
developerd35bbcc2022-09-28 22:46:01 +0800459 u16 minfo;
460 u16 resv3;
461 struct hnat_winfo winfo;
462 struct hnat_winfo_pao winfo_pao;
463 u32 cdrt_id : 8;
464 u32 tops_entry : 6;
465 u32 resv4 : 2;
466 u32 tport_id : 4;
467 u32 resv5 : 12;
developer22fd7712022-10-06 14:13:52 +0800468#elif defined(CONFIG_MEDIATEK_NETSYS_V2)
469 u16 minfo;
470 struct hnat_winfo winfo;
developerd35bbcc2022-09-28 22:46:01 +0800471#endif
472} __packed;
473
474struct hnat_ipv4_mape {
475 union {
476 struct hnat_bind_info_blk bfib1;
477 struct hnat_unbind_info_blk udib1;
478 u32 info_blk1;
479 };
480 u32 sip;
481 u32 dip;
482 u16 dport;
483 u16 sport;
484
485 u32 tunnel_sipv6_0;
486 u32 tunnel_sipv6_1;
487 u32 tunnel_sipv6_2;
488 u32 tunnel_sipv6_3;
489
490 u32 tunnel_dipv6_0;
491 u32 tunnel_dipv6_1;
492 u32 tunnel_dipv6_2;
493 u32 tunnel_dipv6_3;
494
495 u8 flow_lbl[3]; /* in order to consist with Linux kernel (should be 20bits) */
496 u8 priority; /* in order to consist with Linux kernel (should be 8bits) */
497 u32 hop_limit : 8;
498 u32 resv2 : 18;
499 u32 act_dp : 6; /* UDF */
500
501 union {
502 struct hnat_info_blk2 iblk2;
503 struct hnat_info_blk2_whnat iblk2w;
504 u32 info_blk2;
505 };
506
507 u16 vlan1;
508 u16 etype;
509 u32 dmac_hi;
510 union {
511#if !defined(CONFIG_MEDIATEK_NETSYS_V2) && !defined(CONFIG_MEDIATEK_NETSYS_V3)
512 struct hnat_winfo winfo;
513#endif
514 u16 vlan2;
515 };
516 u16 dmac_lo;
517 u32 smac_hi;
518 u16 pppoe_id;
519 u16 smac_lo;
developer22fd7712022-10-06 14:13:52 +0800520#if defined(CONFIG_MEDIATEK_NETSYS_V3)
developerd35bbcc2022-09-28 22:46:01 +0800521 u16 minfo;
522 u16 resv3;
523 u32 new_sip;
524 u32 new_dip;
525 u16 new_dport;
526 u16 new_sport;
527 struct hnat_winfo winfo;
528 struct hnat_winfo_pao winfo_pao;
529 u32 cdrt_id : 8;
530 u32 tops_entry : 6;
531 u32 resv4 : 2;
532 u32 tport_id : 4;
533 u32 resv5 : 12;
developer22fd7712022-10-06 14:13:52 +0800534#elif defined(CONFIG_MEDIATEK_NETSYS_V2)
535 u16 minfo;
536 struct hnat_winfo winfo;
537 u32 new_sip;
538 u32 new_dip;
539 u16 new_dport;
540 u16 new_sport;
developerfd40db22021-04-29 10:08:25 +0800541#endif
542} __packed;
543
544struct hnat_ipv6_3t_route {
545 union {
546 struct hnat_bind_info_blk bfib1;
547 struct hnat_unbind_info_blk udib1;
548 u32 info_blk1;
549 };
550 u32 ipv6_sip0;
551 u32 ipv6_sip1;
552 u32 ipv6_sip2;
553 u32 ipv6_sip3;
554 u32 ipv6_dip0;
555 u32 ipv6_dip1;
556 u32 ipv6_dip2;
557 u32 ipv6_dip3;
558 u32 prot : 8;
developer729f0272021-06-09 17:28:38 +0800559 u32 hph : 24; /* hash placeholder */
developerfd40db22021-04-29 10:08:25 +0800560
561 u32 resv1;
562 u32 resv2;
563 u32 resv3;
564 u32 resv4 : 26;
565 u32 act_dp : 6; /* UDF */
566
567 union {
568 struct hnat_info_blk2 iblk2;
569 struct hnat_info_blk2_whnat iblk2w;
570 u32 info_blk2;
571 };
572 u16 vlan1;
573 u16 etype;
574 u32 dmac_hi;
575 union {
developerd35bbcc2022-09-28 22:46:01 +0800576#if !defined(CONFIG_MEDIATEK_NETSYS_V2) && !defined(CONFIG_MEDIATEK_NETSYS_V3)
developerfd40db22021-04-29 10:08:25 +0800577 struct hnat_winfo winfo;
578#endif
579 u16 vlan2;
580 };
581 u16 dmac_lo;
582 u32 smac_hi;
583 u16 pppoe_id;
584 u16 smac_lo;
developer22fd7712022-10-06 14:13:52 +0800585#if defined(CONFIG_MEDIATEK_NETSYS_V3)
developerd35bbcc2022-09-28 22:46:01 +0800586 u16 minfo;
587 u16 resv5;
588 struct hnat_winfo winfo;
589 struct hnat_winfo_pao winfo_pao;
590 u32 cdrt_id : 8;
591 u32 tops_entry : 6;
592 u32 resv6 : 2;
593 u32 tport_id : 4;
594 u32 resv7 : 12;
developer22fd7712022-10-06 14:13:52 +0800595#elif defined(CONFIG_MEDIATEK_NETSYS_V2)
596 u16 minfo;
597 struct hnat_winfo winfo;
developerfd40db22021-04-29 10:08:25 +0800598#endif
599} __packed;
600
601struct hnat_ipv6_5t_route {
602 union {
603 struct hnat_bind_info_blk bfib1;
604 struct hnat_unbind_info_blk udib1;
605 u32 info_blk1;
606 };
607 u32 ipv6_sip0;
608 u32 ipv6_sip1;
609 u32 ipv6_sip2;
610 u32 ipv6_sip3;
611 u32 ipv6_dip0;
612 u32 ipv6_dip1;
613 u32 ipv6_dip2;
614 u32 ipv6_dip3;
615 u16 dport;
616 u16 sport;
617
618 u32 resv1;
619 u32 resv2;
620 u32 resv3;
621 u32 resv4 : 26;
622 u32 act_dp : 6; /* UDF */
623
624 union {
625 struct hnat_info_blk2 iblk2;
626 struct hnat_info_blk2_whnat iblk2w;
627 u32 info_blk2;
628 };
629
630 u16 vlan1;
631 u16 etype;
632 u32 dmac_hi;
633 union {
developerd35bbcc2022-09-28 22:46:01 +0800634#if !defined(CONFIG_MEDIATEK_NETSYS_V2) && !defined(CONFIG_MEDIATEK_NETSYS_V3)
developerfd40db22021-04-29 10:08:25 +0800635 struct hnat_winfo winfo;
636#endif
637 u16 vlan2;
638 };
639 u16 dmac_lo;
640 u32 smac_hi;
641 u16 pppoe_id;
642 u16 smac_lo;
developer22fd7712022-10-06 14:13:52 +0800643#if defined(CONFIG_MEDIATEK_NETSYS_V3)
developerd35bbcc2022-09-28 22:46:01 +0800644 u16 minfo;
645 u16 resv5;
developerfd40db22021-04-29 10:08:25 +0800646 struct hnat_winfo winfo;
developerd35bbcc2022-09-28 22:46:01 +0800647 struct hnat_winfo_pao winfo_pao;
648 u32 cdrt_id : 8;
649 u32 tops_entry : 6;
650 u32 resv6 : 2;
651 u32 tport_id : 4;
652 u32 resv7 : 12;
developer22fd7712022-10-06 14:13:52 +0800653#elif defined(CONFIG_MEDIATEK_NETSYS_V2)
654 u16 minfo;
655 struct hnat_winfo winfo;
developerfd40db22021-04-29 10:08:25 +0800656#endif
657} __packed;
658
659struct hnat_ipv6_6rd {
660 union {
661 struct hnat_bind_info_blk bfib1;
662 struct hnat_unbind_info_blk udib1;
663 u32 info_blk1;
664 };
665 u32 ipv6_sip0;
666 u32 ipv6_sip1;
667 u32 ipv6_sip2;
668 u32 ipv6_sip3;
669 u32 ipv6_dip0;
670 u32 ipv6_dip1;
671 u32 ipv6_dip2;
672 u32 ipv6_dip3;
673 u16 dport;
674 u16 sport;
675
676 u32 tunnel_sipv4;
677 u32 tunnel_dipv4;
678 u32 hdr_chksum : 16;
679 u32 dscp : 8;
680 u32 ttl : 8;
681 u32 flag : 3;
682 u32 resv1 : 13;
683 u32 per_flow_6rd_id : 1;
684 u32 resv2 : 9;
685 u32 act_dp : 6; /* UDF */
686
687 union {
688 struct hnat_info_blk2 iblk2;
689 struct hnat_info_blk2_whnat iblk2w;
690 u32 info_blk2;
691 };
692
693 u16 vlan1;
694 u16 etype;
695 u32 dmac_hi;
696 union {
developerd35bbcc2022-09-28 22:46:01 +0800697#if !defined(CONFIG_MEDIATEK_NETSYS_V2) && !defined(CONFIG_MEDIATEK_NETSYS_V3)
developerfd40db22021-04-29 10:08:25 +0800698 struct hnat_winfo winfo;
699#endif
700 u16 vlan2;
701 };
702 u16 dmac_lo;
703 u32 smac_hi;
704 u16 pppoe_id;
705 u16 smac_lo;
developer22fd7712022-10-06 14:13:52 +0800706#if defined(CONFIG_MEDIATEK_NETSYS_V3)
developerd35bbcc2022-09-28 22:46:01 +0800707 u16 minfo;
708 u16 resv3;
709 struct hnat_winfo winfo;
710 struct hnat_winfo_pao winfo_pao;
711 u32 cdrt_id : 8;
712 u32 tops_entry : 6;
713 u32 resv4 : 2;
714 u32 tport_id : 4;
715 u32 resv5 : 12;
developer22fd7712022-10-06 14:13:52 +0800716#elif defined(CONFIG_MEDIATEK_NETSYS_V2)
717 u16 minfo;
718 struct hnat_winfo winfo;
developer5ffc5f12022-10-25 18:51:46 +0800719#endif
720} __packed;
721
722struct hnat_ipv6_hnapt {
723 union {
724 struct hnat_bind_info_blk bfib1;
725 struct hnat_unbind_info_blk udib1;
726 u32 info_blk1;
727 };
728 u32 ipv6_sip0;
729 u32 ipv6_sip1;
730 u32 ipv6_sip2;
731 u32 ipv6_sip3;
732 u32 ipv6_dip0;
733 u32 ipv6_dip1;
734 u32 ipv6_dip2;
735 u32 ipv6_dip3;
736 u16 dport;
737 u16 sport;
738
739 u32 resv1;
740 u32 resv2;
developer22fd7712022-10-06 14:13:52 +0800741 u32 resv3;
developer5ffc5f12022-10-25 18:51:46 +0800742 u32 resv4 : 8;
743 u32 eg_ipv6_dir : 1;
744 u32 eg_keep_ecn : 1;
745 u32 eg_keep_cls : 1;
746 u32 resv5 : 15;
747 u32 act_dp : 6; /* UDF */
748
749 union {
750 struct hnat_info_blk2 iblk2;
751 struct hnat_info_blk2_whnat iblk2w;
752 u32 info_blk2;
753 };
754
755 u16 vlan1;
756 u16 etype;
757 u32 dmac_hi;
758 u16 vlan2;
759 u16 dmac_lo;
760 u32 smac_hi;
761 u16 pppoe_id;
762 u16 smac_lo;
763#if defined(CONFIG_MEDIATEK_NETSYS_V3)
764 u16 minfo;
765 u16 resv6;
766 u32 new_ipv6_ip0;
767 u32 new_ipv6_ip1;
768 u32 new_ipv6_ip2;
769 u32 new_ipv6_ip3;
developer22fd7712022-10-06 14:13:52 +0800770 u16 new_dport;
771 u16 new_sport;
developer5ffc5f12022-10-25 18:51:46 +0800772 struct hnat_winfo winfo;
773 struct hnat_winfo_pao winfo_pao;
774 u32 cdrt_id : 8;
775 u32 tops_entry : 6;
776 u32 resv7 : 2;
777 u32 tport_id : 4;
778 u32 resv8 : 12;
779 u32 resv9;
780 u32 resv10;
781 u32 resv11;
782#elif defined(CONFIG_MEDIATEK_NETSYS_V2)
783 u16 minfo;
784 struct hnat_winfo winfo;
developerfd40db22021-04-29 10:08:25 +0800785#endif
786} __packed;
787
788struct foe_entry {
789 union {
790 struct hnat_unbind_info_blk udib1;
791 struct hnat_bind_info_blk bfib1;
792 struct hnat_ipv4_hnapt ipv4_hnapt;
793 struct hnat_ipv4_dslite ipv4_dslite;
developerd35bbcc2022-09-28 22:46:01 +0800794 struct hnat_ipv4_mape ipv4_mape;
developerfd40db22021-04-29 10:08:25 +0800795 struct hnat_ipv6_3t_route ipv6_3t_route;
796 struct hnat_ipv6_5t_route ipv6_5t_route;
797 struct hnat_ipv6_6rd ipv6_6rd;
developer5ffc5f12022-10-25 18:51:46 +0800798 struct hnat_ipv6_hnapt ipv6_hnapt;
developerfd40db22021-04-29 10:08:25 +0800799 };
800};
801
802/* If user wants to change default FOE entry number, both DEF_ETRY_NUM and
803 * DEF_ETRY_NUM_CFG need to be modified.
804 */
805#define DEF_ETRY_NUM 8192
developerbc53e5f2021-05-21 10:07:17 +0800806/* feasible values : 32768, 16384, 8192, 4096, 2048, 1024 */
developerfd40db22021-04-29 10:08:25 +0800807#define DEF_ETRY_NUM_CFG TABLE_8K
developerbc53e5f2021-05-21 10:07:17 +0800808/* corresponding values : TABLE_32K, TABLE_16K, TABLE_8K, TABLE_4K, TABLE_2K,
809 * TABLE_1K
810 */
developerfd40db22021-04-29 10:08:25 +0800811#define MAX_EXT_DEVS (0x3fU)
812#define MAX_IF_NUM 64
813
developerd35bbcc2022-09-28 22:46:01 +0800814#if defined(CONFIG_MEDIATEK_NETSYS_V3)
815#define MAX_PPE_NUM 3
816#elif defined(CONFIG_MEDIATEK_NETSYS_V2)
developer471f6562021-05-10 20:48:34 +0800817#define MAX_PPE_NUM 2
818#else
819#define MAX_PPE_NUM 1
820#endif
821#define CFG_PPE_NUM (hnat_priv->ppe_num)
822
developerfd40db22021-04-29 10:08:25 +0800823struct mib_entry {
824 u32 byt_cnt_l;
825 u16 byt_cnt_h;
826 u32 pkt_cnt_l;
827 u8 pkt_cnt_h;
828 u8 resv0;
829 u32 resv1;
830} __packed;
831
832struct hnat_accounting {
833 u64 bytes;
834 u64 packets;
835};
836
837enum mtk_hnat_version {
developer4164cfe2022-12-01 11:27:41 +0800838 MTK_HNAT_V1_1 = 1, /* version 1.1: mt7621, mt7623 */
839 MTK_HNAT_V1_2, /* version 1.2: mt7622 */
840 MTK_HNAT_V1_3, /* version 1.3: mt7629 */
841 MTK_HNAT_V2, /* version 2: mt7981, mt7986 */
842 MTK_HNAT_V3, /* version 3: mt7988 */
developerfd40db22021-04-29 10:08:25 +0800843};
844
845struct mtk_hnat_data {
846 u8 num_of_sch;
847 bool whnat;
848 bool per_flow_accounting;
849 bool mcast;
850 enum mtk_hnat_version version;
851};
852
developere8b7dfa2023-04-20 10:16:44 +0800853struct map46 {
854 u32 ipv4;
855 struct in6_addr ipv6;
856 struct list_head list;
857};
858
859struct xlat_conf {
860 struct list_head map_list;
861 struct in6_addr prefix;
862 int prefix_len;
863};
864
developerfd40db22021-04-29 10:08:25 +0800865struct mtk_hnat {
866 struct device *dev;
867 void __iomem *fe_base;
developer471f6562021-05-10 20:48:34 +0800868 void __iomem *ppe_base[MAX_PPE_NUM];
869 struct foe_entry *foe_table_cpu[MAX_PPE_NUM];
870 dma_addr_t foe_table_dev[MAX_PPE_NUM];
developerfd40db22021-04-29 10:08:25 +0800871 u8 enable;
872 u8 enable1;
873 struct dentry *root;
developer471f6562021-05-10 20:48:34 +0800874 struct debugfs_regset32 *regset[MAX_PPE_NUM];
developerfd40db22021-04-29 10:08:25 +0800875
developer471f6562021-05-10 20:48:34 +0800876 struct mib_entry *foe_mib_cpu[MAX_PPE_NUM];
877 dma_addr_t foe_mib_dev[MAX_PPE_NUM];
878 struct hnat_accounting *acct[MAX_PPE_NUM];
developerfd40db22021-04-29 10:08:25 +0800879 const struct mtk_hnat_data *data;
880
881 /*devices we plays for*/
882 char wan[IFNAMSIZ];
883 char lan[IFNAMSIZ];
developerd35bbcc2022-09-28 22:46:01 +0800884 char lan2[IFNAMSIZ];
developerfd40db22021-04-29 10:08:25 +0800885 char ppd[IFNAMSIZ];
886 u16 lvid;
887 u16 wvid;
888
889 struct reset_control *rstc;
890
developer471f6562021-05-10 20:48:34 +0800891 u8 ppe_num;
developerfd40db22021-04-29 10:08:25 +0800892 u8 gmac_num;
893 u8 wan_dsa_port;
894 struct ppe_mcast_table *pmcast;
895
896 u32 foe_etry_num;
developer8051e042022-04-08 13:26:36 +0800897 u32 etry_num_cfg;
developerfd40db22021-04-29 10:08:25 +0800898 struct net_device *g_ppdev;
developer8c9c0d02021-06-18 16:15:37 +0800899 struct net_device *g_wandev;
developerfd40db22021-04-29 10:08:25 +0800900 struct net_device *wifi_hook_if[MAX_IF_NUM];
901 struct extdev_entry *ext_if[MAX_EXT_DEVS];
902 struct timer_list hnat_sma_build_entry_timer;
903 struct timer_list hnat_reset_timestamp_timer;
904 struct timer_list hnat_mcast_check_timer;
developer30a47682021-11-02 17:06:14 +0800905 bool nf_stat_en;
developere8b7dfa2023-04-20 10:16:44 +0800906 struct xlat_conf xlat;
developerfd40db22021-04-29 10:08:25 +0800907};
908
909struct extdev_entry {
910 char name[IFNAMSIZ];
911 struct net_device *dev;
912};
913
914struct tcpudphdr {
915 __be16 src;
916 __be16 dst;
917};
918
919enum FoeEntryState { INVALID = 0, UNBIND = 1, BIND = 2, FIN = 3 };
920
921enum FoeIpAct {
922 IPV4_HNAPT = 0,
923 IPV4_HNAT = 1,
924 IPV4_DSLITE = 3,
925 IPV6_3T_ROUTE = 4,
926 IPV6_5T_ROUTE = 5,
927 IPV6_6RD = 7,
developerfd40db22021-04-29 10:08:25 +0800928 IPV4_MAP_T = 8,
929 IPV4_MAP_E = 9,
developer5ffc5f12022-10-25 18:51:46 +0800930 IPV6_HNAPT = 10,
931 IPV6_HNAT = 11,
developerfd40db22021-04-29 10:08:25 +0800932};
933
934/*--------------------------------------------------------------------------*/
935/* Common Definition*/
936/*--------------------------------------------------------------------------*/
937
938#define HNAT_SW_VER "1.1.0"
939#define HASH_SEED_KEY 0x12345678
940
941/*PPE_TB_CFG value*/
developerd35bbcc2022-09-28 22:46:01 +0800942#define ENTRY_128B 0
943#define ENTRY_96B 1
developerfd40db22021-04-29 10:08:25 +0800944#define ENTRY_80B 1
developerfd40db22021-04-29 10:08:25 +0800945#define TABLE_1K 0
946#define TABLE_2K 1
947#define TABLE_4K 2
948#define TABLE_8K 3
949#define TABLE_16K 4
developerbc53e5f2021-05-21 10:07:17 +0800950#define TABLE_32K 5
developerfd40db22021-04-29 10:08:25 +0800951#define SMA_DROP 0 /* Drop the packet */
952#define SMA_DROP2 1 /* Drop the packet */
953#define SMA_ONLY_FWD_CPU 2 /* Only Forward to CPU */
954#define SMA_FWD_CPU_BUILD_ENTRY 3 /* Forward to CPU and build new FOE entry */
955#define HASH_MODE_0 0
956#define HASH_MODE_1 1
957#define HASH_MODE_2 2
958#define HASH_MODE_3 3
959
960/*PPE_FLOW_CFG*/
961#define BIT_FUC_FOE BIT(2)
962#define BIT_FMC_FOE BIT(1)
963#define BIT_FBC_FOE BIT(0)
964#define BIT_UDP_IP4F_NAT_EN BIT(7) /*Enable IPv4 fragment + UDP packet NAT*/
965#define BIT_IPV6_3T_ROUTE_EN BIT(8)
966#define BIT_IPV6_5T_ROUTE_EN BIT(9)
967#define BIT_IPV6_6RD_EN BIT(10)
developere8b7dfa2023-04-20 10:16:44 +0800968#define BIT_IPV6_464XLAT_EN BIT(11)
developerfd40db22021-04-29 10:08:25 +0800969#define BIT_IPV4_NAT_EN BIT(12)
970#define BIT_IPV4_NAPT_EN BIT(13)
971#define BIT_IPV4_DSL_EN BIT(14)
972#define BIT_MIB_BUSY BIT(16)
973#define BIT_IPV4_NAT_FRAG_EN BIT(17)
974#define BIT_IPV4_HASH_GREK BIT(19)
975#define BIT_IPV6_HASH_GREK BIT(20)
976#define BIT_IPV4_MAPE_EN BIT(21)
977#define BIT_IPV4_MAPT_EN BIT(22)
developer5ffc5f12022-10-25 18:51:46 +0800978#define BIT_IPV6_NAT_EN BIT(23)
979#define BIT_IPV6_NAPT_EN BIT(24)
980#define BIT_CS0_RM_ALL_IP6_IP_EN BIT(25)
developerfd40db22021-04-29 10:08:25 +0800981
982/*GDMA_FWD_CFG value*/
developer471f6562021-05-10 20:48:34 +0800983#define BITS_GDM_UFRC_P_PPE (NR_PPE0_PORT << 12)
984#define BITS_GDM_BFRC_P_PPE (NR_PPE0_PORT << 8)
985#define BITS_GDM_MFRC_P_PPE (NR_PPE0_PORT << 4)
986#define BITS_GDM_OFRC_P_PPE (NR_PPE0_PORT << 0)
developerfd40db22021-04-29 10:08:25 +0800987#define BITS_GDM_ALL_FRC_P_PPE \
988 (BITS_GDM_UFRC_P_PPE | BITS_GDM_BFRC_P_PPE | BITS_GDM_MFRC_P_PPE | \
989 BITS_GDM_OFRC_P_PPE)
990
developerd35bbcc2022-09-28 22:46:01 +0800991#define BITS_GDM_UFRC_P_PPE1 (NR_PPE1_PORT << 12)
992#define BITS_GDM_BFRC_P_PPE1 (NR_PPE1_PORT << 8)
993#define BITS_GDM_MFRC_P_PPE1 (NR_PPE1_PORT << 4)
994#define BITS_GDM_OFRC_P_PPE1 (NR_PPE1_PORT << 0)
995#define BITS_GDM_ALL_FRC_P_PPE1 \
996 (BITS_GDM_UFRC_P_PPE1 | BITS_GDM_BFRC_P_PPE1 | \
997 BITS_GDM_MFRC_P_PPE1 | BITS_GDM_OFRC_P_PPE1)
998
999#define BITS_GDM_UFRC_P_PPE2 (NR_PPE2_PORT << 12)
1000#define BITS_GDM_BFRC_P_PPE2 (NR_PPE2_PORT << 8)
1001#define BITS_GDM_MFRC_P_PPE2 (NR_PPE2_PORT << 4)
1002#define BITS_GDM_OFRC_P_PPE2 (NR_PPE2_PORT << 0)
1003#define BITS_GDM_ALL_FRC_P_PPE2 \
1004 (BITS_GDM_UFRC_P_PPE2 | BITS_GDM_BFRC_P_PPE2 | \
1005 BITS_GDM_MFRC_P_PPE2 | BITS_GDM_OFRC_P_PPE2)
1006
developerfd40db22021-04-29 10:08:25 +08001007#define BITS_GDM_UFRC_P_CPU_PDMA (NR_PDMA_PORT << 12)
1008#define BITS_GDM_BFRC_P_CPU_PDMA (NR_PDMA_PORT << 8)
1009#define BITS_GDM_MFRC_P_CPU_PDMA (NR_PDMA_PORT << 4)
1010#define BITS_GDM_OFRC_P_CPU_PDMA (NR_PDMA_PORT << 0)
1011#define BITS_GDM_ALL_FRC_P_CPU_PDMA \
1012 (BITS_GDM_UFRC_P_CPU_PDMA | BITS_GDM_BFRC_P_CPU_PDMA | \
1013 BITS_GDM_MFRC_P_CPU_PDMA | BITS_GDM_OFRC_P_CPU_PDMA)
1014
1015#define BITS_GDM_UFRC_P_CPU_QDMA (NR_QDMA_PORT << 12)
1016#define BITS_GDM_BFRC_P_CPU_QDMA (NR_QDMA_PORT << 8)
1017#define BITS_GDM_MFRC_P_CPU_QDMA (NR_QDMA_PORT << 4)
1018#define BITS_GDM_OFRC_P_CPU_QDMA (NR_QDMA_PORT << 0)
1019#define BITS_GDM_ALL_FRC_P_CPU_QDMA \
1020 (BITS_GDM_UFRC_P_CPU_QDMA | BITS_GDM_BFRC_P_CPU_QDMA | \
1021 BITS_GDM_MFRC_P_CPU_QDMA | BITS_GDM_OFRC_P_CPU_QDMA)
1022
1023#define BITS_GDM_UFRC_P_DISCARD (NR_DISCARD << 12)
1024#define BITS_GDM_BFRC_P_DISCARD (NR_DISCARD << 8)
1025#define BITS_GDM_MFRC_P_DISCARD (NR_DISCARD << 4)
1026#define BITS_GDM_OFRC_P_DISCARD (NR_DISCARD << 0)
1027#define BITS_GDM_ALL_FRC_P_DISCARD \
1028 (BITS_GDM_UFRC_P_DISCARD | BITS_GDM_BFRC_P_DISCARD | \
1029 BITS_GDM_MFRC_P_DISCARD | BITS_GDM_OFRC_P_DISCARD)
1030
1031#define hnat_is_enabled(hnat_priv) (hnat_priv->enable)
1032#define hnat_enabled(hnat_priv) (hnat_priv->enable = 1)
1033#define hnat_disabled(hnat_priv) (hnat_priv->enable = 0)
1034#define hnat_is_enabled1(hnat_priv) (hnat_priv->enable1)
1035#define hnat_enabled1(hnat_priv) (hnat_priv->enable1 = 1)
1036#define hnat_disabled1(hnat_priv) (hnat_priv->enable1 = 0)
1037
1038#define entry_hnat_is_bound(e) (e->bfib1.state == BIND)
1039#define entry_hnat_state(e) (e->bfib1.state)
1040
1041#define skb_hnat_is_hashed(skb) \
1042 (skb_hnat_entry(skb) != 0x3fff && skb_hnat_entry(skb) < hnat_priv->foe_etry_num)
developerd35bbcc2022-09-28 22:46:01 +08001043#define FROM_GE_LAN_GRP(skb) (FROM_GE_LAN(skb) | FROM_GE_LAN2(skb))
developerfd40db22021-04-29 10:08:25 +08001044#define FROM_GE_LAN(skb) (skb_hnat_iface(skb) == FOE_MAGIC_GE_LAN)
developerd35bbcc2022-09-28 22:46:01 +08001045#define FROM_GE_LAN2(skb) (skb_hnat_iface(skb) == FOE_MAGIC_GE_LAN2)
developerfd40db22021-04-29 10:08:25 +08001046#define FROM_GE_WAN(skb) (skb_hnat_iface(skb) == FOE_MAGIC_GE_WAN)
1047#define FROM_GE_PPD(skb) (skb_hnat_iface(skb) == FOE_MAGIC_GE_PPD)
1048#define FROM_GE_VIRTUAL(skb) (skb_hnat_iface(skb) == FOE_MAGIC_GE_VIRTUAL)
1049#define FROM_EXT(skb) (skb_hnat_iface(skb) == FOE_MAGIC_EXT)
developere567ad32021-05-25 17:16:17 +08001050#define FROM_WED(skb) ((skb_hnat_iface(skb) == FOE_MAGIC_WED0) || \
1051 (skb_hnat_iface(skb) == FOE_MAGIC_WED1))
developerfd40db22021-04-29 10:08:25 +08001052#define FOE_MAGIC_GE_LAN 0x1
1053#define FOE_MAGIC_GE_WAN 0x2
1054#define FOE_MAGIC_EXT 0x3
1055#define FOE_MAGIC_GE_VIRTUAL 0x4
1056#define FOE_MAGIC_GE_PPD 0x5
developerd35bbcc2022-09-28 22:46:01 +08001057#define FOE_MAGIC_GE_LAN2 0x6
developere567ad32021-05-25 17:16:17 +08001058#define FOE_MAGIC_WED0 0x78
1059#define FOE_MAGIC_WED1 0x79
developerd35bbcc2022-09-28 22:46:01 +08001060#define FOE_MAGIC_WED2 0x7A
developerfd40db22021-04-29 10:08:25 +08001061#define FOE_INVALID 0xf
1062#define index6b(i) (0x3fU - i)
1063
1064#define IPV4_HNAPT 0
1065#define IPV4_HNAT 1
1066#define IP_FORMAT(addr) \
1067 (((unsigned char *)&addr)[3], ((unsigned char *)&addr)[2], \
1068 ((unsigned char *)&addr)[1], ((unsigned char *)&addr)[0])
1069
1070/*PSE Ports*/
1071#define NR_PDMA_PORT 0
1072#define NR_GMAC1_PORT 1
1073#define NR_GMAC2_PORT 2
developerd35bbcc2022-09-28 22:46:01 +08001074#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3)
developer471f6562021-05-10 20:48:34 +08001075#define NR_WHNAT_WDMA_PORT EINVAL
1076#define NR_PPE0_PORT 3
1077#define NR_PPE1_PORT 4
developerd35bbcc2022-09-28 22:46:01 +08001078#define NR_PPE2_PORT 0xC
developer471f6562021-05-10 20:48:34 +08001079#else
developerfd40db22021-04-29 10:08:25 +08001080#define NR_WHNAT_WDMA_PORT 3
developer471f6562021-05-10 20:48:34 +08001081#define NR_PPE0_PORT 4
1082#endif
developerfd40db22021-04-29 10:08:25 +08001083#define NR_QDMA_PORT 5
1084#define NR_DISCARD 7
1085#define NR_WDMA0_PORT 8
1086#define NR_WDMA1_PORT 9
developerd35bbcc2022-09-28 22:46:01 +08001087#define NR_GMAC3_PORT 15
developerfd40db22021-04-29 10:08:25 +08001088#define LAN_DEV_NAME hnat_priv->lan
developerd35bbcc2022-09-28 22:46:01 +08001089#define LAN2_DEV_NAME hnat_priv->lan2
developerfd40db22021-04-29 10:08:25 +08001090#define IS_WAN(dev) \
1091 (!strncmp((dev)->name, hnat_priv->wan, strlen(hnat_priv->wan)))
developerd35bbcc2022-09-28 22:46:01 +08001092#define IS_LAN_GRP(dev) (IS_LAN(dev) | IS_LAN2(dev))
developerfd40db22021-04-29 10:08:25 +08001093#define IS_LAN(dev) (!strncmp(dev->name, LAN_DEV_NAME, strlen(LAN_DEV_NAME)))
developerd35bbcc2022-09-28 22:46:01 +08001094#define IS_LAN2(dev) (!strncmp(dev->name, LAN2_DEV_NAME, \
1095 strlen(LAN2_DEV_NAME)))
developerfd40db22021-04-29 10:08:25 +08001096#define IS_BR(dev) (!strncmp(dev->name, "br", 2))
1097#define IS_WHNAT(dev) \
1098 ((hnat_priv->data->whnat && \
1099 (get_wifi_hook_if_index_from_dev(dev) != 0)) ? 1 : 0)
1100#define IS_EXT(dev) ((get_index_from_dev(dev) != 0) ? 1 : 0)
1101#define IS_PPD(dev) (!strcmp(dev->name, hnat_priv->ppd))
1102#define IS_IPV4_HNAPT(x) (((x)->bfib1.pkt_type == IPV4_HNAPT) ? 1 : 0)
1103#define IS_IPV4_HNAT(x) (((x)->bfib1.pkt_type == IPV4_HNAT) ? 1 : 0)
1104#define IS_IPV4_GRP(x) (IS_IPV4_HNAPT(x) | IS_IPV4_HNAT(x))
1105#define IS_IPV4_DSLITE(x) (((x)->bfib1.pkt_type == IPV4_DSLITE) ? 1 : 0)
1106#define IS_IPV4_MAPE(x) (((x)->bfib1.pkt_type == IPV4_MAP_E) ? 1 : 0)
1107#define IS_IPV4_MAPT(x) (((x)->bfib1.pkt_type == IPV4_MAP_T) ? 1 : 0)
1108#define IS_IPV6_3T_ROUTE(x) (((x)->bfib1.pkt_type == IPV6_3T_ROUTE) ? 1 : 0)
1109#define IS_IPV6_5T_ROUTE(x) (((x)->bfib1.pkt_type == IPV6_5T_ROUTE) ? 1 : 0)
1110#define IS_IPV6_6RD(x) (((x)->bfib1.pkt_type == IPV6_6RD) ? 1 : 0)
developer5ffc5f12022-10-25 18:51:46 +08001111#define IS_IPV6_HNAPT(x) (((x)->bfib1.pkt_type == IPV6_HNAPT) ? 1 : 0)
1112#define IS_IPV6_HNAT(x) (((x)->bfib1.pkt_type == IPV6_HNAT) ? 1 : 0)
developerfd40db22021-04-29 10:08:25 +08001113#define IS_IPV6_GRP(x) \
1114 (IS_IPV6_3T_ROUTE(x) | IS_IPV6_5T_ROUTE(x) | IS_IPV6_6RD(x) | \
developer5ffc5f12022-10-25 18:51:46 +08001115 IS_IPV4_DSLITE(x) | IS_IPV4_MAPE(x) | IS_IPV4_MAPT(x) | \
1116 IS_IPV6_HNAPT(x) | IS_IPV6_HNAT(x))
developerfd40db22021-04-29 10:08:25 +08001117#define IS_BOND_MODE (!strncmp(LAN_DEV_NAME, "bond", 4))
1118#define IS_GMAC1_MODE ((hnat_priv->gmac_num == 1) ? 1 : 0)
developeraf07fad2021-11-19 17:53:42 +08001119#define IS_HQOS_MODE (qos_toggle == 1)
1120#define IS_PPPQ_MODE (qos_toggle == 2) /* Per Port Per Queue */
developer934756a2022-11-18 14:51:34 +08001121#define IS_PPPQ_PATH(dev, skb) \
1122 ((IS_DSA_1G_LAN(dev) || IS_DSA_WAN(dev)) || \
1123 (FROM_WED(skb) && IS_DSA_LAN(dev)))
developer47545a32022-11-15 16:06:58 +08001124#define IS_HQOS_DL_MODE (IS_HQOS_MODE && qos_dl_toggle)
1125#define IS_HQOS_UL_MODE (IS_HQOS_MODE && qos_ul_toggle)
developer70cdf6e2021-12-07 18:58:35 +08001126#define MAX_PPPQ_PORT_NUM 6
developerfd40db22021-04-29 10:08:25 +08001127
1128#define es(entry) (entry_state[entry->bfib1.state])
1129#define ei(entry, end) (hnat_priv->foe_etry_num - (int)(end - entry))
1130#define pt(entry) (packet_type[entry->ipv4_hnapt.bfib1.pkt_type])
1131#define ipv4_smac(mac, e) \
1132 ({ \
1133 mac[0] = e->ipv4_hnapt.smac_hi[3]; \
1134 mac[1] = e->ipv4_hnapt.smac_hi[2]; \
1135 mac[2] = e->ipv4_hnapt.smac_hi[1]; \
1136 mac[3] = e->ipv4_hnapt.smac_hi[0]; \
1137 mac[4] = e->ipv4_hnapt.smac_lo[1]; \
1138 mac[5] = e->ipv4_hnapt.smac_lo[0]; \
1139 })
1140#define ipv4_dmac(mac, e) \
1141 ({ \
1142 mac[0] = e->ipv4_hnapt.dmac_hi[3]; \
1143 mac[1] = e->ipv4_hnapt.dmac_hi[2]; \
1144 mac[2] = e->ipv4_hnapt.dmac_hi[1]; \
1145 mac[3] = e->ipv4_hnapt.dmac_hi[0]; \
1146 mac[4] = e->ipv4_hnapt.dmac_lo[1]; \
1147 mac[5] = e->ipv4_hnapt.dmac_lo[0]; \
1148 })
1149
1150#define IS_DSA_LAN(dev) (!strncmp(dev->name, "lan", 3))
developer399ec072022-06-24 16:07:41 +08001151#define IS_DSA_1G_LAN(dev) (!strncmp(dev->name, "lan", 3) && \
1152 strcmp(dev->name, "lan5"))
developerfd40db22021-04-29 10:08:25 +08001153#define IS_DSA_WAN(dev) (!strncmp(dev->name, "wan", 3))
1154#define NONE_DSA_PORT 0xff
1155#define MAX_CRSN_NUM 32
1156#define IPV6_HDR_LEN 40
developer5ffc5f12022-10-25 18:51:46 +08001157#define IPV6_SNAT 0
1158#define IPV6_DNAT 1
developerfd40db22021-04-29 10:08:25 +08001159
1160/*QDMA_PAGE value*/
1161#define NUM_OF_Q_PER_PAGE 16
1162
1163/*IPv6 Header*/
1164#ifndef NEXTHDR_IPIP
1165#define NEXTHDR_IPIP 4
1166#endif
1167
1168extern const struct of_device_id of_hnat_match[];
1169extern struct mtk_hnat *hnat_priv;
1170
1171#if defined(CONFIG_NET_DSA_MT7530)
developeraf07fad2021-11-19 17:53:42 +08001172u32 hnat_dsa_fill_stag(const struct net_device *netdev,
1173 struct foe_entry *entry,
1174 struct flow_offload_hw_path *hw_path,
1175 u16 eth_proto, int mape);
developerfd40db22021-04-29 10:08:25 +08001176
1177static inline bool hnat_dsa_is_enable(struct mtk_hnat *priv)
1178{
1179 return (priv->wan_dsa_port != NONE_DSA_PORT);
1180}
1181#else
developeraf07fad2021-11-19 17:53:42 +08001182static inline u32 hnat_dsa_fill_stag(const struct net_device *netdev,
1183 struct foe_entry *entry,
1184 struct flow_offload_hw_path *hw_path,
1185 u16 eth_proto, int mape)
developerfd40db22021-04-29 10:08:25 +08001186{
developerd35bbcc2022-09-28 22:46:01 +08001187 return 0;
developerfd40db22021-04-29 10:08:25 +08001188}
1189
1190static inline bool hnat_dsa_is_enable(struct mtk_hnat *priv)
1191{
1192 return false;
1193}
1194#endif
1195
1196void hnat_deinit_debugfs(struct mtk_hnat *h);
1197int hnat_init_debugfs(struct mtk_hnat *h);
1198int hnat_register_nf_hooks(void);
1199void hnat_unregister_nf_hooks(void);
1200int whnat_adjust_nf_hooks(void);
1201int mtk_hqos_ptype_cb(struct sk_buff *skb, struct net_device *dev,
1202 struct packet_type *pt, struct net_device *unused);
1203extern int dbg_cpu_reason;
1204extern int debug_level;
developere8b7dfa2023-04-20 10:16:44 +08001205extern int xlat_toggle;
1206extern struct hnat_desc headroom[DEF_ETRY_NUM];
developer47545a32022-11-15 16:06:58 +08001207extern int qos_dl_toggle;
1208extern int qos_ul_toggle;
developerfd40db22021-04-29 10:08:25 +08001209extern int hook_toggle;
1210extern int mape_toggle;
developeraf07fad2021-11-19 17:53:42 +08001211extern int qos_toggle;
developerfd40db22021-04-29 10:08:25 +08001212
1213int ext_if_add(struct extdev_entry *ext_entry);
1214int ext_if_del(struct extdev_entry *ext_entry);
1215void cr_set_field(void __iomem *reg, u32 field, u32 val);
1216int mtk_sw_nat_hook_tx(struct sk_buff *skb, int gmac_no);
1217int mtk_sw_nat_hook_rx(struct sk_buff *skb);
1218void mtk_ppe_dev_register_hook(struct net_device *dev);
1219void mtk_ppe_dev_unregister_hook(struct net_device *dev);
1220int nf_hnat_netdevice_event(struct notifier_block *unused, unsigned long event,
1221 void *ptr);
1222int nf_hnat_netevent_handler(struct notifier_block *unused, unsigned long event,
1223 void *ptr);
1224uint32_t foe_dump_pkt(struct sk_buff *skb);
1225uint32_t hnat_cpu_reason_cnt(struct sk_buff *skb);
1226int hnat_enable_hook(void);
1227int hnat_disable_hook(void);
1228void hnat_cache_ebl(int enable);
developer70cdf6e2021-12-07 18:58:35 +08001229void hnat_qos_shaper_ebl(u32 id, u32 enable);
developerfd40db22021-04-29 10:08:25 +08001230void set_gmac_ppe_fwd(int gmac_no, int enable);
developer4c32b7a2021-11-13 16:46:43 +08001231int entry_detail(u32 ppe_id, int index);
developer731b98f2021-09-17 17:44:37 +08001232int entry_delete_by_mac(u8 *mac);
developer4c32b7a2021-11-13 16:46:43 +08001233int entry_delete(u32 ppe_id, int index);
developer8051e042022-04-08 13:26:36 +08001234int hnat_warm_init(void);
developere8b7dfa2023-04-20 10:16:44 +08001235u32 hnat_get_ppe_hash(struct foe_entry *entry);
1236int mtk_ppe_get_xlat_v4_by_v6(struct in6_addr *ipv6, u32 *ipv4);
1237int mtk_ppe_get_xlat_v6_by_v4(u32 *ipv4, struct in6_addr *ipv6,
1238 struct in6_addr *prefix);
developer8051e042022-04-08 13:26:36 +08001239
developer4c32b7a2021-11-13 16:46:43 +08001240struct hnat_accounting *hnat_get_count(struct mtk_hnat *h, u32 ppe_id,
developer30a47682021-11-02 17:06:14 +08001241 u32 index, struct hnat_accounting *diff);
developerfd40db22021-04-29 10:08:25 +08001242
1243static inline u16 foe_timestamp(struct mtk_hnat *h)
1244{
1245 return (readl(hnat_priv->fe_base + 0x0010)) & 0xffff;
1246}