blob: 19482e5d7c592d67b7bd4db952c8193e64c316a6 [file] [log] [blame]
developerfd40db22021-04-29 10:08:25 +08001/* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
4 *
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
9 *
10 * Copyright (C) 2014-2016 Sean Wang <sean.wang@mediatek.com>
11 * Copyright (C) 2016-2017 John Crispin <blogic@openwrt.org>
12 */
13
14#include <linux/debugfs.h>
15#include <linux/string.h>
16#include <linux/if.h>
17#include <linux/if_ether.h>
18#include <net/netevent.h>
19#include <linux/mod_devicetable.h>
20#include "hnat_mcast.h"
21
22/*--------------------------------------------------------------------------*/
23/* Register Offset*/
24/*--------------------------------------------------------------------------*/
25#define PPE_GLO_CFG 0x00
26#define PPE_FLOW_CFG 0x04
27#define PPE_IP_PROT_CHK 0x08
28#define PPE_IP_PROT_0 0x0C
29#define PPE_IP_PROT_1 0x10
30#define PPE_IP_PROT_2 0x14
31#define PPE_IP_PROT_3 0x18
32#define PPE_TB_CFG 0x1C
33#define PPE_TB_BASE 0x20
34#define PPE_TB_USED 0x24
35#define PPE_BNDR 0x28
36#define PPE_BIND_LMT_0 0x2C
37#define PPE_BIND_LMT_1 0x30
38#define PPE_KA 0x34
39#define PPE_UNB_AGE 0x38
40#define PPE_BND_AGE_0 0x3C
41#define PPE_BND_AGE_1 0x40
42#define PPE_HASH_SEED 0x44
43#define PPE_DFT_CPORT 0x48
44#define PPE_DFT_CPORT1 0x4C
45#define PPE_MCAST_PPSE 0x84
46#define PPE_MCAST_L_0 0x88
47#define PPE_MCAST_H_0 0x8C
48#define PPE_MCAST_L_1 0x90
49#define PPE_MCAST_H_1 0x94
50#define PPE_MCAST_L_2 0x98
51#define PPE_MCAST_H_2 0x9C
52#define PPE_MCAST_L_3 0xA0
53#define PPE_MCAST_H_3 0xA4
54#define PPE_MCAST_L_4 0xA8
55#define PPE_MCAST_H_4 0xAC
56#define PPE_MCAST_L_5 0xB0
57#define PPE_MCAST_H_5 0xB4
58#define PPE_MCAST_L_6 0xBC
59#define PPE_MCAST_H_6 0xC0
60#define PPE_MCAST_L_7 0xC4
61#define PPE_MCAST_H_7 0xC8
62#define PPE_MCAST_L_8 0xCC
63#define PPE_MCAST_H_8 0xD0
64#define PPE_MCAST_L_9 0xD4
65#define PPE_MCAST_H_9 0xD8
66#define PPE_MCAST_L_A 0xDC
67#define PPE_MCAST_H_A 0xE0
68#define PPE_MCAST_L_B 0xE4
69#define PPE_MCAST_H_B 0xE8
70#define PPE_MCAST_L_C 0xEC
71#define PPE_MCAST_H_C 0xF0
72#define PPE_MCAST_L_D 0xF4
73#define PPE_MCAST_H_D 0xF8
74#define PPE_MCAST_L_E 0xFC
75#define PPE_MCAST_H_E 0xE0
76#define PPE_MCAST_L_F 0x100
77#define PPE_MCAST_H_F 0x104
78#define PPE_MCAST_L_10 0xC00
79#define PPE_MCAST_H_10 0xC04
80#define PPE_MTU_DRP 0x108
81#define PPE_MTU_VLYR_0 0x10C
82#define PPE_MTU_VLYR_1 0x110
83#define PPE_MTU_VLYR_2 0x114
84#define PPE_VPM_TPID 0x118
85#define PPE_CAH_CTRL 0x120
86#define PPE_CAH_TAG_SRH 0x124
87#define PPE_CAH_LINE_RW 0x128
88#define PPE_CAH_WDATA 0x12C
89#define PPE_CAH_RDATA 0x130
90
91#define PPE_MIB_CFG 0X134
92#define PPE_MIB_TB_BASE 0X138
93#define PPE_MIB_SER_CR 0X13C
94#define PPE_MIB_SER_R0 0X140
95#define PPE_MIB_SER_R1 0X144
96#define PPE_MIB_SER_R2 0X148
97#define PPE_MIB_CAH_CTRL 0X150
98#define PPE_MIB_CAH_TAG_SRH 0X154
99#define PPE_MIB_CAH_LINE_RW 0X158
100#define PPE_MIB_CAH_WDATA 0X15C
101#define PPE_MIB_CAH_RDATA 0X160
102#define PPE_SBW_CTRL 0x174
103
104#define GDMA1_FWD_CFG 0x500
105#define GDMA2_FWD_CFG 0x1500
106
107#define QTX_CFG(x) (QDMA_BASE + ((x) * 0x10))
108#define QTX_SCH(x) (QDMA_BASE + 0x4 + ((x) * 0x10))
109#define QDMA_PAGE (QDMA_BASE + 0x1f0)
110#define QDMA_TX_2SCH_BASE (QDMA_BASE + 0x214)
111#define QTX_MIB_IF (QDMA_BASE + 0x2bc)
112#define QDMA_TX_4SCH_BASE(x) (QDMA_BASE + 0x398 + (((x) >> 1) * 0x4))
113
114/*--------------------------------------------------------------------------*/
115/* Register Mask*/
116/*--------------------------------------------------------------------------*/
117/* PPE_TB_CFG mask */
118#define TB_ETRY_NUM (0x7 << 0) /* RW */
119#define TB_ENTRY_SIZE (0x1 << 3) /* RW */
120#define SMA (0x3 << 4) /* RW */
121#define NTU_AGE (0x1 << 7) /* RW */
122#define UNBD_AGE (0x1 << 8) /* RW */
123#define TCP_AGE (0x1 << 9) /* RW */
124#define UDP_AGE (0x1 << 10) /* RW */
125#define FIN_AGE (0x1 << 11) /* RW */
126#define KA_CFG (0x3 << 12)
127#define HASH_MODE (0x3 << 14) /* RW */
128#define SCAN_MODE (0x3 << 16) /* RW */
129#define XMODE (0x3 << 18) /* RW */
130
131/*PPE_CAH_CTRL mask*/
132#define CAH_EN (0x1 << 0) /* RW */
133#define CAH_X_MODE (0x1 << 9) /* RW */
134
135/*PPE_UNB_AGE mask*/
136#define UNB_DLTA (0xff << 0) /* RW */
137#define UNB_MNP (0xffff << 16) /* RW */
138
139/*PPE_BND_AGE_0 mask*/
140#define UDP_DLTA (0xffff << 0) /* RW */
141#define NTU_DLTA (0xffff << 16) /* RW */
142
143/*PPE_BND_AGE_1 mask*/
144#define TCP_DLTA (0xffff << 0) /* RW */
145#define FIN_DLTA (0xffff << 16) /* RW */
146
147/*PPE_KA mask*/
148#define KA_T (0xffff << 0) /* RW */
149#define TCP_KA (0xff << 16) /* RW */
150#define UDP_KA (0xff << 24) /* RW */
151
152/*PPE_BIND_LMT_0 mask*/
153#define QURT_LMT (0x3ff << 0) /* RW */
154#define HALF_LMT (0x3ff << 16) /* RW */
155
156/*PPE_BIND_LMT_1 mask*/
157#define FULL_LMT (0x3fff << 0) /* RW */
158#define NTU_KA (0xff << 16) /* RW */
159
160/*PPE_BNDR mask*/
161#define BIND_RATE (0xffff << 0) /* RW */
162#define PBND_RD_PRD (0xffff << 16) /* RW */
163
164/*PPE_GLO_CFG mask*/
165#define PPE_EN (0x1 << 0) /* RW */
166#define TTL0_DRP (0x1 << 4) /* RW */
167#define MCAST_TB_EN (0x1 << 7) /* RW */
168#define MCAST_HASH (0x3 << 12) /* RW */
169
170#define MC_P3_PPSE (0xf << 12) /* RW */
171#define MC_P2_PPSE (0xf << 8) /* RW */
172#define MC_P1_PPSE (0xf << 4) /* RW */
173#define MC_P0_PPSE (0xf << 0) /* RW */
174
175#define MIB_EN (0x1 << 0) /* RW */
176#define MIB_READ_CLEAR (0X1 << 1) /* RW */
177#define MIB_CAH_EN (0X1 << 0) /* RW */
178
179/*GDMA_FWD_CFG mask */
180#define GDM_UFRC_MASK (0x7 << 12) /* RW */
181#define GDM_BFRC_MASK (0x7 << 8) /*RW*/
182#define GDM_MFRC_MASK (0x7 << 4) /*RW*/
183#define GDM_OFRC_MASK (0x7 << 0) /*RW*/
184#define GDM_ALL_FRC_MASK \
185 (GDM_UFRC_MASK | GDM_BFRC_MASK | GDM_MFRC_MASK | GDM_OFRC_MASK)
186
187/*QDMA_PAGE mask*/
188#define QTX_CFG_PAGE (0xf << 0) /* RW */
189
190/*QTX_MIB_IF mask*/
191#define MIB_ON_QTX_CFG (0x1 << 31) /* RW */
192#define VQTX_MIB_EN (0x1 << 28) /* RW */
193
194/*--------------------------------------------------------------------------*/
195/* Descriptor Structure */
196/*--------------------------------------------------------------------------*/
197#if defined(CONFIG_MEDIATEK_NETSYS_V2)
198struct hnat_unbind_info_blk {
199 u32 time_stamp : 8;
200 u32 sp : 4;
201 u32 pcnt : 8;
202 u32 ilgf : 1;
203 u32 mc : 1;
204 u32 preb : 1;
205 u32 pkt_type : 5;
206 u32 state : 2;
207 u32 udp : 1;
208 u32 sta : 1; /* static entry */
209} __packed;
210
211struct hnat_bind_info_blk {
212 u32 time_stamp : 8;
213 u32 sp : 4;
214 u32 mc : 1;
215 u32 ka : 1; /* keep alive */
216 u32 vlan_layer : 3;
217 u32 psn : 1; /* egress packet has PPPoE session */
218 u32 vpm : 1; /* 0:ethertype remark, 1:0x8100(CR default) */
219 u32 ps : 1; /* packet sampling */
220 u32 cah : 1; /* cacheable flag */
221 u32 rmt : 1; /* remove tunnel ip header (6rd/dslite only) */
222 u32 ttl : 1;
223 u32 pkt_type : 5;
224 u32 state : 2;
225 u32 udp : 1;
226 u32 sta : 1; /* static entry */
227} __packed;
228
229struct hnat_info_blk2 {
230 u32 qid : 7; /* QID in Qos Port */
231 u32 port_mg : 1;
232 u32 fqos : 1; /* force to PSE QoS port */
233 u32 dp : 4; /* force to PSE port x */
234 u32 mcast : 1; /* multicast this packet to CPU */
235 u32 pcpl : 1; /* OSBN */
236 u32 mibf : 1;
237 u32 alen : 1;
238 u32 rxid : 2;
239 u32 winfoi : 1;
240 u32 port_ag : 4;
241 u32 dscp : 8; /* DSCP value */
242} __packed;
243
244struct hnat_winfo {
245 u32 bssid : 6; /* WiFi Bssidx */
246 u32 wcid : 10; /* WiFi wtable Idx */
247} __packed;
248
249#else
250struct hnat_unbind_info_blk {
251 u32 time_stamp : 8;
252 u32 pcnt : 16; /* packet count */
253 u32 preb : 1;
254 u32 pkt_type : 3;
255 u32 state : 2;
256 u32 udp : 1;
257 u32 sta : 1; /* static entry */
258} __packed;
259
260struct hnat_bind_info_blk {
261 u32 time_stamp : 15;
262 u32 ka : 1; /* keep alive */
263 u32 vlan_layer : 3;
264 u32 psn : 1; /* egress packet has PPPoE session */
265 u32 vpm : 1; /* 0:ethertype remark, 1:0x8100(CR default) */
266 u32 ps : 1; /* packet sampling */
267 u32 cah : 1; /* cacheable flag */
268 u32 rmt : 1; /* remove tunnel ip header (6rd/dslite only) */
269 u32 ttl : 1;
270 u32 pkt_type : 3;
271 u32 state : 2;
272 u32 udp : 1;
273 u32 sta : 1; /* static entry */
274} __packed;
275
276struct hnat_info_blk2 {
277 u32 qid : 4; /* QID in Qos Port */
278 u32 fqos : 1; /* force to PSE QoS port */
279 u32 dp : 3; /* force to PSE port x
280 * 0:PSE,1:GSW, 2:GMAC,4:PPE,5:QDMA,7=DROP
281 */
282 u32 mcast : 1; /* multicast this packet to CPU */
283 u32 pcpl : 1; /* OSBN */
284 u32 mibf : 1; /* 0:off 1:on PPE MIB counter */
285 u32 alen : 1; /* 0:post 1:pre packet length in accounting */
286 u32 port_mg : 6; /* port meter group */
287 u32 port_ag : 6; /* port account group */
288 u32 dscp : 8; /* DSCP value */
289} __packed;
290
291struct hnat_winfo {
292 u32 bssid : 6; /* WiFi Bssidx */
293 u32 wcid : 8; /* WiFi wtable Idx */
294 u32 rxid : 2; /* WiFi Ring idx */
295} __packed;
296#endif
297
298/* info blk2 for WHNAT */
299struct hnat_info_blk2_whnat {
300 u32 qid : 4; /* QID[3:0] in Qos Port */
301 u32 fqos : 1; /* force to PSE QoS port */
302 u32 dp : 3; /* force to PSE port x
303 * 0:PSE,1:GSW, 2:GMAC,4:PPE,5:QDMA,7=DROP
304 */
305 u32 mcast : 1; /* multicast this packet to CPU */
306 u32 pcpl : 1; /* OSBN */
307 u32 mibf : 1; /* 0:off 1:on PPE MIB counter */
308 u32 alen : 1; /* 0:post 1:pre packet length in accounting */
309 u32 qid2 : 2; /* QID[5:4] in Qos Port */
310 u32 resv : 2;
311 u32 wdmaid : 1; /* 0:to pcie0 dev 1:to pcie1 dev */
312 u32 winfoi : 1; /* 0:off 1:on Wi-Fi hwnat support */
313 u32 port_ag : 6; /* port account group */
314 u32 dscp : 8; /* DSCP value */
315} __packed;
316
317struct hnat_ipv4_hnapt {
318 union {
319 struct hnat_bind_info_blk bfib1;
320 struct hnat_unbind_info_blk udib1;
321 u32 info_blk1;
322 };
323 u32 sip;
324 u32 dip;
325 u16 dport;
326 u16 sport;
327 union {
328 struct hnat_info_blk2 iblk2;
329 struct hnat_info_blk2_whnat iblk2w;
330 u32 info_blk2;
331 };
332 u32 new_sip;
333 u32 new_dip;
334 u16 new_dport;
335 u16 new_sport;
336 u16 m_timestamp; /* For mcast*/
337 u16 resv1;
338 u32 resv2;
339 u32 resv3 : 26;
340 u32 act_dp : 6; /* UDF */
341 u16 vlan1;
342 u16 etype;
343 u32 dmac_hi;
344 union {
345#if !defined(CONFIG_MEDIATEK_NETSYS_V2)
346 struct hnat_winfo winfo;
347#endif
348 u16 vlan2;
349 };
350 u16 dmac_lo;
351 u32 smac_hi;
352 u16 pppoe_id;
353 u16 smac_lo;
354#if defined(CONFIG_MEDIATEK_NETSYS_V2)
355 u16 minfo;
356 struct hnat_winfo winfo;
357#endif
358} __packed;
359
360struct hnat_ipv4_dslite {
361 union {
362 struct hnat_bind_info_blk bfib1;
363 struct hnat_unbind_info_blk udib1;
364 u32 info_blk1;
365 };
366 u32 sip;
367 u32 dip;
368 u16 dport;
369 u16 sport;
370
371 u32 tunnel_sipv6_0;
372 u32 tunnel_sipv6_1;
373 u32 tunnel_sipv6_2;
374 u32 tunnel_sipv6_3;
375
376 u32 tunnel_dipv6_0;
377 u32 tunnel_dipv6_1;
378 u32 tunnel_dipv6_2;
379 u32 tunnel_dipv6_3;
380
381 u8 flow_lbl[3]; /* in order to consist with Linux kernel (should be 20bits) */
382 u8 priority; /* in order to consist with Linux kernel (should be 8bits) */
383 u32 hop_limit : 8;
384 u32 resv2 : 18;
385 u32 act_dp : 6; /* UDF */
386
387 union {
388 struct hnat_info_blk2 iblk2;
389 struct hnat_info_blk2_whnat iblk2w;
390 u32 info_blk2;
391 };
392
393 u16 vlan1;
394 u16 etype;
395 u32 dmac_hi;
396 union {
397#if !defined(CONFIG_MEDIATEK_NETSYS_V2)
398 struct hnat_winfo winfo;
399#endif
400 u16 vlan2;
401 };
402 u16 dmac_lo;
403 u32 smac_hi;
404 u16 pppoe_id;
405 u16 smac_lo;
406#if defined(CONFIG_MEDIATEK_NETSYS_V2)
407 u16 minfo;
408 struct hnat_winfo winfo;
409 u32 new_sip;
410 u32 new_dip;
411 u16 new_dport;
412 u16 new_sport;
413#endif
414} __packed;
415
416struct hnat_ipv6_3t_route {
417 union {
418 struct hnat_bind_info_blk bfib1;
419 struct hnat_unbind_info_blk udib1;
420 u32 info_blk1;
421 };
422 u32 ipv6_sip0;
423 u32 ipv6_sip1;
424 u32 ipv6_sip2;
425 u32 ipv6_sip3;
426 u32 ipv6_dip0;
427 u32 ipv6_dip1;
428 u32 ipv6_dip2;
429 u32 ipv6_dip3;
430 u32 prot : 8;
developer729f0272021-06-09 17:28:38 +0800431 u32 hph : 24; /* hash placeholder */
developerfd40db22021-04-29 10:08:25 +0800432
433 u32 resv1;
434 u32 resv2;
435 u32 resv3;
436 u32 resv4 : 26;
437 u32 act_dp : 6; /* UDF */
438
439 union {
440 struct hnat_info_blk2 iblk2;
441 struct hnat_info_blk2_whnat iblk2w;
442 u32 info_blk2;
443 };
444 u16 vlan1;
445 u16 etype;
446 u32 dmac_hi;
447 union {
448#if !defined(CONFIG_MEDIATEK_NETSYS_V2)
449 struct hnat_winfo winfo;
450#endif
451 u16 vlan2;
452 };
453 u16 dmac_lo;
454 u32 smac_hi;
455 u16 pppoe_id;
456 u16 smac_lo;
457#if defined(CONFIG_MEDIATEK_NETSYS_V2)
458 u16 minfo;
459 struct hnat_winfo winfo;
460#endif
461} __packed;
462
463struct hnat_ipv6_5t_route {
464 union {
465 struct hnat_bind_info_blk bfib1;
466 struct hnat_unbind_info_blk udib1;
467 u32 info_blk1;
468 };
469 u32 ipv6_sip0;
470 u32 ipv6_sip1;
471 u32 ipv6_sip2;
472 u32 ipv6_sip3;
473 u32 ipv6_dip0;
474 u32 ipv6_dip1;
475 u32 ipv6_dip2;
476 u32 ipv6_dip3;
477 u16 dport;
478 u16 sport;
479
480 u32 resv1;
481 u32 resv2;
482 u32 resv3;
483 u32 resv4 : 26;
484 u32 act_dp : 6; /* UDF */
485
486 union {
487 struct hnat_info_blk2 iblk2;
488 struct hnat_info_blk2_whnat iblk2w;
489 u32 info_blk2;
490 };
491
492 u16 vlan1;
493 u16 etype;
494 u32 dmac_hi;
495 union {
496#if !defined(CONFIG_MEDIATEK_NETSYS_V2)
497 struct hnat_winfo winfo;
498#endif
499 u16 vlan2;
500 };
501 u16 dmac_lo;
502 u32 smac_hi;
503 u16 pppoe_id;
504 u16 smac_lo;
505#if defined(CONFIG_MEDIATEK_NETSYS_V2)
506 u16 minfo;
507 struct hnat_winfo winfo;
508#endif
509} __packed;
510
511struct hnat_ipv6_6rd {
512 union {
513 struct hnat_bind_info_blk bfib1;
514 struct hnat_unbind_info_blk udib1;
515 u32 info_blk1;
516 };
517 u32 ipv6_sip0;
518 u32 ipv6_sip1;
519 u32 ipv6_sip2;
520 u32 ipv6_sip3;
521 u32 ipv6_dip0;
522 u32 ipv6_dip1;
523 u32 ipv6_dip2;
524 u32 ipv6_dip3;
525 u16 dport;
526 u16 sport;
527
528 u32 tunnel_sipv4;
529 u32 tunnel_dipv4;
530 u32 hdr_chksum : 16;
531 u32 dscp : 8;
532 u32 ttl : 8;
533 u32 flag : 3;
534 u32 resv1 : 13;
535 u32 per_flow_6rd_id : 1;
536 u32 resv2 : 9;
537 u32 act_dp : 6; /* UDF */
538
539 union {
540 struct hnat_info_blk2 iblk2;
541 struct hnat_info_blk2_whnat iblk2w;
542 u32 info_blk2;
543 };
544
545 u16 vlan1;
546 u16 etype;
547 u32 dmac_hi;
548 union {
549#if !defined(CONFIG_MEDIATEK_NETSYS_V2)
550 struct hnat_winfo winfo;
551#endif
552 u16 vlan2;
553 };
554 u16 dmac_lo;
555 u32 smac_hi;
556 u16 pppoe_id;
557 u16 smac_lo;
558#if defined(CONFIG_MEDIATEK_NETSYS_V2)
559 u16 minfo;
560 struct hnat_winfo winfo;
561 u32 resv3;
562 u32 resv4;
563 u16 new_dport;
564 u16 new_sport;
565#endif
566} __packed;
567
568struct foe_entry {
569 union {
570 struct hnat_unbind_info_blk udib1;
571 struct hnat_bind_info_blk bfib1;
572 struct hnat_ipv4_hnapt ipv4_hnapt;
573 struct hnat_ipv4_dslite ipv4_dslite;
574 struct hnat_ipv6_3t_route ipv6_3t_route;
575 struct hnat_ipv6_5t_route ipv6_5t_route;
576 struct hnat_ipv6_6rd ipv6_6rd;
577 };
578};
579
580/* If user wants to change default FOE entry number, both DEF_ETRY_NUM and
581 * DEF_ETRY_NUM_CFG need to be modified.
582 */
583#define DEF_ETRY_NUM 8192
developerbc53e5f2021-05-21 10:07:17 +0800584/* feasible values : 32768, 16384, 8192, 4096, 2048, 1024 */
developerfd40db22021-04-29 10:08:25 +0800585#define DEF_ETRY_NUM_CFG TABLE_8K
developerbc53e5f2021-05-21 10:07:17 +0800586/* corresponding values : TABLE_32K, TABLE_16K, TABLE_8K, TABLE_4K, TABLE_2K,
587 * TABLE_1K
588 */
developerfd40db22021-04-29 10:08:25 +0800589#define MAX_EXT_DEVS (0x3fU)
590#define MAX_IF_NUM 64
591
developer471f6562021-05-10 20:48:34 +0800592#if defined(CONFIG_MEDIATEK_NETSYS_V2)
593#define MAX_PPE_NUM 2
594#else
595#define MAX_PPE_NUM 1
596#endif
597#define CFG_PPE_NUM (hnat_priv->ppe_num)
598
developerfd40db22021-04-29 10:08:25 +0800599struct mib_entry {
600 u32 byt_cnt_l;
601 u16 byt_cnt_h;
602 u32 pkt_cnt_l;
603 u8 pkt_cnt_h;
604 u8 resv0;
605 u32 resv1;
606} __packed;
607
608struct hnat_accounting {
609 u64 bytes;
610 u64 packets;
611};
612
613enum mtk_hnat_version {
614 MTK_HNAT_V1 = 1, /* version 1: mt7621, mt7623 */
615 MTK_HNAT_V2, /* version 2: mt7622 */
616 MTK_HNAT_V3, /* version 3: mt7629 */
617 MTK_HNAT_V4, /* version 4: mt7986 */
618};
619
620struct mtk_hnat_data {
621 u8 num_of_sch;
622 bool whnat;
623 bool per_flow_accounting;
624 bool mcast;
625 enum mtk_hnat_version version;
626};
627
628struct mtk_hnat {
629 struct device *dev;
630 void __iomem *fe_base;
developer471f6562021-05-10 20:48:34 +0800631 void __iomem *ppe_base[MAX_PPE_NUM];
632 struct foe_entry *foe_table_cpu[MAX_PPE_NUM];
633 dma_addr_t foe_table_dev[MAX_PPE_NUM];
developerfd40db22021-04-29 10:08:25 +0800634 u8 enable;
635 u8 enable1;
636 struct dentry *root;
developer471f6562021-05-10 20:48:34 +0800637 struct debugfs_regset32 *regset[MAX_PPE_NUM];
developerfd40db22021-04-29 10:08:25 +0800638
developer471f6562021-05-10 20:48:34 +0800639 struct mib_entry *foe_mib_cpu[MAX_PPE_NUM];
640 dma_addr_t foe_mib_dev[MAX_PPE_NUM];
641 struct hnat_accounting *acct[MAX_PPE_NUM];
developerfd40db22021-04-29 10:08:25 +0800642 const struct mtk_hnat_data *data;
643
644 /*devices we plays for*/
645 char wan[IFNAMSIZ];
646 char lan[IFNAMSIZ];
647 char ppd[IFNAMSIZ];
648 u16 lvid;
649 u16 wvid;
650
651 struct reset_control *rstc;
652
developer471f6562021-05-10 20:48:34 +0800653 u8 ppe_num;
developerfd40db22021-04-29 10:08:25 +0800654 u8 gmac_num;
655 u8 wan_dsa_port;
656 struct ppe_mcast_table *pmcast;
657
658 u32 foe_etry_num;
659 struct net_device *g_ppdev;
developer8c9c0d02021-06-18 16:15:37 +0800660 struct net_device *g_wandev;
developerfd40db22021-04-29 10:08:25 +0800661 struct net_device *wifi_hook_if[MAX_IF_NUM];
662 struct extdev_entry *ext_if[MAX_EXT_DEVS];
663 struct timer_list hnat_sma_build_entry_timer;
664 struct timer_list hnat_reset_timestamp_timer;
665 struct timer_list hnat_mcast_check_timer;
developer30a47682021-11-02 17:06:14 +0800666 bool nf_stat_en;
developerfd40db22021-04-29 10:08:25 +0800667};
668
669struct extdev_entry {
670 char name[IFNAMSIZ];
671 struct net_device *dev;
672};
673
674struct tcpudphdr {
675 __be16 src;
676 __be16 dst;
677};
678
679enum FoeEntryState { INVALID = 0, UNBIND = 1, BIND = 2, FIN = 3 };
680
681enum FoeIpAct {
682 IPV4_HNAPT = 0,
683 IPV4_HNAT = 1,
684 IPV4_DSLITE = 3,
685 IPV6_3T_ROUTE = 4,
686 IPV6_5T_ROUTE = 5,
687 IPV6_6RD = 7,
688#if defined(CONFIG_MEDIATEK_NETSYS_V2)
689 IPV4_MAP_T = 8,
690 IPV4_MAP_E = 9,
691#else
692 IPV4_MAP_T = 6,
693 IPV4_MAP_E = 6,
694#endif
695};
696
697/*--------------------------------------------------------------------------*/
698/* Common Definition*/
699/*--------------------------------------------------------------------------*/
700
701#define HNAT_SW_VER "1.1.0"
702#define HASH_SEED_KEY 0x12345678
703
704/*PPE_TB_CFG value*/
705#define ENTRY_80B 1
706#define ENTRY_64B 0
707#define TABLE_1K 0
708#define TABLE_2K 1
709#define TABLE_4K 2
710#define TABLE_8K 3
711#define TABLE_16K 4
developerbc53e5f2021-05-21 10:07:17 +0800712#define TABLE_32K 5
developerfd40db22021-04-29 10:08:25 +0800713#define SMA_DROP 0 /* Drop the packet */
714#define SMA_DROP2 1 /* Drop the packet */
715#define SMA_ONLY_FWD_CPU 2 /* Only Forward to CPU */
716#define SMA_FWD_CPU_BUILD_ENTRY 3 /* Forward to CPU and build new FOE entry */
717#define HASH_MODE_0 0
718#define HASH_MODE_1 1
719#define HASH_MODE_2 2
720#define HASH_MODE_3 3
721
722/*PPE_FLOW_CFG*/
723#define BIT_FUC_FOE BIT(2)
724#define BIT_FMC_FOE BIT(1)
725#define BIT_FBC_FOE BIT(0)
726#define BIT_UDP_IP4F_NAT_EN BIT(7) /*Enable IPv4 fragment + UDP packet NAT*/
727#define BIT_IPV6_3T_ROUTE_EN BIT(8)
728#define BIT_IPV6_5T_ROUTE_EN BIT(9)
729#define BIT_IPV6_6RD_EN BIT(10)
730#define BIT_IPV4_NAT_EN BIT(12)
731#define BIT_IPV4_NAPT_EN BIT(13)
732#define BIT_IPV4_DSL_EN BIT(14)
733#define BIT_MIB_BUSY BIT(16)
734#define BIT_IPV4_NAT_FRAG_EN BIT(17)
735#define BIT_IPV4_HASH_GREK BIT(19)
736#define BIT_IPV6_HASH_GREK BIT(20)
737#define BIT_IPV4_MAPE_EN BIT(21)
738#define BIT_IPV4_MAPT_EN BIT(22)
739
740/*GDMA_FWD_CFG value*/
developer471f6562021-05-10 20:48:34 +0800741#define BITS_GDM_UFRC_P_PPE (NR_PPE0_PORT << 12)
742#define BITS_GDM_BFRC_P_PPE (NR_PPE0_PORT << 8)
743#define BITS_GDM_MFRC_P_PPE (NR_PPE0_PORT << 4)
744#define BITS_GDM_OFRC_P_PPE (NR_PPE0_PORT << 0)
developerfd40db22021-04-29 10:08:25 +0800745#define BITS_GDM_ALL_FRC_P_PPE \
746 (BITS_GDM_UFRC_P_PPE | BITS_GDM_BFRC_P_PPE | BITS_GDM_MFRC_P_PPE | \
747 BITS_GDM_OFRC_P_PPE)
748
749#define BITS_GDM_UFRC_P_CPU_PDMA (NR_PDMA_PORT << 12)
750#define BITS_GDM_BFRC_P_CPU_PDMA (NR_PDMA_PORT << 8)
751#define BITS_GDM_MFRC_P_CPU_PDMA (NR_PDMA_PORT << 4)
752#define BITS_GDM_OFRC_P_CPU_PDMA (NR_PDMA_PORT << 0)
753#define BITS_GDM_ALL_FRC_P_CPU_PDMA \
754 (BITS_GDM_UFRC_P_CPU_PDMA | BITS_GDM_BFRC_P_CPU_PDMA | \
755 BITS_GDM_MFRC_P_CPU_PDMA | BITS_GDM_OFRC_P_CPU_PDMA)
756
757#define BITS_GDM_UFRC_P_CPU_QDMA (NR_QDMA_PORT << 12)
758#define BITS_GDM_BFRC_P_CPU_QDMA (NR_QDMA_PORT << 8)
759#define BITS_GDM_MFRC_P_CPU_QDMA (NR_QDMA_PORT << 4)
760#define BITS_GDM_OFRC_P_CPU_QDMA (NR_QDMA_PORT << 0)
761#define BITS_GDM_ALL_FRC_P_CPU_QDMA \
762 (BITS_GDM_UFRC_P_CPU_QDMA | BITS_GDM_BFRC_P_CPU_QDMA | \
763 BITS_GDM_MFRC_P_CPU_QDMA | BITS_GDM_OFRC_P_CPU_QDMA)
764
765#define BITS_GDM_UFRC_P_DISCARD (NR_DISCARD << 12)
766#define BITS_GDM_BFRC_P_DISCARD (NR_DISCARD << 8)
767#define BITS_GDM_MFRC_P_DISCARD (NR_DISCARD << 4)
768#define BITS_GDM_OFRC_P_DISCARD (NR_DISCARD << 0)
769#define BITS_GDM_ALL_FRC_P_DISCARD \
770 (BITS_GDM_UFRC_P_DISCARD | BITS_GDM_BFRC_P_DISCARD | \
771 BITS_GDM_MFRC_P_DISCARD | BITS_GDM_OFRC_P_DISCARD)
772
773#define hnat_is_enabled(hnat_priv) (hnat_priv->enable)
774#define hnat_enabled(hnat_priv) (hnat_priv->enable = 1)
775#define hnat_disabled(hnat_priv) (hnat_priv->enable = 0)
776#define hnat_is_enabled1(hnat_priv) (hnat_priv->enable1)
777#define hnat_enabled1(hnat_priv) (hnat_priv->enable1 = 1)
778#define hnat_disabled1(hnat_priv) (hnat_priv->enable1 = 0)
779
780#define entry_hnat_is_bound(e) (e->bfib1.state == BIND)
781#define entry_hnat_state(e) (e->bfib1.state)
782
783#define skb_hnat_is_hashed(skb) \
784 (skb_hnat_entry(skb) != 0x3fff && skb_hnat_entry(skb) < hnat_priv->foe_etry_num)
785#define FROM_GE_LAN(skb) (skb_hnat_iface(skb) == FOE_MAGIC_GE_LAN)
786#define FROM_GE_WAN(skb) (skb_hnat_iface(skb) == FOE_MAGIC_GE_WAN)
787#define FROM_GE_PPD(skb) (skb_hnat_iface(skb) == FOE_MAGIC_GE_PPD)
788#define FROM_GE_VIRTUAL(skb) (skb_hnat_iface(skb) == FOE_MAGIC_GE_VIRTUAL)
789#define FROM_EXT(skb) (skb_hnat_iface(skb) == FOE_MAGIC_EXT)
developere567ad32021-05-25 17:16:17 +0800790#define FROM_WED(skb) ((skb_hnat_iface(skb) == FOE_MAGIC_WED0) || \
791 (skb_hnat_iface(skb) == FOE_MAGIC_WED1))
developerfd40db22021-04-29 10:08:25 +0800792#define FOE_MAGIC_GE_LAN 0x1
793#define FOE_MAGIC_GE_WAN 0x2
794#define FOE_MAGIC_EXT 0x3
795#define FOE_MAGIC_GE_VIRTUAL 0x4
796#define FOE_MAGIC_GE_PPD 0x5
developere567ad32021-05-25 17:16:17 +0800797#define FOE_MAGIC_WED0 0x78
798#define FOE_MAGIC_WED1 0x79
developerfd40db22021-04-29 10:08:25 +0800799#define FOE_INVALID 0xf
800#define index6b(i) (0x3fU - i)
801
802#define IPV4_HNAPT 0
803#define IPV4_HNAT 1
804#define IP_FORMAT(addr) \
805 (((unsigned char *)&addr)[3], ((unsigned char *)&addr)[2], \
806 ((unsigned char *)&addr)[1], ((unsigned char *)&addr)[0])
807
808/*PSE Ports*/
809#define NR_PDMA_PORT 0
810#define NR_GMAC1_PORT 1
811#define NR_GMAC2_PORT 2
developer471f6562021-05-10 20:48:34 +0800812#if defined(CONFIG_MEDIATEK_NETSYS_V2)
813#define NR_WHNAT_WDMA_PORT EINVAL
814#define NR_PPE0_PORT 3
815#define NR_PPE1_PORT 4
816#else
developerfd40db22021-04-29 10:08:25 +0800817#define NR_WHNAT_WDMA_PORT 3
developer471f6562021-05-10 20:48:34 +0800818#define NR_PPE0_PORT 4
819#endif
developerfd40db22021-04-29 10:08:25 +0800820#define NR_QDMA_PORT 5
821#define NR_DISCARD 7
822#define NR_WDMA0_PORT 8
823#define NR_WDMA1_PORT 9
824#define LAN_DEV_NAME hnat_priv->lan
825#define IS_WAN(dev) \
826 (!strncmp((dev)->name, hnat_priv->wan, strlen(hnat_priv->wan)))
827#define IS_LAN(dev) (!strncmp(dev->name, LAN_DEV_NAME, strlen(LAN_DEV_NAME)))
828#define IS_BR(dev) (!strncmp(dev->name, "br", 2))
829#define IS_WHNAT(dev) \
830 ((hnat_priv->data->whnat && \
831 (get_wifi_hook_if_index_from_dev(dev) != 0)) ? 1 : 0)
832#define IS_EXT(dev) ((get_index_from_dev(dev) != 0) ? 1 : 0)
833#define IS_PPD(dev) (!strcmp(dev->name, hnat_priv->ppd))
834#define IS_IPV4_HNAPT(x) (((x)->bfib1.pkt_type == IPV4_HNAPT) ? 1 : 0)
835#define IS_IPV4_HNAT(x) (((x)->bfib1.pkt_type == IPV4_HNAT) ? 1 : 0)
836#define IS_IPV4_GRP(x) (IS_IPV4_HNAPT(x) | IS_IPV4_HNAT(x))
837#define IS_IPV4_DSLITE(x) (((x)->bfib1.pkt_type == IPV4_DSLITE) ? 1 : 0)
838#define IS_IPV4_MAPE(x) (((x)->bfib1.pkt_type == IPV4_MAP_E) ? 1 : 0)
839#define IS_IPV4_MAPT(x) (((x)->bfib1.pkt_type == IPV4_MAP_T) ? 1 : 0)
840#define IS_IPV6_3T_ROUTE(x) (((x)->bfib1.pkt_type == IPV6_3T_ROUTE) ? 1 : 0)
841#define IS_IPV6_5T_ROUTE(x) (((x)->bfib1.pkt_type == IPV6_5T_ROUTE) ? 1 : 0)
842#define IS_IPV6_6RD(x) (((x)->bfib1.pkt_type == IPV6_6RD) ? 1 : 0)
843#define IS_IPV6_GRP(x) \
844 (IS_IPV6_3T_ROUTE(x) | IS_IPV6_5T_ROUTE(x) | IS_IPV6_6RD(x) | \
845 IS_IPV4_DSLITE(x) | IS_IPV4_MAPE(x) | IS_IPV4_MAPT(x))
846#define IS_BOND_MODE (!strncmp(LAN_DEV_NAME, "bond", 4))
847#define IS_GMAC1_MODE ((hnat_priv->gmac_num == 1) ? 1 : 0)
developeraf07fad2021-11-19 17:53:42 +0800848#define IS_HQOS_MODE (qos_toggle == 1)
849#define IS_PPPQ_MODE (qos_toggle == 2) /* Per Port Per Queue */
developerfd40db22021-04-29 10:08:25 +0800850
851#define es(entry) (entry_state[entry->bfib1.state])
852#define ei(entry, end) (hnat_priv->foe_etry_num - (int)(end - entry))
853#define pt(entry) (packet_type[entry->ipv4_hnapt.bfib1.pkt_type])
854#define ipv4_smac(mac, e) \
855 ({ \
856 mac[0] = e->ipv4_hnapt.smac_hi[3]; \
857 mac[1] = e->ipv4_hnapt.smac_hi[2]; \
858 mac[2] = e->ipv4_hnapt.smac_hi[1]; \
859 mac[3] = e->ipv4_hnapt.smac_hi[0]; \
860 mac[4] = e->ipv4_hnapt.smac_lo[1]; \
861 mac[5] = e->ipv4_hnapt.smac_lo[0]; \
862 })
863#define ipv4_dmac(mac, e) \
864 ({ \
865 mac[0] = e->ipv4_hnapt.dmac_hi[3]; \
866 mac[1] = e->ipv4_hnapt.dmac_hi[2]; \
867 mac[2] = e->ipv4_hnapt.dmac_hi[1]; \
868 mac[3] = e->ipv4_hnapt.dmac_hi[0]; \
869 mac[4] = e->ipv4_hnapt.dmac_lo[1]; \
870 mac[5] = e->ipv4_hnapt.dmac_lo[0]; \
871 })
872
873#define IS_DSA_LAN(dev) (!strncmp(dev->name, "lan", 3))
874#define IS_DSA_WAN(dev) (!strncmp(dev->name, "wan", 3))
875#define NONE_DSA_PORT 0xff
876#define MAX_CRSN_NUM 32
877#define IPV6_HDR_LEN 40
878
879/*QDMA_PAGE value*/
880#define NUM_OF_Q_PER_PAGE 16
881
882/*IPv6 Header*/
883#ifndef NEXTHDR_IPIP
884#define NEXTHDR_IPIP 4
885#endif
886
887extern const struct of_device_id of_hnat_match[];
888extern struct mtk_hnat *hnat_priv;
889
890#if defined(CONFIG_NET_DSA_MT7530)
developeraf07fad2021-11-19 17:53:42 +0800891u32 hnat_dsa_fill_stag(const struct net_device *netdev,
892 struct foe_entry *entry,
893 struct flow_offload_hw_path *hw_path,
894 u16 eth_proto, int mape);
developerfd40db22021-04-29 10:08:25 +0800895
896static inline bool hnat_dsa_is_enable(struct mtk_hnat *priv)
897{
898 return (priv->wan_dsa_port != NONE_DSA_PORT);
899}
900#else
developeraf07fad2021-11-19 17:53:42 +0800901static inline u32 hnat_dsa_fill_stag(const struct net_device *netdev,
902 struct foe_entry *entry,
903 struct flow_offload_hw_path *hw_path,
904 u16 eth_proto, int mape)
developerfd40db22021-04-29 10:08:25 +0800905{
906}
907
908static inline bool hnat_dsa_is_enable(struct mtk_hnat *priv)
909{
910 return false;
911}
912#endif
913
914void hnat_deinit_debugfs(struct mtk_hnat *h);
915int hnat_init_debugfs(struct mtk_hnat *h);
916int hnat_register_nf_hooks(void);
917void hnat_unregister_nf_hooks(void);
918int whnat_adjust_nf_hooks(void);
919int mtk_hqos_ptype_cb(struct sk_buff *skb, struct net_device *dev,
920 struct packet_type *pt, struct net_device *unused);
921extern int dbg_cpu_reason;
922extern int debug_level;
923extern int hook_toggle;
924extern int mape_toggle;
developeraf07fad2021-11-19 17:53:42 +0800925extern int qos_toggle;
developerfd40db22021-04-29 10:08:25 +0800926
927int ext_if_add(struct extdev_entry *ext_entry);
928int ext_if_del(struct extdev_entry *ext_entry);
929void cr_set_field(void __iomem *reg, u32 field, u32 val);
930int mtk_sw_nat_hook_tx(struct sk_buff *skb, int gmac_no);
931int mtk_sw_nat_hook_rx(struct sk_buff *skb);
932void mtk_ppe_dev_register_hook(struct net_device *dev);
933void mtk_ppe_dev_unregister_hook(struct net_device *dev);
934int nf_hnat_netdevice_event(struct notifier_block *unused, unsigned long event,
935 void *ptr);
936int nf_hnat_netevent_handler(struct notifier_block *unused, unsigned long event,
937 void *ptr);
938uint32_t foe_dump_pkt(struct sk_buff *skb);
939uint32_t hnat_cpu_reason_cnt(struct sk_buff *skb);
940int hnat_enable_hook(void);
941int hnat_disable_hook(void);
942void hnat_cache_ebl(int enable);
943void set_gmac_ppe_fwd(int gmac_no, int enable);
developer471f6562021-05-10 20:48:34 +0800944int entry_detail(int ppe_id, int index);
developer731b98f2021-09-17 17:44:37 +0800945int entry_delete_by_mac(u8 *mac);
developer471f6562021-05-10 20:48:34 +0800946int entry_delete(int ppe_id, int index);
developer30a47682021-11-02 17:06:14 +0800947struct hnat_accounting *hnat_get_count(struct mtk_hnat *h, int ppe_id,
948 u32 index, struct hnat_accounting *diff);
developerfd40db22021-04-29 10:08:25 +0800949
950static inline u16 foe_timestamp(struct mtk_hnat *h)
951{
952 return (readl(hnat_priv->fe_base + 0x0010)) & 0xffff;
953}