blob: f2d5dc847b633094ae9da69d6b4aa7022e6de036 [file] [log] [blame]
developerfd40db22021-04-29 10:08:25 +08001/* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
4 *
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
9 *
10 * Copyright (C) 2014-2016 Sean Wang <sean.wang@mediatek.com>
11 * Copyright (C) 2016-2017 John Crispin <blogic@openwrt.org>
12 */
13
14#include <linux/debugfs.h>
15#include <linux/string.h>
16#include <linux/if.h>
17#include <linux/if_ether.h>
18#include <net/netevent.h>
19#include <linux/mod_devicetable.h>
20#include "hnat_mcast.h"
21
22/*--------------------------------------------------------------------------*/
23/* Register Offset*/
24/*--------------------------------------------------------------------------*/
25#define PPE_GLO_CFG 0x00
26#define PPE_FLOW_CFG 0x04
27#define PPE_IP_PROT_CHK 0x08
28#define PPE_IP_PROT_0 0x0C
29#define PPE_IP_PROT_1 0x10
30#define PPE_IP_PROT_2 0x14
31#define PPE_IP_PROT_3 0x18
32#define PPE_TB_CFG 0x1C
33#define PPE_TB_BASE 0x20
34#define PPE_TB_USED 0x24
35#define PPE_BNDR 0x28
36#define PPE_BIND_LMT_0 0x2C
37#define PPE_BIND_LMT_1 0x30
38#define PPE_KA 0x34
39#define PPE_UNB_AGE 0x38
40#define PPE_BND_AGE_0 0x3C
41#define PPE_BND_AGE_1 0x40
42#define PPE_HASH_SEED 0x44
43#define PPE_DFT_CPORT 0x48
44#define PPE_DFT_CPORT1 0x4C
45#define PPE_MCAST_PPSE 0x84
46#define PPE_MCAST_L_0 0x88
47#define PPE_MCAST_H_0 0x8C
48#define PPE_MCAST_L_1 0x90
49#define PPE_MCAST_H_1 0x94
50#define PPE_MCAST_L_2 0x98
51#define PPE_MCAST_H_2 0x9C
52#define PPE_MCAST_L_3 0xA0
53#define PPE_MCAST_H_3 0xA4
54#define PPE_MCAST_L_4 0xA8
55#define PPE_MCAST_H_4 0xAC
56#define PPE_MCAST_L_5 0xB0
57#define PPE_MCAST_H_5 0xB4
58#define PPE_MCAST_L_6 0xBC
59#define PPE_MCAST_H_6 0xC0
60#define PPE_MCAST_L_7 0xC4
61#define PPE_MCAST_H_7 0xC8
62#define PPE_MCAST_L_8 0xCC
63#define PPE_MCAST_H_8 0xD0
64#define PPE_MCAST_L_9 0xD4
65#define PPE_MCAST_H_9 0xD8
66#define PPE_MCAST_L_A 0xDC
67#define PPE_MCAST_H_A 0xE0
68#define PPE_MCAST_L_B 0xE4
69#define PPE_MCAST_H_B 0xE8
70#define PPE_MCAST_L_C 0xEC
71#define PPE_MCAST_H_C 0xF0
72#define PPE_MCAST_L_D 0xF4
73#define PPE_MCAST_H_D 0xF8
74#define PPE_MCAST_L_E 0xFC
75#define PPE_MCAST_H_E 0xE0
76#define PPE_MCAST_L_F 0x100
77#define PPE_MCAST_H_F 0x104
78#define PPE_MCAST_L_10 0xC00
79#define PPE_MCAST_H_10 0xC04
80#define PPE_MTU_DRP 0x108
81#define PPE_MTU_VLYR_0 0x10C
82#define PPE_MTU_VLYR_1 0x110
83#define PPE_MTU_VLYR_2 0x114
84#define PPE_VPM_TPID 0x118
85#define PPE_CAH_CTRL 0x120
86#define PPE_CAH_TAG_SRH 0x124
87#define PPE_CAH_LINE_RW 0x128
88#define PPE_CAH_WDATA 0x12C
89#define PPE_CAH_RDATA 0x130
90
91#define PPE_MIB_CFG 0X134
92#define PPE_MIB_TB_BASE 0X138
93#define PPE_MIB_SER_CR 0X13C
94#define PPE_MIB_SER_R0 0X140
95#define PPE_MIB_SER_R1 0X144
96#define PPE_MIB_SER_R2 0X148
developerd35bbcc2022-09-28 22:46:01 +080097#define PPE_MIB_SER_R3 0X14C
developerfd40db22021-04-29 10:08:25 +080098#define PPE_MIB_CAH_CTRL 0X150
99#define PPE_MIB_CAH_TAG_SRH 0X154
100#define PPE_MIB_CAH_LINE_RW 0X158
101#define PPE_MIB_CAH_WDATA 0X15C
102#define PPE_MIB_CAH_RDATA 0X160
developerd35bbcc2022-09-28 22:46:01 +0800103#define PPE_SB_FIFO_DBG 0x170
developerfd40db22021-04-29 10:08:25 +0800104#define PPE_SBW_CTRL 0x174
105
106#define GDMA1_FWD_CFG 0x500
107#define GDMA2_FWD_CFG 0x1500
developerd35bbcc2022-09-28 22:46:01 +0800108#define GDMA3_FWD_CFG 0x540
developerfd40db22021-04-29 10:08:25 +0800109
developer24948202021-11-24 17:38:27 +0800110/* QDMA Tx queue configuration */
developer70cdf6e2021-12-07 18:58:35 +0800111#define QTX_CFG(x) (QDMA_BASE + ((x) * 0x10))
112#define QTX_CFG_HW_RESV_CNT_OFFSET (8)
113#define QTX_CFG_SW_RESV_CNT_OFFSET (0)
114
115#define QTX_SCH(x) (QDMA_BASE + 0x4 + ((x) * 0x10))
116#define QTX_SCH_MIN_RATE_EN BIT(27)
117#define QTX_SCH_MAX_RATE_EN BIT(11)
118#define QTX_SCH_MIN_RATE_MAN_OFFSET (20)
119#define QTX_SCH_MIN_RATE_EXP_OFFSET (16)
120#define QTX_SCH_MAX_RATE_WGHT_OFFSET (12)
121#define QTX_SCH_MAX_RATE_MAN_OFFSET (4)
122#define QTX_SCH_MAX_RATE_EXP_OFFSET (0)
developer24948202021-11-24 17:38:27 +0800123
124/* QDMA Tx scheduler configuration */
developer70cdf6e2021-12-07 18:58:35 +0800125#define QDMA_PAGE (QDMA_BASE + 0x1f0)
126#define QDMA_TX_2SCH_BASE (QDMA_BASE + 0x214)
127#define QTX_MIB_IF (QDMA_BASE + 0x2bc)
128#define QDMA_TX_4SCH_BASE(x) (QDMA_BASE + 0x398 + (((x) >> 1) * 0x4))
developer34028fb2022-01-11 13:51:29 +0800129#define QDMA_TX_SCH_WFQ_EN BIT(15)
developerfd40db22021-04-29 10:08:25 +0800130
131/*--------------------------------------------------------------------------*/
132/* Register Mask*/
133/*--------------------------------------------------------------------------*/
134/* PPE_TB_CFG mask */
135#define TB_ETRY_NUM (0x7 << 0) /* RW */
136#define TB_ENTRY_SIZE (0x1 << 3) /* RW */
137#define SMA (0x3 << 4) /* RW */
138#define NTU_AGE (0x1 << 7) /* RW */
139#define UNBD_AGE (0x1 << 8) /* RW */
140#define TCP_AGE (0x1 << 9) /* RW */
141#define UDP_AGE (0x1 << 10) /* RW */
142#define FIN_AGE (0x1 << 11) /* RW */
143#define KA_CFG (0x3 << 12)
144#define HASH_MODE (0x3 << 14) /* RW */
145#define SCAN_MODE (0x3 << 16) /* RW */
146#define XMODE (0x3 << 18) /* RW */
developer8051e042022-04-08 13:26:36 +0800147#define TICK_SEL (0x1 << 24) /* RW */
148
developerfd40db22021-04-29 10:08:25 +0800149
150/*PPE_CAH_CTRL mask*/
151#define CAH_EN (0x1 << 0) /* RW */
152#define CAH_X_MODE (0x1 << 9) /* RW */
153
154/*PPE_UNB_AGE mask*/
155#define UNB_DLTA (0xff << 0) /* RW */
156#define UNB_MNP (0xffff << 16) /* RW */
157
158/*PPE_BND_AGE_0 mask*/
159#define UDP_DLTA (0xffff << 0) /* RW */
160#define NTU_DLTA (0xffff << 16) /* RW */
161
162/*PPE_BND_AGE_1 mask*/
163#define TCP_DLTA (0xffff << 0) /* RW */
164#define FIN_DLTA (0xffff << 16) /* RW */
165
166/*PPE_KA mask*/
167#define KA_T (0xffff << 0) /* RW */
168#define TCP_KA (0xff << 16) /* RW */
169#define UDP_KA (0xff << 24) /* RW */
170
171/*PPE_BIND_LMT_0 mask*/
172#define QURT_LMT (0x3ff << 0) /* RW */
173#define HALF_LMT (0x3ff << 16) /* RW */
174
175/*PPE_BIND_LMT_1 mask*/
176#define FULL_LMT (0x3fff << 0) /* RW */
177#define NTU_KA (0xff << 16) /* RW */
178
179/*PPE_BNDR mask*/
180#define BIND_RATE (0xffff << 0) /* RW */
181#define PBND_RD_PRD (0xffff << 16) /* RW */
182
183/*PPE_GLO_CFG mask*/
184#define PPE_EN (0x1 << 0) /* RW */
185#define TTL0_DRP (0x1 << 4) /* RW */
186#define MCAST_TB_EN (0x1 << 7) /* RW */
187#define MCAST_HASH (0x3 << 12) /* RW */
188
189#define MC_P3_PPSE (0xf << 12) /* RW */
190#define MC_P2_PPSE (0xf << 8) /* RW */
191#define MC_P1_PPSE (0xf << 4) /* RW */
192#define MC_P0_PPSE (0xf << 0) /* RW */
193
194#define MIB_EN (0x1 << 0) /* RW */
195#define MIB_READ_CLEAR (0X1 << 1) /* RW */
196#define MIB_CAH_EN (0X1 << 0) /* RW */
197
198/*GDMA_FWD_CFG mask */
developerd35bbcc2022-09-28 22:46:01 +0800199#define GDM_UFRC_MASK (0xF << 12) /* RW */
200#define GDM_BFRC_MASK (0xF << 8) /*RW*/
201#define GDM_MFRC_MASK (0xF << 4) /*RW*/
202#define GDM_OFRC_MASK (0xF << 0) /*RW*/
developerfd40db22021-04-29 10:08:25 +0800203#define GDM_ALL_FRC_MASK \
204 (GDM_UFRC_MASK | GDM_BFRC_MASK | GDM_MFRC_MASK | GDM_OFRC_MASK)
205
206/*QDMA_PAGE mask*/
207#define QTX_CFG_PAGE (0xf << 0) /* RW */
208
209/*QTX_MIB_IF mask*/
210#define MIB_ON_QTX_CFG (0x1 << 31) /* RW */
211#define VQTX_MIB_EN (0x1 << 28) /* RW */
212
developerd35bbcc2022-09-28 22:46:01 +0800213/* PPE Side Band FIFO Debug Mask */
214#define SB_MED_FULL_DRP_EN (0x1 << 11)
215
developerfd40db22021-04-29 10:08:25 +0800216/*--------------------------------------------------------------------------*/
217/* Descriptor Structure */
218/*--------------------------------------------------------------------------*/
developerd35bbcc2022-09-28 22:46:01 +0800219#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3)
developerfd40db22021-04-29 10:08:25 +0800220struct hnat_unbind_info_blk {
221 u32 time_stamp : 8;
222 u32 sp : 4;
223 u32 pcnt : 8;
224 u32 ilgf : 1;
225 u32 mc : 1;
226 u32 preb : 1;
227 u32 pkt_type : 5;
228 u32 state : 2;
229 u32 udp : 1;
230 u32 sta : 1; /* static entry */
231} __packed;
232
233struct hnat_bind_info_blk {
234 u32 time_stamp : 8;
235 u32 sp : 4;
236 u32 mc : 1;
237 u32 ka : 1; /* keep alive */
238 u32 vlan_layer : 3;
239 u32 psn : 1; /* egress packet has PPPoE session */
240 u32 vpm : 1; /* 0:ethertype remark, 1:0x8100(CR default) */
241 u32 ps : 1; /* packet sampling */
242 u32 cah : 1; /* cacheable flag */
243 u32 rmt : 1; /* remove tunnel ip header (6rd/dslite only) */
244 u32 ttl : 1;
245 u32 pkt_type : 5;
246 u32 state : 2;
247 u32 udp : 1;
248 u32 sta : 1; /* static entry */
249} __packed;
250
251struct hnat_info_blk2 {
252 u32 qid : 7; /* QID in Qos Port */
253 u32 port_mg : 1;
254 u32 fqos : 1; /* force to PSE QoS port */
255 u32 dp : 4; /* force to PSE port x */
256 u32 mcast : 1; /* multicast this packet to CPU */
257 u32 pcpl : 1; /* OSBN */
258 u32 mibf : 1;
259 u32 alen : 1;
260 u32 rxid : 2;
261 u32 winfoi : 1;
262 u32 port_ag : 4;
263 u32 dscp : 8; /* DSCP value */
264} __packed;
265
developerd35bbcc2022-09-28 22:46:01 +0800266#if defined(CONFIG_MEDIATEK_NETSYS_V3)
267struct hnat_winfo {
268 u32 wcid : 16; /* WiFi wtable Idx */
269 u32 bssid : 8; /* WiFi Bssidx */
270 u32 resv : 8;
271} __packed;
272
273struct hnat_winfo_pao {
274 u32 usr_info : 16;
275 u32 tid : 4;
276 u32 is_fixedrate : 1;
277 u32 is_prior : 1;
278 u32 is_sp : 1;
279 u32 hf : 1;
280 u32 amsdu : 1;
281 u32 resv : 7;
282} __packed;
283#elif defined(CONFIG_MEDIATEK_NETSYS_V2)
developerfd40db22021-04-29 10:08:25 +0800284struct hnat_winfo {
285 u32 bssid : 6; /* WiFi Bssidx */
286 u32 wcid : 10; /* WiFi wtable Idx */
287} __packed;
developerd35bbcc2022-09-28 22:46:01 +0800288#endif
developerfd40db22021-04-29 10:08:25 +0800289
290#else
291struct hnat_unbind_info_blk {
292 u32 time_stamp : 8;
293 u32 pcnt : 16; /* packet count */
294 u32 preb : 1;
295 u32 pkt_type : 3;
296 u32 state : 2;
297 u32 udp : 1;
298 u32 sta : 1; /* static entry */
299} __packed;
300
301struct hnat_bind_info_blk {
302 u32 time_stamp : 15;
303 u32 ka : 1; /* keep alive */
304 u32 vlan_layer : 3;
305 u32 psn : 1; /* egress packet has PPPoE session */
306 u32 vpm : 1; /* 0:ethertype remark, 1:0x8100(CR default) */
307 u32 ps : 1; /* packet sampling */
308 u32 cah : 1; /* cacheable flag */
309 u32 rmt : 1; /* remove tunnel ip header (6rd/dslite only) */
310 u32 ttl : 1;
311 u32 pkt_type : 3;
312 u32 state : 2;
313 u32 udp : 1;
314 u32 sta : 1; /* static entry */
315} __packed;
316
317struct hnat_info_blk2 {
318 u32 qid : 4; /* QID in Qos Port */
319 u32 fqos : 1; /* force to PSE QoS port */
320 u32 dp : 3; /* force to PSE port x
321 * 0:PSE,1:GSW, 2:GMAC,4:PPE,5:QDMA,7=DROP
322 */
323 u32 mcast : 1; /* multicast this packet to CPU */
324 u32 pcpl : 1; /* OSBN */
325 u32 mibf : 1; /* 0:off 1:on PPE MIB counter */
326 u32 alen : 1; /* 0:post 1:pre packet length in accounting */
327 u32 port_mg : 6; /* port meter group */
328 u32 port_ag : 6; /* port account group */
329 u32 dscp : 8; /* DSCP value */
330} __packed;
331
332struct hnat_winfo {
333 u32 bssid : 6; /* WiFi Bssidx */
334 u32 wcid : 8; /* WiFi wtable Idx */
335 u32 rxid : 2; /* WiFi Ring idx */
336} __packed;
337#endif
338
339/* info blk2 for WHNAT */
340struct hnat_info_blk2_whnat {
341 u32 qid : 4; /* QID[3:0] in Qos Port */
342 u32 fqos : 1; /* force to PSE QoS port */
343 u32 dp : 3; /* force to PSE port x
344 * 0:PSE,1:GSW, 2:GMAC,4:PPE,5:QDMA,7=DROP
345 */
346 u32 mcast : 1; /* multicast this packet to CPU */
347 u32 pcpl : 1; /* OSBN */
348 u32 mibf : 1; /* 0:off 1:on PPE MIB counter */
349 u32 alen : 1; /* 0:post 1:pre packet length in accounting */
350 u32 qid2 : 2; /* QID[5:4] in Qos Port */
351 u32 resv : 2;
352 u32 wdmaid : 1; /* 0:to pcie0 dev 1:to pcie1 dev */
353 u32 winfoi : 1; /* 0:off 1:on Wi-Fi hwnat support */
354 u32 port_ag : 6; /* port account group */
355 u32 dscp : 8; /* DSCP value */
356} __packed;
357
358struct hnat_ipv4_hnapt {
359 union {
360 struct hnat_bind_info_blk bfib1;
361 struct hnat_unbind_info_blk udib1;
362 u32 info_blk1;
363 };
364 u32 sip;
365 u32 dip;
366 u16 dport;
367 u16 sport;
368 union {
369 struct hnat_info_blk2 iblk2;
370 struct hnat_info_blk2_whnat iblk2w;
371 u32 info_blk2;
372 };
373 u32 new_sip;
374 u32 new_dip;
375 u16 new_dport;
376 u16 new_sport;
377 u16 m_timestamp; /* For mcast*/
378 u16 resv1;
379 u32 resv2;
380 u32 resv3 : 26;
381 u32 act_dp : 6; /* UDF */
382 u16 vlan1;
383 u16 etype;
384 u32 dmac_hi;
385 union {
developerd35bbcc2022-09-28 22:46:01 +0800386#if !defined(CONFIG_MEDIATEK_NETSYS_V2) && !defined(CONFIG_MEDIATEK_NETSYS_V3)
developerfd40db22021-04-29 10:08:25 +0800387 struct hnat_winfo winfo;
388#endif
389 u16 vlan2;
390 };
391 u16 dmac_lo;
392 u32 smac_hi;
393 u16 pppoe_id;
394 u16 smac_lo;
developer22fd7712022-10-06 14:13:52 +0800395#if defined(CONFIG_MEDIATEK_NETSYS_V3)
developerd35bbcc2022-09-28 22:46:01 +0800396 u16 minfo;
397 u16 resv4;
developerfd40db22021-04-29 10:08:25 +0800398 struct hnat_winfo winfo;
developerd35bbcc2022-09-28 22:46:01 +0800399 struct hnat_winfo_pao winfo_pao;
400 u32 cdrt_id : 8;
401 u32 tops_entry : 6;
402 u32 resv5 : 2;
403 u32 tport_id : 4;
404 u32 resv6 : 12;
developer22fd7712022-10-06 14:13:52 +0800405#elif defined(CONFIG_MEDIATEK_NETSYS_V2)
406 u16 minfo;
407 struct hnat_winfo winfo;
developerfd40db22021-04-29 10:08:25 +0800408#endif
409} __packed;
410
411struct hnat_ipv4_dslite {
412 union {
413 struct hnat_bind_info_blk bfib1;
414 struct hnat_unbind_info_blk udib1;
415 u32 info_blk1;
416 };
417 u32 sip;
418 u32 dip;
419 u16 dport;
420 u16 sport;
421
422 u32 tunnel_sipv6_0;
423 u32 tunnel_sipv6_1;
424 u32 tunnel_sipv6_2;
425 u32 tunnel_sipv6_3;
426
427 u32 tunnel_dipv6_0;
428 u32 tunnel_dipv6_1;
429 u32 tunnel_dipv6_2;
430 u32 tunnel_dipv6_3;
431
432 u8 flow_lbl[3]; /* in order to consist with Linux kernel (should be 20bits) */
433 u8 priority; /* in order to consist with Linux kernel (should be 8bits) */
434 u32 hop_limit : 8;
435 u32 resv2 : 18;
436 u32 act_dp : 6; /* UDF */
437
438 union {
439 struct hnat_info_blk2 iblk2;
440 struct hnat_info_blk2_whnat iblk2w;
441 u32 info_blk2;
442 };
443
444 u16 vlan1;
445 u16 etype;
446 u32 dmac_hi;
447 union {
developerd35bbcc2022-09-28 22:46:01 +0800448#if !defined(CONFIG_MEDIATEK_NETSYS_V2) && !defined(CONFIG_MEDIATEK_NETSYS_V3)
developerfd40db22021-04-29 10:08:25 +0800449 struct hnat_winfo winfo;
450#endif
451 u16 vlan2;
452 };
453 u16 dmac_lo;
454 u32 smac_hi;
455 u16 pppoe_id;
456 u16 smac_lo;
developer22fd7712022-10-06 14:13:52 +0800457#if defined(CONFIG_MEDIATEK_NETSYS_V3)
developerd35bbcc2022-09-28 22:46:01 +0800458 u16 minfo;
459 u16 resv3;
460 struct hnat_winfo winfo;
461 struct hnat_winfo_pao winfo_pao;
462 u32 cdrt_id : 8;
463 u32 tops_entry : 6;
464 u32 resv4 : 2;
465 u32 tport_id : 4;
466 u32 resv5 : 12;
developer22fd7712022-10-06 14:13:52 +0800467#elif defined(CONFIG_MEDIATEK_NETSYS_V2)
468 u16 minfo;
469 struct hnat_winfo winfo;
developerd35bbcc2022-09-28 22:46:01 +0800470#endif
471} __packed;
472
473struct hnat_ipv4_mape {
474 union {
475 struct hnat_bind_info_blk bfib1;
476 struct hnat_unbind_info_blk udib1;
477 u32 info_blk1;
478 };
479 u32 sip;
480 u32 dip;
481 u16 dport;
482 u16 sport;
483
484 u32 tunnel_sipv6_0;
485 u32 tunnel_sipv6_1;
486 u32 tunnel_sipv6_2;
487 u32 tunnel_sipv6_3;
488
489 u32 tunnel_dipv6_0;
490 u32 tunnel_dipv6_1;
491 u32 tunnel_dipv6_2;
492 u32 tunnel_dipv6_3;
493
494 u8 flow_lbl[3]; /* in order to consist with Linux kernel (should be 20bits) */
495 u8 priority; /* in order to consist with Linux kernel (should be 8bits) */
496 u32 hop_limit : 8;
497 u32 resv2 : 18;
498 u32 act_dp : 6; /* UDF */
499
500 union {
501 struct hnat_info_blk2 iblk2;
502 struct hnat_info_blk2_whnat iblk2w;
503 u32 info_blk2;
504 };
505
506 u16 vlan1;
507 u16 etype;
508 u32 dmac_hi;
509 union {
510#if !defined(CONFIG_MEDIATEK_NETSYS_V2) && !defined(CONFIG_MEDIATEK_NETSYS_V3)
511 struct hnat_winfo winfo;
512#endif
513 u16 vlan2;
514 };
515 u16 dmac_lo;
516 u32 smac_hi;
517 u16 pppoe_id;
518 u16 smac_lo;
developer22fd7712022-10-06 14:13:52 +0800519#if defined(CONFIG_MEDIATEK_NETSYS_V3)
developerd35bbcc2022-09-28 22:46:01 +0800520 u16 minfo;
521 u16 resv3;
522 u32 new_sip;
523 u32 new_dip;
524 u16 new_dport;
525 u16 new_sport;
526 struct hnat_winfo winfo;
527 struct hnat_winfo_pao winfo_pao;
528 u32 cdrt_id : 8;
529 u32 tops_entry : 6;
530 u32 resv4 : 2;
531 u32 tport_id : 4;
532 u32 resv5 : 12;
developer22fd7712022-10-06 14:13:52 +0800533#elif defined(CONFIG_MEDIATEK_NETSYS_V2)
534 u16 minfo;
535 struct hnat_winfo winfo;
536 u32 new_sip;
537 u32 new_dip;
538 u16 new_dport;
539 u16 new_sport;
developerfd40db22021-04-29 10:08:25 +0800540#endif
541} __packed;
542
543struct hnat_ipv6_3t_route {
544 union {
545 struct hnat_bind_info_blk bfib1;
546 struct hnat_unbind_info_blk udib1;
547 u32 info_blk1;
548 };
549 u32 ipv6_sip0;
550 u32 ipv6_sip1;
551 u32 ipv6_sip2;
552 u32 ipv6_sip3;
553 u32 ipv6_dip0;
554 u32 ipv6_dip1;
555 u32 ipv6_dip2;
556 u32 ipv6_dip3;
557 u32 prot : 8;
developer729f0272021-06-09 17:28:38 +0800558 u32 hph : 24; /* hash placeholder */
developerfd40db22021-04-29 10:08:25 +0800559
560 u32 resv1;
561 u32 resv2;
562 u32 resv3;
563 u32 resv4 : 26;
564 u32 act_dp : 6; /* UDF */
565
566 union {
567 struct hnat_info_blk2 iblk2;
568 struct hnat_info_blk2_whnat iblk2w;
569 u32 info_blk2;
570 };
571 u16 vlan1;
572 u16 etype;
573 u32 dmac_hi;
574 union {
developerd35bbcc2022-09-28 22:46:01 +0800575#if !defined(CONFIG_MEDIATEK_NETSYS_V2) && !defined(CONFIG_MEDIATEK_NETSYS_V3)
developerfd40db22021-04-29 10:08:25 +0800576 struct hnat_winfo winfo;
577#endif
578 u16 vlan2;
579 };
580 u16 dmac_lo;
581 u32 smac_hi;
582 u16 pppoe_id;
583 u16 smac_lo;
developer22fd7712022-10-06 14:13:52 +0800584#if defined(CONFIG_MEDIATEK_NETSYS_V3)
developerd35bbcc2022-09-28 22:46:01 +0800585 u16 minfo;
586 u16 resv5;
587 struct hnat_winfo winfo;
588 struct hnat_winfo_pao winfo_pao;
589 u32 cdrt_id : 8;
590 u32 tops_entry : 6;
591 u32 resv6 : 2;
592 u32 tport_id : 4;
593 u32 resv7 : 12;
developer22fd7712022-10-06 14:13:52 +0800594#elif defined(CONFIG_MEDIATEK_NETSYS_V2)
595 u16 minfo;
596 struct hnat_winfo winfo;
developerfd40db22021-04-29 10:08:25 +0800597#endif
598} __packed;
599
600struct hnat_ipv6_5t_route {
601 union {
602 struct hnat_bind_info_blk bfib1;
603 struct hnat_unbind_info_blk udib1;
604 u32 info_blk1;
605 };
606 u32 ipv6_sip0;
607 u32 ipv6_sip1;
608 u32 ipv6_sip2;
609 u32 ipv6_sip3;
610 u32 ipv6_dip0;
611 u32 ipv6_dip1;
612 u32 ipv6_dip2;
613 u32 ipv6_dip3;
614 u16 dport;
615 u16 sport;
616
617 u32 resv1;
618 u32 resv2;
619 u32 resv3;
620 u32 resv4 : 26;
621 u32 act_dp : 6; /* UDF */
622
623 union {
624 struct hnat_info_blk2 iblk2;
625 struct hnat_info_blk2_whnat iblk2w;
626 u32 info_blk2;
627 };
628
629 u16 vlan1;
630 u16 etype;
631 u32 dmac_hi;
632 union {
developerd35bbcc2022-09-28 22:46:01 +0800633#if !defined(CONFIG_MEDIATEK_NETSYS_V2) && !defined(CONFIG_MEDIATEK_NETSYS_V3)
developerfd40db22021-04-29 10:08:25 +0800634 struct hnat_winfo winfo;
635#endif
636 u16 vlan2;
637 };
638 u16 dmac_lo;
639 u32 smac_hi;
640 u16 pppoe_id;
641 u16 smac_lo;
developer22fd7712022-10-06 14:13:52 +0800642#if defined(CONFIG_MEDIATEK_NETSYS_V3)
developerd35bbcc2022-09-28 22:46:01 +0800643 u16 minfo;
644 u16 resv5;
developerfd40db22021-04-29 10:08:25 +0800645 struct hnat_winfo winfo;
developerd35bbcc2022-09-28 22:46:01 +0800646 struct hnat_winfo_pao winfo_pao;
647 u32 cdrt_id : 8;
648 u32 tops_entry : 6;
649 u32 resv6 : 2;
650 u32 tport_id : 4;
651 u32 resv7 : 12;
developer22fd7712022-10-06 14:13:52 +0800652#elif defined(CONFIG_MEDIATEK_NETSYS_V2)
653 u16 minfo;
654 struct hnat_winfo winfo;
developerfd40db22021-04-29 10:08:25 +0800655#endif
656} __packed;
657
658struct hnat_ipv6_6rd {
659 union {
660 struct hnat_bind_info_blk bfib1;
661 struct hnat_unbind_info_blk udib1;
662 u32 info_blk1;
663 };
664 u32 ipv6_sip0;
665 u32 ipv6_sip1;
666 u32 ipv6_sip2;
667 u32 ipv6_sip3;
668 u32 ipv6_dip0;
669 u32 ipv6_dip1;
670 u32 ipv6_dip2;
671 u32 ipv6_dip3;
672 u16 dport;
673 u16 sport;
674
675 u32 tunnel_sipv4;
676 u32 tunnel_dipv4;
677 u32 hdr_chksum : 16;
678 u32 dscp : 8;
679 u32 ttl : 8;
680 u32 flag : 3;
681 u32 resv1 : 13;
682 u32 per_flow_6rd_id : 1;
683 u32 resv2 : 9;
684 u32 act_dp : 6; /* UDF */
685
686 union {
687 struct hnat_info_blk2 iblk2;
688 struct hnat_info_blk2_whnat iblk2w;
689 u32 info_blk2;
690 };
691
692 u16 vlan1;
693 u16 etype;
694 u32 dmac_hi;
695 union {
developerd35bbcc2022-09-28 22:46:01 +0800696#if !defined(CONFIG_MEDIATEK_NETSYS_V2) && !defined(CONFIG_MEDIATEK_NETSYS_V3)
developerfd40db22021-04-29 10:08:25 +0800697 struct hnat_winfo winfo;
698#endif
699 u16 vlan2;
700 };
701 u16 dmac_lo;
702 u32 smac_hi;
703 u16 pppoe_id;
704 u16 smac_lo;
developer22fd7712022-10-06 14:13:52 +0800705#if defined(CONFIG_MEDIATEK_NETSYS_V3)
developerd35bbcc2022-09-28 22:46:01 +0800706 u16 minfo;
707 u16 resv3;
708 struct hnat_winfo winfo;
709 struct hnat_winfo_pao winfo_pao;
710 u32 cdrt_id : 8;
711 u32 tops_entry : 6;
712 u32 resv4 : 2;
713 u32 tport_id : 4;
714 u32 resv5 : 12;
developer22fd7712022-10-06 14:13:52 +0800715#elif defined(CONFIG_MEDIATEK_NETSYS_V2)
716 u16 minfo;
717 struct hnat_winfo winfo;
developer5ffc5f12022-10-25 18:51:46 +0800718#endif
719} __packed;
720
721struct hnat_ipv6_hnapt {
722 union {
723 struct hnat_bind_info_blk bfib1;
724 struct hnat_unbind_info_blk udib1;
725 u32 info_blk1;
726 };
727 u32 ipv6_sip0;
728 u32 ipv6_sip1;
729 u32 ipv6_sip2;
730 u32 ipv6_sip3;
731 u32 ipv6_dip0;
732 u32 ipv6_dip1;
733 u32 ipv6_dip2;
734 u32 ipv6_dip3;
735 u16 dport;
736 u16 sport;
737
738 u32 resv1;
739 u32 resv2;
developer22fd7712022-10-06 14:13:52 +0800740 u32 resv3;
developer5ffc5f12022-10-25 18:51:46 +0800741 u32 resv4 : 8;
742 u32 eg_ipv6_dir : 1;
743 u32 eg_keep_ecn : 1;
744 u32 eg_keep_cls : 1;
745 u32 resv5 : 15;
746 u32 act_dp : 6; /* UDF */
747
748 union {
749 struct hnat_info_blk2 iblk2;
750 struct hnat_info_blk2_whnat iblk2w;
751 u32 info_blk2;
752 };
753
754 u16 vlan1;
755 u16 etype;
756 u32 dmac_hi;
757 u16 vlan2;
758 u16 dmac_lo;
759 u32 smac_hi;
760 u16 pppoe_id;
761 u16 smac_lo;
762#if defined(CONFIG_MEDIATEK_NETSYS_V3)
763 u16 minfo;
764 u16 resv6;
765 u32 new_ipv6_ip0;
766 u32 new_ipv6_ip1;
767 u32 new_ipv6_ip2;
768 u32 new_ipv6_ip3;
developer22fd7712022-10-06 14:13:52 +0800769 u16 new_dport;
770 u16 new_sport;
developer5ffc5f12022-10-25 18:51:46 +0800771 struct hnat_winfo winfo;
772 struct hnat_winfo_pao winfo_pao;
773 u32 cdrt_id : 8;
774 u32 tops_entry : 6;
775 u32 resv7 : 2;
776 u32 tport_id : 4;
777 u32 resv8 : 12;
778 u32 resv9;
779 u32 resv10;
780 u32 resv11;
781#elif defined(CONFIG_MEDIATEK_NETSYS_V2)
782 u16 minfo;
783 struct hnat_winfo winfo;
developerfd40db22021-04-29 10:08:25 +0800784#endif
785} __packed;
786
787struct foe_entry {
788 union {
789 struct hnat_unbind_info_blk udib1;
790 struct hnat_bind_info_blk bfib1;
791 struct hnat_ipv4_hnapt ipv4_hnapt;
792 struct hnat_ipv4_dslite ipv4_dslite;
developerd35bbcc2022-09-28 22:46:01 +0800793 struct hnat_ipv4_mape ipv4_mape;
developerfd40db22021-04-29 10:08:25 +0800794 struct hnat_ipv6_3t_route ipv6_3t_route;
795 struct hnat_ipv6_5t_route ipv6_5t_route;
796 struct hnat_ipv6_6rd ipv6_6rd;
developer5ffc5f12022-10-25 18:51:46 +0800797 struct hnat_ipv6_hnapt ipv6_hnapt;
developerfd40db22021-04-29 10:08:25 +0800798 };
799};
800
801/* If user wants to change default FOE entry number, both DEF_ETRY_NUM and
802 * DEF_ETRY_NUM_CFG need to be modified.
803 */
804#define DEF_ETRY_NUM 8192
developerbc53e5f2021-05-21 10:07:17 +0800805/* feasible values : 32768, 16384, 8192, 4096, 2048, 1024 */
developerfd40db22021-04-29 10:08:25 +0800806#define DEF_ETRY_NUM_CFG TABLE_8K
developerbc53e5f2021-05-21 10:07:17 +0800807/* corresponding values : TABLE_32K, TABLE_16K, TABLE_8K, TABLE_4K, TABLE_2K,
808 * TABLE_1K
809 */
developerfd40db22021-04-29 10:08:25 +0800810#define MAX_EXT_DEVS (0x3fU)
811#define MAX_IF_NUM 64
812
developerd35bbcc2022-09-28 22:46:01 +0800813#if defined(CONFIG_MEDIATEK_NETSYS_V3)
814#define MAX_PPE_NUM 3
815#elif defined(CONFIG_MEDIATEK_NETSYS_V2)
developer471f6562021-05-10 20:48:34 +0800816#define MAX_PPE_NUM 2
817#else
818#define MAX_PPE_NUM 1
819#endif
820#define CFG_PPE_NUM (hnat_priv->ppe_num)
821
developerfd40db22021-04-29 10:08:25 +0800822struct mib_entry {
823 u32 byt_cnt_l;
824 u16 byt_cnt_h;
825 u32 pkt_cnt_l;
826 u8 pkt_cnt_h;
827 u8 resv0;
828 u32 resv1;
829} __packed;
830
831struct hnat_accounting {
832 u64 bytes;
833 u64 packets;
834};
835
836enum mtk_hnat_version {
developer4164cfe2022-12-01 11:27:41 +0800837 MTK_HNAT_V1_1 = 1, /* version 1.1: mt7621, mt7623 */
838 MTK_HNAT_V1_2, /* version 1.2: mt7622 */
839 MTK_HNAT_V1_3, /* version 1.3: mt7629 */
840 MTK_HNAT_V2, /* version 2: mt7981, mt7986 */
841 MTK_HNAT_V3, /* version 3: mt7988 */
developerfd40db22021-04-29 10:08:25 +0800842};
843
844struct mtk_hnat_data {
845 u8 num_of_sch;
846 bool whnat;
847 bool per_flow_accounting;
848 bool mcast;
849 enum mtk_hnat_version version;
850};
851
852struct mtk_hnat {
853 struct device *dev;
854 void __iomem *fe_base;
developer471f6562021-05-10 20:48:34 +0800855 void __iomem *ppe_base[MAX_PPE_NUM];
856 struct foe_entry *foe_table_cpu[MAX_PPE_NUM];
857 dma_addr_t foe_table_dev[MAX_PPE_NUM];
developerfd40db22021-04-29 10:08:25 +0800858 u8 enable;
859 u8 enable1;
860 struct dentry *root;
developer471f6562021-05-10 20:48:34 +0800861 struct debugfs_regset32 *regset[MAX_PPE_NUM];
developerfd40db22021-04-29 10:08:25 +0800862
developer471f6562021-05-10 20:48:34 +0800863 struct mib_entry *foe_mib_cpu[MAX_PPE_NUM];
864 dma_addr_t foe_mib_dev[MAX_PPE_NUM];
865 struct hnat_accounting *acct[MAX_PPE_NUM];
developerfd40db22021-04-29 10:08:25 +0800866 const struct mtk_hnat_data *data;
867
868 /*devices we plays for*/
869 char wan[IFNAMSIZ];
870 char lan[IFNAMSIZ];
developerd35bbcc2022-09-28 22:46:01 +0800871 char lan2[IFNAMSIZ];
developerfd40db22021-04-29 10:08:25 +0800872 char ppd[IFNAMSIZ];
873 u16 lvid;
874 u16 wvid;
875
876 struct reset_control *rstc;
877
developer471f6562021-05-10 20:48:34 +0800878 u8 ppe_num;
developerfd40db22021-04-29 10:08:25 +0800879 u8 gmac_num;
880 u8 wan_dsa_port;
881 struct ppe_mcast_table *pmcast;
882
883 u32 foe_etry_num;
developer8051e042022-04-08 13:26:36 +0800884 u32 etry_num_cfg;
developerfd40db22021-04-29 10:08:25 +0800885 struct net_device *g_ppdev;
developer8c9c0d02021-06-18 16:15:37 +0800886 struct net_device *g_wandev;
developerfd40db22021-04-29 10:08:25 +0800887 struct net_device *wifi_hook_if[MAX_IF_NUM];
888 struct extdev_entry *ext_if[MAX_EXT_DEVS];
889 struct timer_list hnat_sma_build_entry_timer;
890 struct timer_list hnat_reset_timestamp_timer;
891 struct timer_list hnat_mcast_check_timer;
developer30a47682021-11-02 17:06:14 +0800892 bool nf_stat_en;
developerfd40db22021-04-29 10:08:25 +0800893};
894
895struct extdev_entry {
896 char name[IFNAMSIZ];
897 struct net_device *dev;
898};
899
900struct tcpudphdr {
901 __be16 src;
902 __be16 dst;
903};
904
905enum FoeEntryState { INVALID = 0, UNBIND = 1, BIND = 2, FIN = 3 };
906
907enum FoeIpAct {
908 IPV4_HNAPT = 0,
909 IPV4_HNAT = 1,
910 IPV4_DSLITE = 3,
911 IPV6_3T_ROUTE = 4,
912 IPV6_5T_ROUTE = 5,
913 IPV6_6RD = 7,
developerfd40db22021-04-29 10:08:25 +0800914 IPV4_MAP_T = 8,
915 IPV4_MAP_E = 9,
developer5ffc5f12022-10-25 18:51:46 +0800916 IPV6_HNAPT = 10,
917 IPV6_HNAT = 11,
developerfd40db22021-04-29 10:08:25 +0800918};
919
920/*--------------------------------------------------------------------------*/
921/* Common Definition*/
922/*--------------------------------------------------------------------------*/
923
924#define HNAT_SW_VER "1.1.0"
925#define HASH_SEED_KEY 0x12345678
926
927/*PPE_TB_CFG value*/
developerd35bbcc2022-09-28 22:46:01 +0800928#define ENTRY_128B 0
929#define ENTRY_96B 1
developerfd40db22021-04-29 10:08:25 +0800930#define ENTRY_80B 1
developerfd40db22021-04-29 10:08:25 +0800931#define TABLE_1K 0
932#define TABLE_2K 1
933#define TABLE_4K 2
934#define TABLE_8K 3
935#define TABLE_16K 4
developerbc53e5f2021-05-21 10:07:17 +0800936#define TABLE_32K 5
developerfd40db22021-04-29 10:08:25 +0800937#define SMA_DROP 0 /* Drop the packet */
938#define SMA_DROP2 1 /* Drop the packet */
939#define SMA_ONLY_FWD_CPU 2 /* Only Forward to CPU */
940#define SMA_FWD_CPU_BUILD_ENTRY 3 /* Forward to CPU and build new FOE entry */
941#define HASH_MODE_0 0
942#define HASH_MODE_1 1
943#define HASH_MODE_2 2
944#define HASH_MODE_3 3
945
946/*PPE_FLOW_CFG*/
947#define BIT_FUC_FOE BIT(2)
948#define BIT_FMC_FOE BIT(1)
949#define BIT_FBC_FOE BIT(0)
950#define BIT_UDP_IP4F_NAT_EN BIT(7) /*Enable IPv4 fragment + UDP packet NAT*/
951#define BIT_IPV6_3T_ROUTE_EN BIT(8)
952#define BIT_IPV6_5T_ROUTE_EN BIT(9)
953#define BIT_IPV6_6RD_EN BIT(10)
954#define BIT_IPV4_NAT_EN BIT(12)
955#define BIT_IPV4_NAPT_EN BIT(13)
956#define BIT_IPV4_DSL_EN BIT(14)
957#define BIT_MIB_BUSY BIT(16)
958#define BIT_IPV4_NAT_FRAG_EN BIT(17)
959#define BIT_IPV4_HASH_GREK BIT(19)
960#define BIT_IPV6_HASH_GREK BIT(20)
961#define BIT_IPV4_MAPE_EN BIT(21)
962#define BIT_IPV4_MAPT_EN BIT(22)
developer5ffc5f12022-10-25 18:51:46 +0800963#define BIT_IPV6_NAT_EN BIT(23)
964#define BIT_IPV6_NAPT_EN BIT(24)
965#define BIT_CS0_RM_ALL_IP6_IP_EN BIT(25)
developerfd40db22021-04-29 10:08:25 +0800966
967/*GDMA_FWD_CFG value*/
developer471f6562021-05-10 20:48:34 +0800968#define BITS_GDM_UFRC_P_PPE (NR_PPE0_PORT << 12)
969#define BITS_GDM_BFRC_P_PPE (NR_PPE0_PORT << 8)
970#define BITS_GDM_MFRC_P_PPE (NR_PPE0_PORT << 4)
971#define BITS_GDM_OFRC_P_PPE (NR_PPE0_PORT << 0)
developerfd40db22021-04-29 10:08:25 +0800972#define BITS_GDM_ALL_FRC_P_PPE \
973 (BITS_GDM_UFRC_P_PPE | BITS_GDM_BFRC_P_PPE | BITS_GDM_MFRC_P_PPE | \
974 BITS_GDM_OFRC_P_PPE)
975
developerd35bbcc2022-09-28 22:46:01 +0800976#define BITS_GDM_UFRC_P_PPE1 (NR_PPE1_PORT << 12)
977#define BITS_GDM_BFRC_P_PPE1 (NR_PPE1_PORT << 8)
978#define BITS_GDM_MFRC_P_PPE1 (NR_PPE1_PORT << 4)
979#define BITS_GDM_OFRC_P_PPE1 (NR_PPE1_PORT << 0)
980#define BITS_GDM_ALL_FRC_P_PPE1 \
981 (BITS_GDM_UFRC_P_PPE1 | BITS_GDM_BFRC_P_PPE1 | \
982 BITS_GDM_MFRC_P_PPE1 | BITS_GDM_OFRC_P_PPE1)
983
984#define BITS_GDM_UFRC_P_PPE2 (NR_PPE2_PORT << 12)
985#define BITS_GDM_BFRC_P_PPE2 (NR_PPE2_PORT << 8)
986#define BITS_GDM_MFRC_P_PPE2 (NR_PPE2_PORT << 4)
987#define BITS_GDM_OFRC_P_PPE2 (NR_PPE2_PORT << 0)
988#define BITS_GDM_ALL_FRC_P_PPE2 \
989 (BITS_GDM_UFRC_P_PPE2 | BITS_GDM_BFRC_P_PPE2 | \
990 BITS_GDM_MFRC_P_PPE2 | BITS_GDM_OFRC_P_PPE2)
991
developerfd40db22021-04-29 10:08:25 +0800992#define BITS_GDM_UFRC_P_CPU_PDMA (NR_PDMA_PORT << 12)
993#define BITS_GDM_BFRC_P_CPU_PDMA (NR_PDMA_PORT << 8)
994#define BITS_GDM_MFRC_P_CPU_PDMA (NR_PDMA_PORT << 4)
995#define BITS_GDM_OFRC_P_CPU_PDMA (NR_PDMA_PORT << 0)
996#define BITS_GDM_ALL_FRC_P_CPU_PDMA \
997 (BITS_GDM_UFRC_P_CPU_PDMA | BITS_GDM_BFRC_P_CPU_PDMA | \
998 BITS_GDM_MFRC_P_CPU_PDMA | BITS_GDM_OFRC_P_CPU_PDMA)
999
1000#define BITS_GDM_UFRC_P_CPU_QDMA (NR_QDMA_PORT << 12)
1001#define BITS_GDM_BFRC_P_CPU_QDMA (NR_QDMA_PORT << 8)
1002#define BITS_GDM_MFRC_P_CPU_QDMA (NR_QDMA_PORT << 4)
1003#define BITS_GDM_OFRC_P_CPU_QDMA (NR_QDMA_PORT << 0)
1004#define BITS_GDM_ALL_FRC_P_CPU_QDMA \
1005 (BITS_GDM_UFRC_P_CPU_QDMA | BITS_GDM_BFRC_P_CPU_QDMA | \
1006 BITS_GDM_MFRC_P_CPU_QDMA | BITS_GDM_OFRC_P_CPU_QDMA)
1007
1008#define BITS_GDM_UFRC_P_DISCARD (NR_DISCARD << 12)
1009#define BITS_GDM_BFRC_P_DISCARD (NR_DISCARD << 8)
1010#define BITS_GDM_MFRC_P_DISCARD (NR_DISCARD << 4)
1011#define BITS_GDM_OFRC_P_DISCARD (NR_DISCARD << 0)
1012#define BITS_GDM_ALL_FRC_P_DISCARD \
1013 (BITS_GDM_UFRC_P_DISCARD | BITS_GDM_BFRC_P_DISCARD | \
1014 BITS_GDM_MFRC_P_DISCARD | BITS_GDM_OFRC_P_DISCARD)
1015
1016#define hnat_is_enabled(hnat_priv) (hnat_priv->enable)
1017#define hnat_enabled(hnat_priv) (hnat_priv->enable = 1)
1018#define hnat_disabled(hnat_priv) (hnat_priv->enable = 0)
1019#define hnat_is_enabled1(hnat_priv) (hnat_priv->enable1)
1020#define hnat_enabled1(hnat_priv) (hnat_priv->enable1 = 1)
1021#define hnat_disabled1(hnat_priv) (hnat_priv->enable1 = 0)
1022
1023#define entry_hnat_is_bound(e) (e->bfib1.state == BIND)
1024#define entry_hnat_state(e) (e->bfib1.state)
1025
1026#define skb_hnat_is_hashed(skb) \
1027 (skb_hnat_entry(skb) != 0x3fff && skb_hnat_entry(skb) < hnat_priv->foe_etry_num)
developerd35bbcc2022-09-28 22:46:01 +08001028#define FROM_GE_LAN_GRP(skb) (FROM_GE_LAN(skb) | FROM_GE_LAN2(skb))
developerfd40db22021-04-29 10:08:25 +08001029#define FROM_GE_LAN(skb) (skb_hnat_iface(skb) == FOE_MAGIC_GE_LAN)
developerd35bbcc2022-09-28 22:46:01 +08001030#define FROM_GE_LAN2(skb) (skb_hnat_iface(skb) == FOE_MAGIC_GE_LAN2)
developerfd40db22021-04-29 10:08:25 +08001031#define FROM_GE_WAN(skb) (skb_hnat_iface(skb) == FOE_MAGIC_GE_WAN)
1032#define FROM_GE_PPD(skb) (skb_hnat_iface(skb) == FOE_MAGIC_GE_PPD)
1033#define FROM_GE_VIRTUAL(skb) (skb_hnat_iface(skb) == FOE_MAGIC_GE_VIRTUAL)
1034#define FROM_EXT(skb) (skb_hnat_iface(skb) == FOE_MAGIC_EXT)
developere567ad32021-05-25 17:16:17 +08001035#define FROM_WED(skb) ((skb_hnat_iface(skb) == FOE_MAGIC_WED0) || \
1036 (skb_hnat_iface(skb) == FOE_MAGIC_WED1))
developerfd40db22021-04-29 10:08:25 +08001037#define FOE_MAGIC_GE_LAN 0x1
1038#define FOE_MAGIC_GE_WAN 0x2
1039#define FOE_MAGIC_EXT 0x3
1040#define FOE_MAGIC_GE_VIRTUAL 0x4
1041#define FOE_MAGIC_GE_PPD 0x5
developerd35bbcc2022-09-28 22:46:01 +08001042#define FOE_MAGIC_GE_LAN2 0x6
developere567ad32021-05-25 17:16:17 +08001043#define FOE_MAGIC_WED0 0x78
1044#define FOE_MAGIC_WED1 0x79
developerd35bbcc2022-09-28 22:46:01 +08001045#define FOE_MAGIC_WED2 0x7A
developerfd40db22021-04-29 10:08:25 +08001046#define FOE_INVALID 0xf
1047#define index6b(i) (0x3fU - i)
1048
1049#define IPV4_HNAPT 0
1050#define IPV4_HNAT 1
1051#define IP_FORMAT(addr) \
1052 (((unsigned char *)&addr)[3], ((unsigned char *)&addr)[2], \
1053 ((unsigned char *)&addr)[1], ((unsigned char *)&addr)[0])
1054
1055/*PSE Ports*/
1056#define NR_PDMA_PORT 0
1057#define NR_GMAC1_PORT 1
1058#define NR_GMAC2_PORT 2
developerd35bbcc2022-09-28 22:46:01 +08001059#if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3)
developer471f6562021-05-10 20:48:34 +08001060#define NR_WHNAT_WDMA_PORT EINVAL
1061#define NR_PPE0_PORT 3
1062#define NR_PPE1_PORT 4
developerd35bbcc2022-09-28 22:46:01 +08001063#define NR_PPE2_PORT 0xC
developer471f6562021-05-10 20:48:34 +08001064#else
developerfd40db22021-04-29 10:08:25 +08001065#define NR_WHNAT_WDMA_PORT 3
developer471f6562021-05-10 20:48:34 +08001066#define NR_PPE0_PORT 4
1067#endif
developerfd40db22021-04-29 10:08:25 +08001068#define NR_QDMA_PORT 5
1069#define NR_DISCARD 7
1070#define NR_WDMA0_PORT 8
1071#define NR_WDMA1_PORT 9
developerd35bbcc2022-09-28 22:46:01 +08001072#define NR_GMAC3_PORT 15
developerfd40db22021-04-29 10:08:25 +08001073#define LAN_DEV_NAME hnat_priv->lan
developerd35bbcc2022-09-28 22:46:01 +08001074#define LAN2_DEV_NAME hnat_priv->lan2
developerfd40db22021-04-29 10:08:25 +08001075#define IS_WAN(dev) \
1076 (!strncmp((dev)->name, hnat_priv->wan, strlen(hnat_priv->wan)))
developerd35bbcc2022-09-28 22:46:01 +08001077#define IS_LAN_GRP(dev) (IS_LAN(dev) | IS_LAN2(dev))
developerfd40db22021-04-29 10:08:25 +08001078#define IS_LAN(dev) (!strncmp(dev->name, LAN_DEV_NAME, strlen(LAN_DEV_NAME)))
developerd35bbcc2022-09-28 22:46:01 +08001079#define IS_LAN2(dev) (!strncmp(dev->name, LAN2_DEV_NAME, \
1080 strlen(LAN2_DEV_NAME)))
developerfd40db22021-04-29 10:08:25 +08001081#define IS_BR(dev) (!strncmp(dev->name, "br", 2))
1082#define IS_WHNAT(dev) \
1083 ((hnat_priv->data->whnat && \
1084 (get_wifi_hook_if_index_from_dev(dev) != 0)) ? 1 : 0)
1085#define IS_EXT(dev) ((get_index_from_dev(dev) != 0) ? 1 : 0)
1086#define IS_PPD(dev) (!strcmp(dev->name, hnat_priv->ppd))
1087#define IS_IPV4_HNAPT(x) (((x)->bfib1.pkt_type == IPV4_HNAPT) ? 1 : 0)
1088#define IS_IPV4_HNAT(x) (((x)->bfib1.pkt_type == IPV4_HNAT) ? 1 : 0)
1089#define IS_IPV4_GRP(x) (IS_IPV4_HNAPT(x) | IS_IPV4_HNAT(x))
1090#define IS_IPV4_DSLITE(x) (((x)->bfib1.pkt_type == IPV4_DSLITE) ? 1 : 0)
1091#define IS_IPV4_MAPE(x) (((x)->bfib1.pkt_type == IPV4_MAP_E) ? 1 : 0)
1092#define IS_IPV4_MAPT(x) (((x)->bfib1.pkt_type == IPV4_MAP_T) ? 1 : 0)
1093#define IS_IPV6_3T_ROUTE(x) (((x)->bfib1.pkt_type == IPV6_3T_ROUTE) ? 1 : 0)
1094#define IS_IPV6_5T_ROUTE(x) (((x)->bfib1.pkt_type == IPV6_5T_ROUTE) ? 1 : 0)
1095#define IS_IPV6_6RD(x) (((x)->bfib1.pkt_type == IPV6_6RD) ? 1 : 0)
developer5ffc5f12022-10-25 18:51:46 +08001096#define IS_IPV6_HNAPT(x) (((x)->bfib1.pkt_type == IPV6_HNAPT) ? 1 : 0)
1097#define IS_IPV6_HNAT(x) (((x)->bfib1.pkt_type == IPV6_HNAT) ? 1 : 0)
developerfd40db22021-04-29 10:08:25 +08001098#define IS_IPV6_GRP(x) \
1099 (IS_IPV6_3T_ROUTE(x) | IS_IPV6_5T_ROUTE(x) | IS_IPV6_6RD(x) | \
developer5ffc5f12022-10-25 18:51:46 +08001100 IS_IPV4_DSLITE(x) | IS_IPV4_MAPE(x) | IS_IPV4_MAPT(x) | \
1101 IS_IPV6_HNAPT(x) | IS_IPV6_HNAT(x))
developerfd40db22021-04-29 10:08:25 +08001102#define IS_BOND_MODE (!strncmp(LAN_DEV_NAME, "bond", 4))
1103#define IS_GMAC1_MODE ((hnat_priv->gmac_num == 1) ? 1 : 0)
developeraf07fad2021-11-19 17:53:42 +08001104#define IS_HQOS_MODE (qos_toggle == 1)
1105#define IS_PPPQ_MODE (qos_toggle == 2) /* Per Port Per Queue */
developer934756a2022-11-18 14:51:34 +08001106#define IS_PPPQ_PATH(dev, skb) \
1107 ((IS_DSA_1G_LAN(dev) || IS_DSA_WAN(dev)) || \
1108 (FROM_WED(skb) && IS_DSA_LAN(dev)))
developer47545a32022-11-15 16:06:58 +08001109#define IS_HQOS_DL_MODE (IS_HQOS_MODE && qos_dl_toggle)
1110#define IS_HQOS_UL_MODE (IS_HQOS_MODE && qos_ul_toggle)
developer70cdf6e2021-12-07 18:58:35 +08001111#define MAX_PPPQ_PORT_NUM 6
developerfd40db22021-04-29 10:08:25 +08001112
1113#define es(entry) (entry_state[entry->bfib1.state])
1114#define ei(entry, end) (hnat_priv->foe_etry_num - (int)(end - entry))
1115#define pt(entry) (packet_type[entry->ipv4_hnapt.bfib1.pkt_type])
1116#define ipv4_smac(mac, e) \
1117 ({ \
1118 mac[0] = e->ipv4_hnapt.smac_hi[3]; \
1119 mac[1] = e->ipv4_hnapt.smac_hi[2]; \
1120 mac[2] = e->ipv4_hnapt.smac_hi[1]; \
1121 mac[3] = e->ipv4_hnapt.smac_hi[0]; \
1122 mac[4] = e->ipv4_hnapt.smac_lo[1]; \
1123 mac[5] = e->ipv4_hnapt.smac_lo[0]; \
1124 })
1125#define ipv4_dmac(mac, e) \
1126 ({ \
1127 mac[0] = e->ipv4_hnapt.dmac_hi[3]; \
1128 mac[1] = e->ipv4_hnapt.dmac_hi[2]; \
1129 mac[2] = e->ipv4_hnapt.dmac_hi[1]; \
1130 mac[3] = e->ipv4_hnapt.dmac_hi[0]; \
1131 mac[4] = e->ipv4_hnapt.dmac_lo[1]; \
1132 mac[5] = e->ipv4_hnapt.dmac_lo[0]; \
1133 })
1134
1135#define IS_DSA_LAN(dev) (!strncmp(dev->name, "lan", 3))
developer399ec072022-06-24 16:07:41 +08001136#define IS_DSA_1G_LAN(dev) (!strncmp(dev->name, "lan", 3) && \
1137 strcmp(dev->name, "lan5"))
developerfd40db22021-04-29 10:08:25 +08001138#define IS_DSA_WAN(dev) (!strncmp(dev->name, "wan", 3))
1139#define NONE_DSA_PORT 0xff
1140#define MAX_CRSN_NUM 32
1141#define IPV6_HDR_LEN 40
developer5ffc5f12022-10-25 18:51:46 +08001142#define IPV6_SNAT 0
1143#define IPV6_DNAT 1
developerfd40db22021-04-29 10:08:25 +08001144
1145/*QDMA_PAGE value*/
1146#define NUM_OF_Q_PER_PAGE 16
1147
1148/*IPv6 Header*/
1149#ifndef NEXTHDR_IPIP
1150#define NEXTHDR_IPIP 4
1151#endif
1152
1153extern const struct of_device_id of_hnat_match[];
1154extern struct mtk_hnat *hnat_priv;
1155
1156#if defined(CONFIG_NET_DSA_MT7530)
developeraf07fad2021-11-19 17:53:42 +08001157u32 hnat_dsa_fill_stag(const struct net_device *netdev,
1158 struct foe_entry *entry,
1159 struct flow_offload_hw_path *hw_path,
1160 u16 eth_proto, int mape);
developerfd40db22021-04-29 10:08:25 +08001161
1162static inline bool hnat_dsa_is_enable(struct mtk_hnat *priv)
1163{
1164 return (priv->wan_dsa_port != NONE_DSA_PORT);
1165}
1166#else
developeraf07fad2021-11-19 17:53:42 +08001167static inline u32 hnat_dsa_fill_stag(const struct net_device *netdev,
1168 struct foe_entry *entry,
1169 struct flow_offload_hw_path *hw_path,
1170 u16 eth_proto, int mape)
developerfd40db22021-04-29 10:08:25 +08001171{
developerd35bbcc2022-09-28 22:46:01 +08001172 return 0;
developerfd40db22021-04-29 10:08:25 +08001173}
1174
1175static inline bool hnat_dsa_is_enable(struct mtk_hnat *priv)
1176{
1177 return false;
1178}
1179#endif
1180
1181void hnat_deinit_debugfs(struct mtk_hnat *h);
1182int hnat_init_debugfs(struct mtk_hnat *h);
1183int hnat_register_nf_hooks(void);
1184void hnat_unregister_nf_hooks(void);
1185int whnat_adjust_nf_hooks(void);
1186int mtk_hqos_ptype_cb(struct sk_buff *skb, struct net_device *dev,
1187 struct packet_type *pt, struct net_device *unused);
1188extern int dbg_cpu_reason;
1189extern int debug_level;
developer47545a32022-11-15 16:06:58 +08001190extern int qos_dl_toggle;
1191extern int qos_ul_toggle;
developerfd40db22021-04-29 10:08:25 +08001192extern int hook_toggle;
1193extern int mape_toggle;
developeraf07fad2021-11-19 17:53:42 +08001194extern int qos_toggle;
developerfd40db22021-04-29 10:08:25 +08001195
1196int ext_if_add(struct extdev_entry *ext_entry);
1197int ext_if_del(struct extdev_entry *ext_entry);
1198void cr_set_field(void __iomem *reg, u32 field, u32 val);
1199int mtk_sw_nat_hook_tx(struct sk_buff *skb, int gmac_no);
1200int mtk_sw_nat_hook_rx(struct sk_buff *skb);
1201void mtk_ppe_dev_register_hook(struct net_device *dev);
1202void mtk_ppe_dev_unregister_hook(struct net_device *dev);
1203int nf_hnat_netdevice_event(struct notifier_block *unused, unsigned long event,
1204 void *ptr);
1205int nf_hnat_netevent_handler(struct notifier_block *unused, unsigned long event,
1206 void *ptr);
1207uint32_t foe_dump_pkt(struct sk_buff *skb);
1208uint32_t hnat_cpu_reason_cnt(struct sk_buff *skb);
1209int hnat_enable_hook(void);
1210int hnat_disable_hook(void);
1211void hnat_cache_ebl(int enable);
developer70cdf6e2021-12-07 18:58:35 +08001212void hnat_qos_shaper_ebl(u32 id, u32 enable);
developerfd40db22021-04-29 10:08:25 +08001213void set_gmac_ppe_fwd(int gmac_no, int enable);
developer4c32b7a2021-11-13 16:46:43 +08001214int entry_detail(u32 ppe_id, int index);
developer731b98f2021-09-17 17:44:37 +08001215int entry_delete_by_mac(u8 *mac);
developer4c32b7a2021-11-13 16:46:43 +08001216int entry_delete(u32 ppe_id, int index);
developer8051e042022-04-08 13:26:36 +08001217int hnat_warm_init(void);
1218
developer4c32b7a2021-11-13 16:46:43 +08001219struct hnat_accounting *hnat_get_count(struct mtk_hnat *h, u32 ppe_id,
developer30a47682021-11-02 17:06:14 +08001220 u32 index, struct hnat_accounting *diff);
developerfd40db22021-04-29 10:08:25 +08001221
1222static inline u16 foe_timestamp(struct mtk_hnat *h)
1223{
1224 return (readl(hnat_priv->fe_base + 0x0010)) & 0xffff;
1225}