developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2018 MediaTek Inc. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License as published by |
| 6 | * the Free Software Foundation; version 2 of the License |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | * |
| 13 | * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> |
| 14 | * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> |
| 15 | * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> |
| 16 | */ |
| 17 | |
| 18 | #ifndef MTK_ETH_DBG_H |
| 19 | #define MTK_ETH_DBG_H |
| 20 | |
| 21 | /* Debug Purpose Register */ |
| 22 | #define MTK_PSE_FQFC_CFG 0x100 |
| 23 | #define MTK_FE_CDM1_FSM 0x220 |
| 24 | #define MTK_FE_CDM2_FSM 0x224 |
developer | 77f3fd4 | 2021-10-05 15:16:05 +0800 | [diff] [blame] | 25 | #define MTK_FE_CDM3_FSM 0x238 |
| 26 | #define MTK_FE_CDM4_FSM 0x298 |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 27 | #define MTK_FE_CDM5_FSM 0x318 |
| 28 | #define MTK_FE_CDM6_FSM 0x328 |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 29 | #define MTK_FE_GDM1_FSM 0x228 |
| 30 | #define MTK_FE_GDM2_FSM 0x22C |
developer | a7570e7 | 2023-05-09 17:06:42 +0800 | [diff] [blame] | 31 | #define MTK_FE_GDM3_FSM 0x23C |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 32 | #define MTK_FE_PSE_FREE 0x240 |
| 33 | #define MTK_FE_DROP_FQ 0x244 |
| 34 | #define MTK_FE_DROP_FC 0x248 |
| 35 | #define MTK_FE_DROP_PPE 0x24C |
developer | 77f3fd4 | 2021-10-05 15:16:05 +0800 | [diff] [blame] | 36 | #define MTK_MAC_FSM(x) (0x1010C + ((x) * 0x100)) |
| 37 | #define MTK_SGMII_FALSE_CARRIER_CNT(x) (0x10060028 + ((x) * 0x10000)) |
| 38 | #define MTK_SGMII_EFUSE 0x11D008C8 |
| 39 | #define MTK_WED_RTQM_GLO_CFG 0x15010B00 |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 40 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 41 | #if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 42 | #define MTK_PSE_IQ_STA(x) (0x180 + (x) * 0x4) |
| 43 | #define MTK_PSE_OQ_STA(x) (0x1A0 + (x) * 0x4) |
| 44 | #else |
| 45 | #define MTK_PSE_IQ_STA(x) (0x110 + (x) * 0x4) |
| 46 | #define MTK_PSE_OQ_STA(x) (0x118 + (x) * 0x4) |
| 47 | #endif |
| 48 | |
| 49 | #define MTKETH_MII_READ 0x89F3 |
| 50 | #define MTKETH_MII_WRITE 0x89F4 |
| 51 | #define MTKETH_ESW_REG_READ 0x89F1 |
| 52 | #define MTKETH_ESW_REG_WRITE 0x89F2 |
| 53 | #define MTKETH_MII_READ_CL45 0x89FC |
| 54 | #define MTKETH_MII_WRITE_CL45 0x89FD |
| 55 | #define REG_ESW_MAX 0xFC |
| 56 | |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 57 | #define PROCREG_ESW_CNT "esw_cnt" |
developer | 621ca6b | 2023-01-11 11:08:46 +0800 | [diff] [blame] | 58 | #define PROCREG_XFI_CNT "xfi_cnt" |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 59 | #define PROCREG_TXRING "tx_ring" |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 60 | #define PROCREG_HWTXRING "hwtx_ring" |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 61 | #define PROCREG_RXRING "rx_ring" |
| 62 | #define PROCREG_DIR "mtketh" |
| 63 | #define PROCREG_DBG_REGS "dbg_regs" |
developer | e3d0de2 | 2023-05-30 17:45:00 +0800 | [diff] [blame^] | 64 | #define PROCREG_RSS_CTRL "rss_ctrl" |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 65 | #define PROCREG_HW_LRO_STATS "hw_lro_stats" |
| 66 | #define PROCREG_HW_LRO_AUTO_TLB "hw_lro_auto_tlb" |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 67 | #define PROCREG_RESET_EVENT "reset_event" |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 68 | |
developer | 621ca6b | 2023-01-11 11:08:46 +0800 | [diff] [blame] | 69 | /* XFI MAC MIB Register */ |
| 70 | #define MTK_XFI_MIB_BASE(x) (MTK_XMAC_MCR(x)) |
| 71 | #define MTK_XFI_CNT_CTRL 0x100 |
| 72 | #define MTK_XFI_TX_PKT_CNT 0x108 |
| 73 | #define MTK_XFI_TX_ETH_CNT 0x114 |
| 74 | #define MTK_XFI_TX_PAUSE_CNT 0x120 |
| 75 | #define MTK_XFI_TX_BYTE_CNT 0x134 |
| 76 | #define MTK_XFI_TX_UC_PKT_CNT_L 0x150 |
| 77 | #define MTK_XFI_TX_UC_PKT_CNT_H 0x154 |
| 78 | #define MTK_XFI_TX_MC_PKT_CNT_L 0x160 |
| 79 | #define MTK_XFI_TX_MC_PKT_CNT_H 0x164 |
| 80 | #define MTK_XFI_TX_BC_PKT_CNT_L 0x170 |
| 81 | #define MTK_XFI_TX_BC_PKT_CNT_H 0x174 |
| 82 | |
| 83 | #define MTK_XFI_RX_PKT_CNT 0x188 |
| 84 | #define MTK_XFI_RX_ETH_CNT 0x18C |
| 85 | #define MTK_XFI_RX_PAUSE_CNT 0x190 |
| 86 | #define MTK_XFI_RX_LEN_ERR_CNT 0x194 |
| 87 | #define MTK_XFI_RX_CRC_ERR_CNT 0x198 |
| 88 | #define MTK_XFI_RX_UC_PKT_CNT_L 0x1C0 |
| 89 | #define MTK_XFI_RX_UC_PKT_CNT_H 0x1C4 |
| 90 | #define MTK_XFI_RX_MC_PKT_CNT_L 0x1D0 |
| 91 | #define MTK_XFI_RX_MC_PKT_CNT_H 0x1D4 |
| 92 | #define MTK_XFI_RX_BC_PKT_CNT_L 0x1E0 |
| 93 | #define MTK_XFI_RX_BC_PKT_CNT_H 0x1E4 |
| 94 | #define MTK_XFI_RX_UC_DROP_CNT 0x200 |
| 95 | #define MTK_XFI_RX_BC_DROP_CNT 0x204 |
| 96 | #define MTK_XFI_RX_MC_DROP_CNT 0x208 |
| 97 | #define MTK_XFI_RX_ALL_DROP_CNT 0x20C |
| 98 | |
| 99 | #define PRINT_FORMATTED_XFI_MIB(seq, reg, mask) \ |
| 100 | { \ |
| 101 | seq_printf(seq, "| XFI%d_%s : %010lu |\n", \ |
| 102 | gdm_id, #reg, \ |
| 103 | FIELD_GET(mask, mtk_r32(eth, \ |
| 104 | MTK_XFI_MIB_BASE(gdm_id) + \ |
| 105 | MTK_XFI_##reg))); \ |
| 106 | } |
| 107 | |
| 108 | #define PRINT_FORMATTED_XFI_MIB64(seq, reg) \ |
| 109 | { \ |
| 110 | seq_printf(seq, "| XFI%d_%s : %010llu |\n", \ |
| 111 | gdm_id, #reg, \ |
| 112 | mtk_r32(eth, MTK_XFI_MIB_BASE(gdm_id) + \ |
| 113 | MTK_XFI_##reg##_L) + \ |
| 114 | ((u64)mtk_r32(eth, MTK_XFI_MIB_BASE(gdm_id) +\ |
| 115 | MTK_XFI_##reg##_H) << 32)); \ |
| 116 | } |
| 117 | |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 118 | /* HW LRO flush reason */ |
| 119 | #define MTK_HW_LRO_AGG_FLUSH (1) |
| 120 | #define MTK_HW_LRO_AGE_FLUSH (2) |
| 121 | #define MTK_HW_LRO_NOT_IN_SEQ_FLUSH (3) |
| 122 | #define MTK_HW_LRO_TIMESTAMP_FLUSH (4) |
| 123 | #define MTK_HW_LRO_NON_RULE_FLUSH (5) |
| 124 | |
| 125 | #define SET_PDMA_RXRING_MAX_AGG_CNT(eth, x, y) \ |
| 126 | { \ |
| 127 | u32 reg_val1 = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(x)); \ |
| 128 | u32 reg_val2 = mtk_r32(eth, MTK_LRO_CTRL_DW3_CFG(x)); \ |
| 129 | reg_val1 &= ~MTK_LRO_RING_AGG_CNT_L_MASK; \ |
| 130 | reg_val2 &= ~MTK_LRO_RING_AGG_CNT_H_MASK; \ |
| 131 | reg_val1 |= ((y) & 0x3f) << MTK_LRO_RING_AGG_CNT_L_OFFSET; \ |
| 132 | reg_val2 |= (((y) >> 6) & 0x03) << \ |
| 133 | MTK_LRO_RING_AGG_CNT_H_OFFSET; \ |
| 134 | mtk_w32(eth, reg_val1, MTK_LRO_CTRL_DW2_CFG(x)); \ |
| 135 | mtk_w32(eth, reg_val2, MTK_LRO_CTRL_DW3_CFG(x)); \ |
| 136 | } |
| 137 | |
| 138 | #define SET_PDMA_RXRING_AGG_TIME(eth, x, y) \ |
| 139 | { \ |
| 140 | u32 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(x)); \ |
| 141 | reg_val &= ~MTK_LRO_RING_AGG_TIME_MASK; \ |
| 142 | reg_val |= ((y) & 0xffff) << MTK_LRO_RING_AGG_TIME_OFFSET; \ |
| 143 | mtk_w32(eth, reg_val, MTK_LRO_CTRL_DW2_CFG(x)); \ |
| 144 | } |
| 145 | |
| 146 | #define SET_PDMA_RXRING_AGE_TIME(eth, x, y) \ |
| 147 | { \ |
| 148 | u32 reg_val1 = mtk_r32(eth, MTK_LRO_CTRL_DW1_CFG(x)); \ |
| 149 | u32 reg_val2 = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(x)); \ |
| 150 | reg_val1 &= ~MTK_LRO_RING_AGE_TIME_L_MASK; \ |
| 151 | reg_val2 &= ~MTK_LRO_RING_AGE_TIME_H_MASK; \ |
| 152 | reg_val1 |= ((y) & 0x3ff) << MTK_LRO_RING_AGE_TIME_L_OFFSET; \ |
| 153 | reg_val2 |= (((y) >> 10) & 0x03f) << \ |
| 154 | MTK_LRO_RING_AGE_TIME_H_OFFSET; \ |
| 155 | mtk_w32(eth, reg_val1, MTK_LRO_CTRL_DW1_CFG(x)); \ |
| 156 | mtk_w32(eth, reg_val2, MTK_LRO_CTRL_DW2_CFG(x)); \ |
| 157 | } |
| 158 | |
| 159 | #define SET_PDMA_LRO_BW_THRESHOLD(eth, x) \ |
| 160 | { \ |
| 161 | u32 reg_val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW2); \ |
| 162 | reg_val = (x); \ |
| 163 | mtk_w32(eth, reg_val, MTK_PDMA_LRO_CTRL_DW2); \ |
| 164 | } |
| 165 | |
| 166 | #define SET_PDMA_RXRING_VALID(eth, x, y) \ |
| 167 | { \ |
| 168 | u32 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(x)); \ |
| 169 | reg_val &= ~(0x1 << MTK_RX_PORT_VALID_OFFSET); \ |
| 170 | reg_val |= ((y) & 0x1) << MTK_RX_PORT_VALID_OFFSET; \ |
| 171 | mtk_w32(eth, reg_val, MTK_LRO_CTRL_DW2_CFG(x)); \ |
| 172 | } |
| 173 | |
| 174 | struct mtk_lro_alt_v1_info0 { |
| 175 | u32 dtp : 16; |
| 176 | u32 stp : 16; |
| 177 | }; |
| 178 | |
| 179 | struct mtk_lro_alt_v1_info1 { |
| 180 | u32 sip0 : 32; |
| 181 | }; |
| 182 | |
| 183 | struct mtk_lro_alt_v1_info2 { |
| 184 | u32 sip1 : 32; |
| 185 | }; |
| 186 | |
| 187 | struct mtk_lro_alt_v1_info3 { |
| 188 | u32 sip2 : 32; |
| 189 | }; |
| 190 | |
| 191 | struct mtk_lro_alt_v1_info4 { |
| 192 | u32 sip3 : 32; |
| 193 | }; |
| 194 | |
| 195 | struct mtk_lro_alt_v1_info5 { |
| 196 | u32 vlan_vid0 : 32; |
| 197 | }; |
| 198 | |
| 199 | struct mtk_lro_alt_v1_info6 { |
| 200 | u32 vlan_vid1 : 16; |
| 201 | u32 vlan_vid_vld : 4; |
| 202 | u32 cnt : 12; |
| 203 | }; |
| 204 | |
| 205 | struct mtk_lro_alt_v1_info7 { |
| 206 | u32 dw_len : 32; |
| 207 | }; |
| 208 | |
| 209 | struct mtk_lro_alt_v1_info8 { |
| 210 | u32 dip_id : 2; |
| 211 | u32 ipv6 : 1; |
| 212 | u32 ipv4 : 1; |
| 213 | u32 resv : 27; |
| 214 | u32 valid : 1; |
| 215 | }; |
| 216 | |
| 217 | struct mtk_lro_alt_v1 { |
| 218 | struct mtk_lro_alt_v1_info0 alt_info0; |
| 219 | struct mtk_lro_alt_v1_info1 alt_info1; |
| 220 | struct mtk_lro_alt_v1_info2 alt_info2; |
| 221 | struct mtk_lro_alt_v1_info3 alt_info3; |
| 222 | struct mtk_lro_alt_v1_info4 alt_info4; |
| 223 | struct mtk_lro_alt_v1_info5 alt_info5; |
| 224 | struct mtk_lro_alt_v1_info6 alt_info6; |
| 225 | struct mtk_lro_alt_v1_info7 alt_info7; |
| 226 | struct mtk_lro_alt_v1_info8 alt_info8; |
| 227 | }; |
| 228 | |
| 229 | struct mtk_lro_alt_v2_info0 { |
| 230 | u32 v2_id_h:3; |
| 231 | u32 v1_id:12; |
| 232 | u32 v0_id:12; |
| 233 | u32 v3_valid:1; |
| 234 | u32 v2_valid:1; |
| 235 | u32 v1_valid:1; |
| 236 | u32 v0_valid:1; |
| 237 | u32 valid:1; |
| 238 | }; |
| 239 | |
| 240 | struct mtk_lro_alt_v2_info1 { |
| 241 | u32 sip3_h:9; |
| 242 | u32 v6_valid:1; |
| 243 | u32 v4_valid:1; |
| 244 | u32 v3_id:12; |
| 245 | u32 v2_id_l:9; |
| 246 | }; |
| 247 | |
| 248 | struct mtk_lro_alt_v2_info2 { |
| 249 | u32 sip2_h:9; |
| 250 | u32 sip3_l:23; |
| 251 | }; |
| 252 | struct mtk_lro_alt_v2_info3 { |
| 253 | u32 sip1_h:9; |
| 254 | u32 sip2_l:23; |
| 255 | }; |
| 256 | struct mtk_lro_alt_v2_info4 { |
| 257 | u32 sip0_h:9; |
| 258 | u32 sip1_l:23; |
| 259 | }; |
| 260 | struct mtk_lro_alt_v2_info5 { |
| 261 | u32 dip3_h:9; |
| 262 | u32 sip0_l:23; |
| 263 | }; |
| 264 | struct mtk_lro_alt_v2_info6 { |
| 265 | u32 dip2_h:9; |
| 266 | u32 dip3_l:23; |
| 267 | }; |
| 268 | struct mtk_lro_alt_v2_info7 { |
| 269 | u32 dip1_h:9; |
| 270 | u32 dip2_l:23; |
| 271 | }; |
| 272 | struct mtk_lro_alt_v2_info8 { |
| 273 | u32 dip0_h:9; |
| 274 | u32 dip1_l:23; |
| 275 | }; |
| 276 | struct mtk_lro_alt_v2_info9 { |
| 277 | u32 sp_h:9; |
| 278 | u32 dip0_l:23; |
| 279 | }; |
| 280 | struct mtk_lro_alt_v2_info10 { |
| 281 | u32 resv:9; |
| 282 | u32 dp:16; |
| 283 | u32 sp_l:7; |
| 284 | }; |
| 285 | |
| 286 | struct mtk_lro_alt_v2 { |
| 287 | struct mtk_lro_alt_v2_info0 alt_info0; |
| 288 | struct mtk_lro_alt_v2_info1 alt_info1; |
| 289 | struct mtk_lro_alt_v2_info2 alt_info2; |
| 290 | struct mtk_lro_alt_v2_info3 alt_info3; |
| 291 | struct mtk_lro_alt_v2_info4 alt_info4; |
| 292 | struct mtk_lro_alt_v2_info5 alt_info5; |
| 293 | struct mtk_lro_alt_v2_info6 alt_info6; |
| 294 | struct mtk_lro_alt_v2_info7 alt_info7; |
| 295 | struct mtk_lro_alt_v2_info8 alt_info8; |
| 296 | struct mtk_lro_alt_v2_info9 alt_info9; |
| 297 | struct mtk_lro_alt_v2_info10 alt_info10; |
| 298 | }; |
| 299 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 300 | struct mtk_esw_reg { |
| 301 | unsigned int off; |
| 302 | unsigned int val; |
| 303 | }; |
| 304 | |
| 305 | struct mtk_mii_ioctl_data { |
developer | 3957a91 | 2021-05-13 16:44:31 +0800 | [diff] [blame] | 306 | u16 phy_id; |
| 307 | u16 reg_num; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 308 | unsigned int val_in; |
| 309 | unsigned int val_out; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 310 | }; |
| 311 | |
| 312 | #if defined(CONFIG_NET_DSA_MT7530) || defined(CONFIG_MT753X_GSW) |
| 313 | static inline bool mt7530_exist(struct mtk_eth *eth) |
| 314 | { |
| 315 | return true; |
| 316 | } |
| 317 | #else |
| 318 | static inline bool mt7530_exist(struct mtk_eth *eth) |
| 319 | { |
| 320 | return false; |
| 321 | } |
| 322 | #endif |
| 323 | |
developer | 599cda4 | 2022-05-24 15:13:31 +0800 | [diff] [blame] | 324 | extern u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg); |
| 325 | extern u32 _mtk_mdio_write(struct mtk_eth *eth, int phy_addr, |
| 326 | int phy_reg, u16 write_data); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 327 | |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 328 | extern atomic_t force; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 329 | |
| 330 | int debug_proc_init(struct mtk_eth *eth); |
| 331 | void debug_proc_exit(void); |
| 332 | |
| 333 | int mtketh_debugfs_init(struct mtk_eth *eth); |
| 334 | void mtketh_debugfs_exit(struct mtk_eth *eth); |
| 335 | int mtk_do_priv_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd); |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 336 | void hw_lro_stats_update(u32 ring_no, struct mtk_rx_dma_v2 *rxd); |
| 337 | void hw_lro_flush_stats_update(u32 ring_no, struct mtk_rx_dma_v2 *rxd); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 338 | |
| 339 | #endif /* MTK_ETH_DBG_H */ |