| developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (C) 2018 MediaTek Inc. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License as published by |
| 6 | * the Free Software Foundation; version 2 of the License |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | * |
| 13 | * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> |
| 14 | * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> |
| 15 | * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> |
| 16 | */ |
| 17 | |
| 18 | #ifndef MTK_ETH_DBG_H |
| 19 | #define MTK_ETH_DBG_H |
| 20 | |
| 21 | /* Debug Purpose Register */ |
| 22 | #define MTK_PSE_FQFC_CFG 0x100 |
| 23 | #define MTK_FE_CDM1_FSM 0x220 |
| 24 | #define MTK_FE_CDM2_FSM 0x224 |
| 25 | #define MTK_FE_GDM1_FSM 0x228 |
| 26 | #define MTK_FE_GDM2_FSM 0x22C |
| 27 | #define MTK_FE_PSE_FREE 0x240 |
| 28 | #define MTK_FE_DROP_FQ 0x244 |
| 29 | #define MTK_FE_DROP_FC 0x248 |
| 30 | #define MTK_FE_DROP_PPE 0x24C |
| 31 | |
| 32 | #if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 33 | #define MTK_PSE_IQ_STA(x) (0x180 + (x) * 0x4) |
| 34 | #define MTK_PSE_OQ_STA(x) (0x1A0 + (x) * 0x4) |
| 35 | #else |
| 36 | #define MTK_PSE_IQ_STA(x) (0x110 + (x) * 0x4) |
| 37 | #define MTK_PSE_OQ_STA(x) (0x118 + (x) * 0x4) |
| 38 | #endif |
| 39 | |
| 40 | #define MTKETH_MII_READ 0x89F3 |
| 41 | #define MTKETH_MII_WRITE 0x89F4 |
| 42 | #define MTKETH_ESW_REG_READ 0x89F1 |
| 43 | #define MTKETH_ESW_REG_WRITE 0x89F2 |
| 44 | #define MTKETH_MII_READ_CL45 0x89FC |
| 45 | #define MTKETH_MII_WRITE_CL45 0x89FD |
| 46 | #define REG_ESW_MAX 0xFC |
| 47 | |
| 48 | struct mtk_esw_reg { |
| 49 | unsigned int off; |
| 50 | unsigned int val; |
| 51 | }; |
| 52 | |
| 53 | struct mtk_mii_ioctl_data { |
| 54 | unsigned int phy_id; |
| 55 | unsigned int reg_num; |
| 56 | unsigned int val_in; |
| 57 | unsigned int val_out; |
| 58 | unsigned int port_num; |
| 59 | unsigned int dev_addr; |
| 60 | unsigned int reg_addr; |
| 61 | }; |
| 62 | |
| 63 | #if defined(CONFIG_NET_DSA_MT7530) || defined(CONFIG_MT753X_GSW) |
| 64 | static inline bool mt7530_exist(struct mtk_eth *eth) |
| 65 | { |
| 66 | return true; |
| 67 | } |
| 68 | #else |
| 69 | static inline bool mt7530_exist(struct mtk_eth *eth) |
| 70 | { |
| 71 | return false; |
| 72 | } |
| 73 | #endif |
| 74 | |
| 75 | extern u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg); |
| 76 | extern u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr, |
| 77 | u32 phy_register, u32 write_data); |
| 78 | |
| 79 | extern u32 mtk_cl45_ind_read(struct mtk_eth *eth, u32 port, u32 devad, u32 reg, u32 *data); |
| 80 | extern u32 mtk_cl45_ind_write(struct mtk_eth *eth, u32 port, u32 devad, u32 reg, u32 data); |
| 81 | |
| 82 | int debug_proc_init(struct mtk_eth *eth); |
| 83 | void debug_proc_exit(void); |
| 84 | |
| 85 | int mtketh_debugfs_init(struct mtk_eth *eth); |
| 86 | void mtketh_debugfs_exit(struct mtk_eth *eth); |
| 87 | int mtk_do_priv_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd); |
| 88 | |
| 89 | #endif /* MTK_ETH_DBG_H */ |