blob: 49bb3f545bc6d58b8af6777363a32c92dcb61b4a [file] [log] [blame]
developerfd40db22021-04-29 10:08:25 +08001/dts-v1/;
2#include "mt7986a.dtsi"
3/ {
4 model = "MediaTek MT7986a RFB";
5 compatible = "mediatek,mt7986a-rfb";
6 chosen {
7 bootargs = "console=ttyS0,115200n1 loglevel=8 \
8 earlycon=uart8250,mmio32,0x11002000";
9 };
10
11 memory {
developerfd40db22021-04-29 10:08:25 +080012 reg = <0 0x40000000 0 0x10000000>;
13 };
developerc20f3452021-05-26 17:27:35 +080014
15 nmbm_snfi {
16 compatible = "generic,nmbm";
17
18 #address-cells = <1>;
19 #size-cells = <1>;
20
21 lower-mtd-device = <&snand>;
22 forced-create;
developerc9faf4a2021-06-17 09:22:21 +080023 empty-page-ecc-protected;
developerc20f3452021-05-26 17:27:35 +080024
25 partitions {
26 compatible = "fixed-partitions";
27 #address-cells = <1>;
28 #size-cells = <1>;
29
30 partition@0 {
31 label = "BL2";
32 reg = <0x00000 0x0100000>;
33 read-only;
34 };
35
36 partition@100000 {
37 label = "u-boot-env";
38 reg = <0x0100000 0x0080000>;
39 };
40
41 partition@180000 {
42 label = "Factory";
43 reg = <0x180000 0x0200000>;
44 };
45
46 partition@380000 {
47 label = "FIP";
48 reg = <0x380000 0x0200000>;
49 };
50
51 partition@580000 {
52 label = "ubi";
53 reg = <0x580000 0x4000000>;
54 };
55 };
56 };
developerfeac91e2021-06-02 09:46:12 +080057
developer86fc2a72021-06-23 17:30:23 +080058 nmbm_spim_nand {
59 compatible = "generic,nmbm";
60
61 #address-cells = <1>;
62 #size-cells = <1>;
63
64 lower-mtd-device = <&spi_nand>;
65 forced-create;
66
67 partitions {
68 compatible = "fixed-partitions";
69 #address-cells = <1>;
70 #size-cells = <1>;
71
72 partition@0 {
73 label = "BL2";
74 reg = <0x00000 0x0100000>;
75 read-only;
76 };
77
78 partition@100000 {
79 label = "u-boot-env";
80 reg = <0x0100000 0x0080000>;
81 };
82
83 partition@180000 {
84 label = "Factory";
85 reg = <0x180000 0x0200000>;
86 };
87
88 partition@380000 {
89 label = "FIP";
90 reg = <0x380000 0x0200000>;
91 };
92
93 partition@580000 {
94 label = "ubi";
95 reg = <0x580000 0x4000000>;
96 };
97 };
98 };
99
developerfeac91e2021-06-02 09:46:12 +0800100 reg_1p8v: regulator-1p8v {
101 compatible = "regulator-fixed";
102 regulator-name = "fixed-1.8V";
103 regulator-min-microvolt = <1800000>;
104 regulator-max-microvolt = <1800000>;
105 regulator-boot-on;
106 regulator-always-on;
107 };
108
109 reg_3p3v: regulator-3p3v {
110 compatible = "regulator-fixed";
111 regulator-name = "fixed-3.3V";
112 regulator-min-microvolt = <3300000>;
113 regulator-max-microvolt = <3300000>;
114 regulator-boot-on;
115 regulator-always-on;
116 };
developere1993bd2021-07-06 13:48:40 +0800117
118 sound {
119 compatible = "mediatek,mt7986-wm8960-machine";
120 mediatek,platform = <&afe>;
121 audio-routing = "Headphone", "HP_L",
122 "Headphone", "HP_R",
123 "LINPUT1", "AMIC",
124 "RINPUT1", "AMIC";
125 mediatek,audio-codec = <&wm8960>;
126 status = "okay";
127 };
developerfd40db22021-04-29 10:08:25 +0800128};
129
developer8b9f2852021-06-03 21:53:08 +0800130&pwm {
131 pinctrl-names = "default";
132 pinctrl-0 = <&pwm0_pin &pwm1_pin_g1>;
133 status = "okay";
134};
135
developerfd40db22021-04-29 10:08:25 +0800136&uart0 {
137 status = "okay";
138};
139
developer8b9f2852021-06-03 21:53:08 +0800140&uart1 {
141 pinctrl-names = "default";
142 pinctrl-0 = <&uart1_pins>;
143 status = "okay";
144};
145
146&uart2 {
147 pinctrl-names = "default";
148 pinctrl-0 = <&uart2_pins>;
149 status = "okay";
150};
151
152&i2c0 {
153 pinctrl-names = "default";
154 pinctrl-0 = <&i2c_pins>;
155 status = "okay";
developere1993bd2021-07-06 13:48:40 +0800156
157 wm8960: wm8960@1a {
158 compatible = "wlf,wm8960";
159 reg = <0x1a>;
160 };
developer8b9f2852021-06-03 21:53:08 +0800161};
162
163&auxadc {
164 status = "okay";
165};
166
developerfd40db22021-04-29 10:08:25 +0800167&watchdog {
168 status = "okay";
169};
170
171&eth {
172 status = "okay";
173
174 gmac0: mac@0 {
175 compatible = "mediatek,eth-mac";
176 reg = <0>;
177 phy-mode = "2500base-x";
178
179 fixed-link {
180 speed = <2500>;
181 full-duplex;
182 pause;
183 };
184 };
185
186 gmac1: mac@1 {
187 compatible = "mediatek,eth-mac";
188 reg = <1>;
189 phy-mode = "2500base-x";
190
191 fixed-link {
192 speed = <2500>;
193 full-duplex;
194 pause;
195 };
196 };
197
198 mdio: mdio-bus {
199 #address-cells = <1>;
200 #size-cells = <0>;
201
developerc0f3c7f2021-05-17 11:48:36 +0800202 phy5: phy@5 {
203 compatible = "ethernet-phy-id67c9.de0a";
204 reg = <5>;
205 reset-gpios = <&pio 6 1>;
206 reset-deassert-us = <20000>;
207 phy-mode = "2500base-x";
208 };
209
210 phy6: phy@6 {
211 compatible = "ethernet-phy-id67c9.de0a";
212 reg = <6>;
213 phy-mode = "2500base-x";
214 };
215
developerfd40db22021-04-29 10:08:25 +0800216 switch@0 {
217 compatible = "mediatek,mt7531";
developerc0f3c7f2021-05-17 11:48:36 +0800218 reg = <31>;
developer51059432021-05-03 16:01:06 +0800219 reset-gpios = <&pio 5 0>;
developerfd40db22021-04-29 10:08:25 +0800220
221 ports {
222 #address-cells = <1>;
223 #size-cells = <0>;
224
225 port@0 {
226 reg = <0>;
developerc0f3c7f2021-05-17 11:48:36 +0800227 label = "lan0";
developerfd40db22021-04-29 10:08:25 +0800228 };
229
230 port@1 {
231 reg = <1>;
developerc0f3c7f2021-05-17 11:48:36 +0800232 label = "lan1";
developerfd40db22021-04-29 10:08:25 +0800233 };
234
235 port@2 {
236 reg = <2>;
developerc0f3c7f2021-05-17 11:48:36 +0800237 label = "lan2";
developerfd40db22021-04-29 10:08:25 +0800238 };
239
240 port@3 {
241 reg = <3>;
developerc0f3c7f2021-05-17 11:48:36 +0800242 label = "lan3";
developerfd40db22021-04-29 10:08:25 +0800243 };
244
developerfd40db22021-04-29 10:08:25 +0800245 port@6 {
246 reg = <6>;
247 label = "cpu";
248 ethernet = <&gmac0>;
249 phy-mode = "2500base-x";
250
251 fixed-link {
252 speed = <2500>;
253 full-duplex;
254 pause;
255 };
256 };
257 };
258 };
259 };
260};
261
262&hnat {
developere5763512021-05-21 01:04:58 +0800263 mtketh-wan = "eth1";
developerd7edc132021-05-06 13:49:50 +0800264 mtketh-lan = "lan";
developerfd40db22021-04-29 10:08:25 +0800265 mtketh-max-gmac = <2>;
266 status = "okay";
267};
268
269&spi0 {
270 pinctrl-names = "default";
271 pinctrl-0 = <&spi_flash_pins>;
272 cs-gpios = <0>, <0>;
273 status = "okay";
274 spi_nor@0 {
275 #address-cells = <1>;
276 #size-cells = <1>;
277 compatible = "jedec,spi-nor";
278 reg = <0>;
279 spi-max-frequency = <20000000>;
280 spi-tx-buswidth = <4>;
281 spi-rx-buswidth = <4>;
282
283 partition@00000 {
284 label = "BL2";
285 reg = <0x00000 0x0040000>;
286 };
287 partition@40000 {
288 label = "u-boot-env";
289 reg = <0x40000 0x0010000>;
290 };
developer298705c2021-06-05 18:48:19 +0800291 factory: partition@50000 {
developerfd40db22021-04-29 10:08:25 +0800292 label = "Factory";
293 reg = <0x50000 0x00B0000>;
294 };
295 partition@100000 {
296 label = "FIP";
297 reg = <0x100000 0x0080000>;
298 };
299 partition@180000 {
300 label = "firmware";
301 reg = <0x180000 0xE00000>;
302 };
303 };
developer86fc2a72021-06-23 17:30:23 +0800304 spi_nand: spi_nand@1 {
developerfd40db22021-04-29 10:08:25 +0800305 #address-cells = <1>;
306 #size-cells = <1>;
307 compatible = "spi-nand";
308 reg = <1>;
309 spi-max-frequency = <20000000>;
310 spi-tx-buswidth = <4>;
311 spi-rx-buswidth = <4>;
developerfd40db22021-04-29 10:08:25 +0800312 };
313};
314
315&snand {
316 pinctrl-names = "default";
developerfd40db22021-04-29 10:08:25 +0800317 pinctrl-0 = <&snfi_pins>;
318 status = "okay";
319 mediatek,quad-spi;
320
321 partitions {
322 compatible = "fixed-partitions";
323 #address-cells = <1>;
324 #size-cells = <1>;
developerfd40db22021-04-29 10:08:25 +0800325 };
326};
327
328&spi1 {
329 pinctrl-names = "default";
developer8b9f2852021-06-03 21:53:08 +0800330 pinctrl-0 = <&spic_pins_g2>;
developerfd40db22021-04-29 10:08:25 +0800331 status = "okay";
332};
333
developer637f5552021-05-27 17:45:27 +0800334&mmc0 {
335 pinctrl-names = "default", "state_uhs";
336 pinctrl-0 = <&mmc0_pins_default>;
337 pinctrl-1 = <&mmc0_pins_uhs>;
338 bus-width = <8>;
339 max-frequency = <50000000>;
340 cap-mmc-highspeed;
341 mmc-hs200-1_8v;
342 vmmc-supply = <&reg_3p3v>;
343 vqmmc-supply = <&reg_1p8v>;
344 non-removable;
345 status = "okay";
346};
347
developerfd40db22021-04-29 10:08:25 +0800348&pio {
developer8b9f2852021-06-03 21:53:08 +0800349 wifi_led_pins: wifi_led-pins-1-2 {
developerfd40db22021-04-29 10:08:25 +0800350 mux {
developer8b9f2852021-06-03 21:53:08 +0800351 function = "led";
352 groups = "wifi_led";
353 };
354 };
355
356 i2c_pins: i2c-pins-3-4 {
357 mux {
358 function = "i2c";
359 groups = "i2c";
360 };
361 };
362
363 uart1_pins_g0: uart1-pins-7-to-10 {
364 mux {
365 function = "uart";
366 groups = "uart1_0";
367 };
368 };
369
370 jtag_pins: jtag-pins-11-to-14 {
371 mux {
372 function = "jtag";
373 groups = "jtag";
374 };
375 };
376
377 spic_pins_g0: spic-pins-11-to-14 {
378 mux {
379 function = "spi";
380 groups = "spi1_0";
381 };
382 };
383
384 pwm1_pin_g0: pwm1-pin-20 {
385 mux {
386 function = "pwm";
387 groups = "pwm1_1";
388 };
389 };
390
391 pwm0_pin: pwm0-pin-21 {
392 mux {
393 function = "pwm";
394 groups = "pwm0";
395 };
396 };
397
398 pwm1_pin_g1: pwm1-pin-22 {
399 mux {
400 function = "pwm";
401 groups = "pwm1_0";
402 };
403 };
404
405 spic_pins_g1: spic-pins-23-to-26 {
406 mux {
407 function = "spi";
408 groups = "spi1_1";
409 };
410 };
411
412 uart1_pins_g1: uart1-pins-23-to-26 {
413 mux {
414 function = "uart";
415 groups = "uart1_1";
developerfd40db22021-04-29 10:08:25 +0800416 };
417 };
418
developer8b9f2852021-06-03 21:53:08 +0800419 snfi_pins: snfi-pins-23-to-28 {
developerfd40db22021-04-29 10:08:25 +0800420 mux {
421 function = "flash";
422 groups = "snfi";
423 };
424 };
425
developer8b9f2852021-06-03 21:53:08 +0800426 spic_pins_g2: spic-pins-29-to-32 {
developerfd40db22021-04-29 10:08:25 +0800427 mux {
428 function = "spi";
developer19d22f62021-05-27 17:36:23 +0800429 groups = "spi1_2";
developerfd40db22021-04-29 10:08:25 +0800430 };
431 };
developer637f5552021-05-27 17:45:27 +0800432
developer8b9f2852021-06-03 21:53:08 +0800433 uart1_pins_g2: uart1-pins-29-to-32 {
434 mux {
435 function = "uart";
436 groups = "uart1_2";
437 };
438 };
439
440 uart2_pins_g0: uart1-pins-29-to-32 {
441 mux {
442 function = "uart";
443 groups = "uart1_2";
444 };
445 };
446
447 uart2_pins_g1: uart1-pins-23-to-36 {
448 mux {
449 function = "uart";
450 groups = "uart2_1";
451 };
452 };
453
454 spic_pins_g3: spic-pins-33-to-36 {
455 mux {
456 function = "spi";
457 groups = "spi1_3";
458 };
459 };
460
461 uart1_pins_g3: uart1-pins-35-to-38 {
462 mux {
463 function = "uart";
464 groups = "uart1_3_rx_tx", "uart1_3_cts_rts";
465 };
466 };
467
468 spi_flash_pins: spi-flash-pins-33-to-38 {
developer637f5552021-05-27 17:45:27 +0800469 mux {
470 function = "flash";
developer8b9f2852021-06-03 21:53:08 +0800471 groups = "spi0", "spi0_wp_hold";
472 };
473 };
474
475 uart1_pins: uart1-pins-42-to-45 {
476 mux {
477 function = "uart";
478 groups = "uart1";
479 };
480 };
481
482 uart2_pins: uart1-pins-46-to-49 {
483 mux {
484 function = "uart";
485 groups = "uart2";
486 };
487 };
488
489 mmc0_pins_default: mmc0-pins-50-to-61-default {
490 mux {
491 function = "flash";
developer637f5552021-05-27 17:45:27 +0800492 groups = "emmc_51";
493 };
494 };
495
developer8b9f2852021-06-03 21:53:08 +0800496 mmc0_pins_uhs: mmc0-pins-50-to-61-uhs {
developer637f5552021-05-27 17:45:27 +0800497 mux {
498 function = "flash";
499 groups = "emmc_51";
500 };
501 };
developer8b9f2852021-06-03 21:53:08 +0800502
503 pcm_pins: pcm-pins-62-to-65 {
504 mux {
505 function = "pcm";
506 groups = "pcm";
507 };
508 };
developerfd40db22021-04-29 10:08:25 +0800509};