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git01.mediatek.com / openwrt / feeds / mtk-openwrt-feeds / c20f345aab696c4a85c241fdab4c4695cbfcc5f3 / . / target / linux / mediatek / files-5.4 / arch / arm64 / boot / dts / mediatek / mt7986a-rfb.dtsi
blob: 3cb52609f364aeb742e5cd7e5340491e6d67b62d [file] [log] [blame]
developerfd40db22021-04-29 10:08:25 +0800[diff] [blame]1/dts-v1/;
2#include "mt7986a.dtsi"
3/ {
4 model = "MediaTek MT7986a RFB";
5 compatible = "mediatek,mt7986a-rfb";
6 chosen {
7 bootargs = "console=ttyS0,115200n1 loglevel=8 \
8 earlycon=uart8250,mmio32,0x11002000";
9 };
10
11 memory {
12 // fpga ddr2: 128MB*2
13 reg = <0 0x40000000 0 0x10000000>;
14 };
developerc20f3452021-05-26 17:27:35 +0800[diff] [blame^]15
16 nmbm_snfi {
17 compatible = "generic,nmbm";
18
19 #address-cells = <1>;
20 #size-cells = <1>;
21
22 lower-mtd-device = <&snand>;
23 forced-create;
24
25 partitions {
26 compatible = "fixed-partitions";
27 #address-cells = <1>;
28 #size-cells = <1>;
29
30 partition@0 {
31 label = "BL2";
32 reg = <0x00000 0x0100000>;
33 read-only;
34 };
35
36 partition@100000 {
37 label = "u-boot-env";
38 reg = <0x0100000 0x0080000>;
39 };
40
41 partition@180000 {
42 label = "Factory";
43 reg = <0x180000 0x0200000>;
44 };
45
46 partition@380000 {
47 label = "FIP";
48 reg = <0x380000 0x0200000>;
49 };
50
51 partition@580000 {
52 label = "ubi";
53 reg = <0x580000 0x4000000>;
54 };
55 };
56 };
developerfd40db22021-04-29 10:08:25 +0800[diff] [blame]57};
58
59&uart0 {
60 status = "okay";
61};
62
63&watchdog {
64 status = "okay";
65};
66
67&eth {
68 status = "okay";
69
70 gmac0: mac@0 {
71 compatible = "mediatek,eth-mac";
72 reg = <0>;
73 phy-mode = "2500base-x";
74
75 fixed-link {
76 speed = <2500>;
77 full-duplex;
78 pause;
79 };
80 };
81
82 gmac1: mac@1 {
83 compatible = "mediatek,eth-mac";
84 reg = <1>;
85 phy-mode = "2500base-x";
86
87 fixed-link {
88 speed = <2500>;
89 full-duplex;
90 pause;
91 };
92 };
93
94 mdio: mdio-bus {
95 #address-cells = <1>;
96 #size-cells = <0>;
97
developerc0f3c7f2021-05-17 11:48:36 +0800[diff] [blame]98 phy5: phy@5 {
99 compatible = "ethernet-phy-id67c9.de0a";
100 reg = <5>;
101 reset-gpios = <&pio 6 1>;
102 reset-deassert-us = <20000>;
103 phy-mode = "2500base-x";
104 };
105
106 phy6: phy@6 {
107 compatible = "ethernet-phy-id67c9.de0a";
108 reg = <6>;
109 phy-mode = "2500base-x";
110 };
111
developerfd40db22021-04-29 10:08:25 +0800[diff] [blame]112 switch@0 {
113 compatible = "mediatek,mt7531";
developerc0f3c7f2021-05-17 11:48:36 +0800[diff] [blame]114 reg = <31>;
developer51059432021-05-03 16:01:06 +0800[diff] [blame]115 reset-gpios = <&pio 5 0>;
developerfd40db22021-04-29 10:08:25 +0800[diff] [blame]116
117 ports {
118 #address-cells = <1>;
119 #size-cells = <0>;
120
121 port@0 {
122 reg = <0>;
developerc0f3c7f2021-05-17 11:48:36 +0800[diff] [blame]123 label = "lan0";
developerfd40db22021-04-29 10:08:25 +0800[diff] [blame]124 };
125
126 port@1 {
127 reg = <1>;
developerc0f3c7f2021-05-17 11:48:36 +0800[diff] [blame]128 label = "lan1";
developerfd40db22021-04-29 10:08:25 +0800[diff] [blame]129 };
130
131 port@2 {
132 reg = <2>;
developerc0f3c7f2021-05-17 11:48:36 +0800[diff] [blame]133 label = "lan2";
developerfd40db22021-04-29 10:08:25 +0800[diff] [blame]134 };
135
136 port@3 {
137 reg = <3>;
developerc0f3c7f2021-05-17 11:48:36 +0800[diff] [blame]138 label = "lan3";
developerfd40db22021-04-29 10:08:25 +0800[diff] [blame]139 };
140
141 port@4 {
142 reg = <4>;
developerc0f3c7f2021-05-17 11:48:36 +0800[diff] [blame]143 label = "lan4";
144 };
145
146 port@5 {
147 reg = <5>;
148 label = "lan5";
149 phy-mode = "2500base-x";
150
151 fixed-link {
152 speed = <2500>;
153 full-duplex;
154 pause;
155 };
developerfd40db22021-04-29 10:08:25 +0800[diff] [blame]156 };
157
158 port@6 {
159 reg = <6>;
160 label = "cpu";
161 ethernet = <&gmac0>;
162 phy-mode = "2500base-x";
163
164 fixed-link {
165 speed = <2500>;
166 full-duplex;
167 pause;
168 };
169 };
170 };
171 };
172 };
173};
174
175&hnat {
developere5763512021-05-21 01:04:58 +0800[diff] [blame]176 mtketh-wan = "eth1";
developerd7edc132021-05-06 13:49:50 +0800[diff] [blame]177 mtketh-lan = "lan";
developerfd40db22021-04-29 10:08:25 +0800[diff] [blame]178 mtketh-max-gmac = <2>;
179 status = "okay";
180};
181
182&spi0 {
183 pinctrl-names = "default";
184 pinctrl-0 = <&spi_flash_pins>;
185 cs-gpios = <0>, <0>;
186 status = "okay";
187 spi_nor@0 {
188 #address-cells = <1>;
189 #size-cells = <1>;
190 compatible = "jedec,spi-nor";
191 reg = <0>;
192 spi-max-frequency = <20000000>;
193 spi-tx-buswidth = <4>;
194 spi-rx-buswidth = <4>;
195
196 partition@00000 {
197 label = "BL2";
198 reg = <0x00000 0x0040000>;
199 };
200 partition@40000 {
201 label = "u-boot-env";
202 reg = <0x40000 0x0010000>;
203 };
204 partition@50000 {
205 label = "Factory";
206 reg = <0x50000 0x00B0000>;
207 };
208 partition@100000 {
209 label = "FIP";
210 reg = <0x100000 0x0080000>;
211 };
212 partition@180000 {
213 label = "firmware";
214 reg = <0x180000 0xE00000>;
215 };
216 };
217 spi_nand@1 {
218 #address-cells = <1>;
219 #size-cells = <1>;
220 compatible = "spi-nand";
221 reg = <1>;
222 spi-max-frequency = <20000000>;
223 spi-tx-buswidth = <4>;
224 spi-rx-buswidth = <4>;
225
226 partition@00000 {
227 label = "BL2";
228 reg = <0x00000 0x0100000>;
229 };
230 partition@100000 {
231 label = "u-boot-env";
232 reg = <0x100000 0x0080000>;
233 };
234 partition@180000 {
235 label = "Factory";
236 reg = <0x180000 0x00200000>;
237 };
238 partition@380000 {
239 label = "FIP";
240 reg = <0x380000 0x0200000>;
241 };
242 partition@580000 {
243 label = "ubi";
244 reg = <0x580000 0x4000000>;
245 };
246 };
247};
248
249&snand {
250 pinctrl-names = "default";
251 /* pin shared with spic */
252 pinctrl-0 = <&snfi_pins>;
253 status = "okay";
254 mediatek,quad-spi;
255
256 partitions {
257 compatible = "fixed-partitions";
258 #address-cells = <1>;
259 #size-cells = <1>;
developerfd40db22021-04-29 10:08:25 +0800[diff] [blame]260 };
261};
262
263&spi1 {
264 pinctrl-names = "default";
265 /* pin shared with snfi */
266 pinctrl-0 = <&spic_pins>;
267 status = "okay";
268};
269
270&pio {
271 spi_flash_pins: spi0-pins {
272 mux {
273 function = "flash";
274 groups = "spi0", "spi0_wp_hold";
275 };
276 };
277
278 snfi_pins: snfi-pins {
279 mux {
280 function = "flash";
281 groups = "snfi";
282 };
283 };
284
285 spic_pins: spi1-pins {
286 mux {
287 function = "spi";
288 groups = "spi1_1";
289 };
290 };
291};