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git01.mediatek.com / openwrt / feeds / mtk-openwrt-feeds / e576351c1600c3d7d0801dc41943ed88fe925e4e / . / target / linux / mediatek / files-5.4 / arch / arm64 / boot / dts / mediatek / mt7986a-rfb.dtsi
blob: 566a1f857eec3119005c4f391aac74767466628a [file] [log] [blame]
developerfd40db22021-04-29 10:08:25 +0800[diff] [blame]1/dts-v1/;
2#include "mt7986a.dtsi"
3/ {
4 model = "MediaTek MT7986a RFB";
5 compatible = "mediatek,mt7986a-rfb";
6 chosen {
7 bootargs = "console=ttyS0,115200n1 loglevel=8 \
8 earlycon=uart8250,mmio32,0x11002000";
9 };
10
11 memory {
12 // fpga ddr2: 128MB*2
13 reg = <0 0x40000000 0 0x10000000>;
14 };
15};
16
17&uart0 {
18 status = "okay";
19};
20
21&watchdog {
22 status = "okay";
23};
24
25&eth {
26 status = "okay";
27
28 gmac0: mac@0 {
29 compatible = "mediatek,eth-mac";
30 reg = <0>;
31 phy-mode = "2500base-x";
32
33 fixed-link {
34 speed = <2500>;
35 full-duplex;
36 pause;
37 };
38 };
39
40 gmac1: mac@1 {
41 compatible = "mediatek,eth-mac";
42 reg = <1>;
43 phy-mode = "2500base-x";
44
45 fixed-link {
46 speed = <2500>;
47 full-duplex;
48 pause;
49 };
50 };
51
52 mdio: mdio-bus {
53 #address-cells = <1>;
54 #size-cells = <0>;
55
developerc0f3c7f2021-05-17 11:48:36 +0800[diff] [blame]56 phy5: phy@5 {
57 compatible = "ethernet-phy-id67c9.de0a";
58 reg = <5>;
59 reset-gpios = <&pio 6 1>;
60 reset-deassert-us = <20000>;
61 phy-mode = "2500base-x";
62 };
63
64 phy6: phy@6 {
65 compatible = "ethernet-phy-id67c9.de0a";
66 reg = <6>;
67 phy-mode = "2500base-x";
68 };
69
developerfd40db22021-04-29 10:08:25 +0800[diff] [blame]70 switch@0 {
71 compatible = "mediatek,mt7531";
developerc0f3c7f2021-05-17 11:48:36 +0800[diff] [blame]72 reg = <31>;
developer51059432021-05-03 16:01:06 +0800[diff] [blame]73 reset-gpios = <&pio 5 0>;
developerfd40db22021-04-29 10:08:25 +0800[diff] [blame]74
75 ports {
76 #address-cells = <1>;
77 #size-cells = <0>;
78
79 port@0 {
80 reg = <0>;
developerc0f3c7f2021-05-17 11:48:36 +0800[diff] [blame]81 label = "lan0";
developerfd40db22021-04-29 10:08:25 +0800[diff] [blame]82 };
83
84 port@1 {
85 reg = <1>;
developerc0f3c7f2021-05-17 11:48:36 +0800[diff] [blame]86 label = "lan1";
developerfd40db22021-04-29 10:08:25 +0800[diff] [blame]87 };
88
89 port@2 {
90 reg = <2>;
developerc0f3c7f2021-05-17 11:48:36 +0800[diff] [blame]91 label = "lan2";
developerfd40db22021-04-29 10:08:25 +0800[diff] [blame]92 };
93
94 port@3 {
95 reg = <3>;
developerc0f3c7f2021-05-17 11:48:36 +0800[diff] [blame]96 label = "lan3";
developerfd40db22021-04-29 10:08:25 +0800[diff] [blame]97 };
98
99 port@4 {
100 reg = <4>;
developerc0f3c7f2021-05-17 11:48:36 +0800[diff] [blame]101 label = "lan4";
102 };
103
104 port@5 {
105 reg = <5>;
106 label = "lan5";
107 phy-mode = "2500base-x";
108
109 fixed-link {
110 speed = <2500>;
111 full-duplex;
112 pause;
113 };
developerfd40db22021-04-29 10:08:25 +0800[diff] [blame]114 };
115
116 port@6 {
117 reg = <6>;
118 label = "cpu";
119 ethernet = <&gmac0>;
120 phy-mode = "2500base-x";
121
122 fixed-link {
123 speed = <2500>;
124 full-duplex;
125 pause;
126 };
127 };
128 };
129 };
130 };
131};
132
133&hnat {
developere5763512021-05-21 01:04:58 +0800[diff] [blame^]134 mtketh-wan = "eth1";
developerd7edc132021-05-06 13:49:50 +0800[diff] [blame]135 mtketh-lan = "lan";
developerfd40db22021-04-29 10:08:25 +0800[diff] [blame]136 mtketh-max-gmac = <2>;
137 status = "okay";
138};
139
140&spi0 {
141 pinctrl-names = "default";
142 pinctrl-0 = <&spi_flash_pins>;
143 cs-gpios = <0>, <0>;
144 status = "okay";
145 spi_nor@0 {
146 #address-cells = <1>;
147 #size-cells = <1>;
148 compatible = "jedec,spi-nor";
149 reg = <0>;
150 spi-max-frequency = <20000000>;
151 spi-tx-buswidth = <4>;
152 spi-rx-buswidth = <4>;
153
154 partition@00000 {
155 label = "BL2";
156 reg = <0x00000 0x0040000>;
157 };
158 partition@40000 {
159 label = "u-boot-env";
160 reg = <0x40000 0x0010000>;
161 };
162 partition@50000 {
163 label = "Factory";
164 reg = <0x50000 0x00B0000>;
165 };
166 partition@100000 {
167 label = "FIP";
168 reg = <0x100000 0x0080000>;
169 };
170 partition@180000 {
171 label = "firmware";
172 reg = <0x180000 0xE00000>;
173 };
174 };
175 spi_nand@1 {
176 #address-cells = <1>;
177 #size-cells = <1>;
178 compatible = "spi-nand";
179 reg = <1>;
180 spi-max-frequency = <20000000>;
181 spi-tx-buswidth = <4>;
182 spi-rx-buswidth = <4>;
183
184 partition@00000 {
185 label = "BL2";
186 reg = <0x00000 0x0100000>;
187 };
188 partition@100000 {
189 label = "u-boot-env";
190 reg = <0x100000 0x0080000>;
191 };
192 partition@180000 {
193 label = "Factory";
194 reg = <0x180000 0x00200000>;
195 };
196 partition@380000 {
197 label = "FIP";
198 reg = <0x380000 0x0200000>;
199 };
200 partition@580000 {
201 label = "ubi";
202 reg = <0x580000 0x4000000>;
203 };
204 };
205};
206
207&snand {
208 pinctrl-names = "default";
209 /* pin shared with spic */
210 pinctrl-0 = <&snfi_pins>;
211 status = "okay";
212 mediatek,quad-spi;
213
214 partitions {
215 compatible = "fixed-partitions";
216 #address-cells = <1>;
217 #size-cells = <1>;
218
219 partition@0 {
220 label = "BL2";
221 reg = <0x00000 0x0100000>;
222 read-only;
223 };
224
225 partition@100000 {
226 label = "u-boot-env";
227 reg = <0x0100000 0x0080000>;
228 };
229
230 partition@180000 {
231 label = "Factory";
232 reg = <0x180000 0x0200000>;
233 };
234
235 partition@380000 {
236 label = "FIP";
237 reg = <0x380000 0x0200000>;
238 };
239
240 partition@580000 {
241 label = "ubi";
242 reg = <0x580000 0x4000000>;
243 };
244 };
245};
246
247&spi1 {
248 pinctrl-names = "default";
249 /* pin shared with snfi */
250 pinctrl-0 = <&spic_pins>;
251 status = "okay";
252};
253
254&pio {
255 spi_flash_pins: spi0-pins {
256 mux {
257 function = "flash";
258 groups = "spi0", "spi0_wp_hold";
259 };
260 };
261
262 snfi_pins: snfi-pins {
263 mux {
264 function = "flash";
265 groups = "snfi";
266 };
267 };
268
269 spic_pins: spi1-pins {
270 mux {
271 function = "spi";
272 groups = "spi1_1";
273 };
274 };
275};