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developerfd40db22021-04-29 10:08:25 +08001/dts-v1/;
2#include "mt7986a.dtsi"
3/ {
4 model = "MediaTek MT7986a RFB";
5 compatible = "mediatek,mt7986a-rfb";
6 chosen {
7 bootargs = "console=ttyS0,115200n1 loglevel=8 \
8 earlycon=uart8250,mmio32,0x11002000";
9 };
10
11 memory {
developerfd40db22021-04-29 10:08:25 +080012 reg = <0 0x40000000 0 0x10000000>;
13 };
developerc20f3452021-05-26 17:27:35 +080014
15 nmbm_snfi {
16 compatible = "generic,nmbm";
17
18 #address-cells = <1>;
19 #size-cells = <1>;
20
21 lower-mtd-device = <&snand>;
22 forced-create;
23
24 partitions {
25 compatible = "fixed-partitions";
26 #address-cells = <1>;
27 #size-cells = <1>;
28
29 partition@0 {
30 label = "BL2";
31 reg = <0x00000 0x0100000>;
32 read-only;
33 };
34
35 partition@100000 {
36 label = "u-boot-env";
37 reg = <0x0100000 0x0080000>;
38 };
39
40 partition@180000 {
41 label = "Factory";
42 reg = <0x180000 0x0200000>;
43 };
44
45 partition@380000 {
46 label = "FIP";
47 reg = <0x380000 0x0200000>;
48 };
49
50 partition@580000 {
51 label = "ubi";
52 reg = <0x580000 0x4000000>;
53 };
54 };
55 };
developerfeac91e2021-06-02 09:46:12 +080056
57 reg_1p8v: regulator-1p8v {
58 compatible = "regulator-fixed";
59 regulator-name = "fixed-1.8V";
60 regulator-min-microvolt = <1800000>;
61 regulator-max-microvolt = <1800000>;
62 regulator-boot-on;
63 regulator-always-on;
64 };
65
66 reg_3p3v: regulator-3p3v {
67 compatible = "regulator-fixed";
68 regulator-name = "fixed-3.3V";
69 regulator-min-microvolt = <3300000>;
70 regulator-max-microvolt = <3300000>;
71 regulator-boot-on;
72 regulator-always-on;
73 };
developerfd40db22021-04-29 10:08:25 +080074};
75
developer8b9f2852021-06-03 21:53:08 +080076&pwm {
77 pinctrl-names = "default";
78 pinctrl-0 = <&pwm0_pin &pwm1_pin_g1>;
79 status = "okay";
80};
81
developerfd40db22021-04-29 10:08:25 +080082&uart0 {
83 status = "okay";
84};
85
developer8b9f2852021-06-03 21:53:08 +080086&uart1 {
87 pinctrl-names = "default";
88 pinctrl-0 = <&uart1_pins>;
89 status = "okay";
90};
91
92&uart2 {
93 pinctrl-names = "default";
94 pinctrl-0 = <&uart2_pins>;
95 status = "okay";
96};
97
98&i2c0 {
99 pinctrl-names = "default";
100 pinctrl-0 = <&i2c_pins>;
101 status = "okay";
102};
103
104&auxadc {
105 status = "okay";
106};
107
developerfd40db22021-04-29 10:08:25 +0800108&watchdog {
109 status = "okay";
110};
111
112&eth {
113 status = "okay";
114
115 gmac0: mac@0 {
116 compatible = "mediatek,eth-mac";
117 reg = <0>;
118 phy-mode = "2500base-x";
119
120 fixed-link {
121 speed = <2500>;
122 full-duplex;
123 pause;
124 };
125 };
126
127 gmac1: mac@1 {
128 compatible = "mediatek,eth-mac";
129 reg = <1>;
130 phy-mode = "2500base-x";
131
132 fixed-link {
133 speed = <2500>;
134 full-duplex;
135 pause;
136 };
137 };
138
139 mdio: mdio-bus {
140 #address-cells = <1>;
141 #size-cells = <0>;
142
developerc0f3c7f2021-05-17 11:48:36 +0800143 phy5: phy@5 {
144 compatible = "ethernet-phy-id67c9.de0a";
145 reg = <5>;
146 reset-gpios = <&pio 6 1>;
147 reset-deassert-us = <20000>;
148 phy-mode = "2500base-x";
149 };
150
151 phy6: phy@6 {
152 compatible = "ethernet-phy-id67c9.de0a";
153 reg = <6>;
154 phy-mode = "2500base-x";
155 };
156
developerfd40db22021-04-29 10:08:25 +0800157 switch@0 {
158 compatible = "mediatek,mt7531";
developerc0f3c7f2021-05-17 11:48:36 +0800159 reg = <31>;
developer51059432021-05-03 16:01:06 +0800160 reset-gpios = <&pio 5 0>;
developerfd40db22021-04-29 10:08:25 +0800161
162 ports {
163 #address-cells = <1>;
164 #size-cells = <0>;
165
166 port@0 {
167 reg = <0>;
developerc0f3c7f2021-05-17 11:48:36 +0800168 label = "lan0";
developerfd40db22021-04-29 10:08:25 +0800169 };
170
171 port@1 {
172 reg = <1>;
developerc0f3c7f2021-05-17 11:48:36 +0800173 label = "lan1";
developerfd40db22021-04-29 10:08:25 +0800174 };
175
176 port@2 {
177 reg = <2>;
developerc0f3c7f2021-05-17 11:48:36 +0800178 label = "lan2";
developerfd40db22021-04-29 10:08:25 +0800179 };
180
181 port@3 {
182 reg = <3>;
developerc0f3c7f2021-05-17 11:48:36 +0800183 label = "lan3";
developerfd40db22021-04-29 10:08:25 +0800184 };
185
186 port@4 {
187 reg = <4>;
developerc0f3c7f2021-05-17 11:48:36 +0800188 label = "lan4";
189 };
190
191 port@5 {
192 reg = <5>;
193 label = "lan5";
194 phy-mode = "2500base-x";
195
196 fixed-link {
197 speed = <2500>;
198 full-duplex;
199 pause;
200 };
developerfd40db22021-04-29 10:08:25 +0800201 };
202
203 port@6 {
204 reg = <6>;
205 label = "cpu";
206 ethernet = <&gmac0>;
207 phy-mode = "2500base-x";
208
209 fixed-link {
210 speed = <2500>;
211 full-duplex;
212 pause;
213 };
214 };
215 };
216 };
217 };
218};
219
220&hnat {
developere5763512021-05-21 01:04:58 +0800221 mtketh-wan = "eth1";
developerd7edc132021-05-06 13:49:50 +0800222 mtketh-lan = "lan";
developerfd40db22021-04-29 10:08:25 +0800223 mtketh-max-gmac = <2>;
224 status = "okay";
225};
226
227&spi0 {
228 pinctrl-names = "default";
229 pinctrl-0 = <&spi_flash_pins>;
230 cs-gpios = <0>, <0>;
231 status = "okay";
232 spi_nor@0 {
233 #address-cells = <1>;
234 #size-cells = <1>;
235 compatible = "jedec,spi-nor";
236 reg = <0>;
237 spi-max-frequency = <20000000>;
238 spi-tx-buswidth = <4>;
239 spi-rx-buswidth = <4>;
240
241 partition@00000 {
242 label = "BL2";
243 reg = <0x00000 0x0040000>;
244 };
245 partition@40000 {
246 label = "u-boot-env";
247 reg = <0x40000 0x0010000>;
248 };
249 partition@50000 {
250 label = "Factory";
251 reg = <0x50000 0x00B0000>;
252 };
253 partition@100000 {
254 label = "FIP";
255 reg = <0x100000 0x0080000>;
256 };
257 partition@180000 {
258 label = "firmware";
259 reg = <0x180000 0xE00000>;
260 };
261 };
262 spi_nand@1 {
263 #address-cells = <1>;
264 #size-cells = <1>;
265 compatible = "spi-nand";
266 reg = <1>;
267 spi-max-frequency = <20000000>;
268 spi-tx-buswidth = <4>;
269 spi-rx-buswidth = <4>;
270
271 partition@00000 {
272 label = "BL2";
273 reg = <0x00000 0x0100000>;
274 };
275 partition@100000 {
276 label = "u-boot-env";
277 reg = <0x100000 0x0080000>;
278 };
279 partition@180000 {
280 label = "Factory";
281 reg = <0x180000 0x00200000>;
282 };
283 partition@380000 {
284 label = "FIP";
285 reg = <0x380000 0x0200000>;
286 };
287 partition@580000 {
288 label = "ubi";
289 reg = <0x580000 0x4000000>;
290 };
291 };
292};
293
294&snand {
295 pinctrl-names = "default";
developerfd40db22021-04-29 10:08:25 +0800296 pinctrl-0 = <&snfi_pins>;
297 status = "okay";
298 mediatek,quad-spi;
299
300 partitions {
301 compatible = "fixed-partitions";
302 #address-cells = <1>;
303 #size-cells = <1>;
developerfd40db22021-04-29 10:08:25 +0800304 };
305};
306
307&spi1 {
308 pinctrl-names = "default";
developer8b9f2852021-06-03 21:53:08 +0800309 pinctrl-0 = <&spic_pins_g2>;
developerfd40db22021-04-29 10:08:25 +0800310 status = "okay";
311};
312
developer637f5552021-05-27 17:45:27 +0800313&mmc0 {
314 pinctrl-names = "default", "state_uhs";
315 pinctrl-0 = <&mmc0_pins_default>;
316 pinctrl-1 = <&mmc0_pins_uhs>;
317 bus-width = <8>;
318 max-frequency = <50000000>;
319 cap-mmc-highspeed;
320 mmc-hs200-1_8v;
321 vmmc-supply = <&reg_3p3v>;
322 vqmmc-supply = <&reg_1p8v>;
323 non-removable;
324 status = "okay";
325};
326
developerfd40db22021-04-29 10:08:25 +0800327&pio {
developer8b9f2852021-06-03 21:53:08 +0800328 wifi_led_pins: wifi_led-pins-1-2 {
developerfd40db22021-04-29 10:08:25 +0800329 mux {
developer8b9f2852021-06-03 21:53:08 +0800330 function = "led";
331 groups = "wifi_led";
332 };
333 };
334
335 i2c_pins: i2c-pins-3-4 {
336 mux {
337 function = "i2c";
338 groups = "i2c";
339 };
340 };
341
342 uart1_pins_g0: uart1-pins-7-to-10 {
343 mux {
344 function = "uart";
345 groups = "uart1_0";
346 };
347 };
348
349 jtag_pins: jtag-pins-11-to-14 {
350 mux {
351 function = "jtag";
352 groups = "jtag";
353 };
354 };
355
356 spic_pins_g0: spic-pins-11-to-14 {
357 mux {
358 function = "spi";
359 groups = "spi1_0";
360 };
361 };
362
363 pwm1_pin_g0: pwm1-pin-20 {
364 mux {
365 function = "pwm";
366 groups = "pwm1_1";
367 };
368 };
369
370 pwm0_pin: pwm0-pin-21 {
371 mux {
372 function = "pwm";
373 groups = "pwm0";
374 };
375 };
376
377 pwm1_pin_g1: pwm1-pin-22 {
378 mux {
379 function = "pwm";
380 groups = "pwm1_0";
381 };
382 };
383
384 spic_pins_g1: spic-pins-23-to-26 {
385 mux {
386 function = "spi";
387 groups = "spi1_1";
388 };
389 };
390
391 uart1_pins_g1: uart1-pins-23-to-26 {
392 mux {
393 function = "uart";
394 groups = "uart1_1";
developerfd40db22021-04-29 10:08:25 +0800395 };
396 };
397
developer8b9f2852021-06-03 21:53:08 +0800398 snfi_pins: snfi-pins-23-to-28 {
developerfd40db22021-04-29 10:08:25 +0800399 mux {
400 function = "flash";
401 groups = "snfi";
402 };
403 };
404
developer8b9f2852021-06-03 21:53:08 +0800405 spic_pins_g2: spic-pins-29-to-32 {
developerfd40db22021-04-29 10:08:25 +0800406 mux {
407 function = "spi";
developer19d22f62021-05-27 17:36:23 +0800408 groups = "spi1_2";
developerfd40db22021-04-29 10:08:25 +0800409 };
410 };
developer637f5552021-05-27 17:45:27 +0800411
developer8b9f2852021-06-03 21:53:08 +0800412 uart1_pins_g2: uart1-pins-29-to-32 {
413 mux {
414 function = "uart";
415 groups = "uart1_2";
416 };
417 };
418
419 uart2_pins_g0: uart1-pins-29-to-32 {
420 mux {
421 function = "uart";
422 groups = "uart1_2";
423 };
424 };
425
426 uart2_pins_g1: uart1-pins-23-to-36 {
427 mux {
428 function = "uart";
429 groups = "uart2_1";
430 };
431 };
432
433 spic_pins_g3: spic-pins-33-to-36 {
434 mux {
435 function = "spi";
436 groups = "spi1_3";
437 };
438 };
439
440 uart1_pins_g3: uart1-pins-35-to-38 {
441 mux {
442 function = "uart";
443 groups = "uart1_3_rx_tx", "uart1_3_cts_rts";
444 };
445 };
446
447 spi_flash_pins: spi-flash-pins-33-to-38 {
developer637f5552021-05-27 17:45:27 +0800448 mux {
449 function = "flash";
developer8b9f2852021-06-03 21:53:08 +0800450 groups = "spi0", "spi0_wp_hold";
451 };
452 };
453
454 uart1_pins: uart1-pins-42-to-45 {
455 mux {
456 function = "uart";
457 groups = "uart1";
458 };
459 };
460
461 uart2_pins: uart1-pins-46-to-49 {
462 mux {
463 function = "uart";
464 groups = "uart2";
465 };
466 };
467
468 mmc0_pins_default: mmc0-pins-50-to-61-default {
469 mux {
470 function = "flash";
developer637f5552021-05-27 17:45:27 +0800471 groups = "emmc_51";
472 };
473 };
474
developer8b9f2852021-06-03 21:53:08 +0800475 mmc0_pins_uhs: mmc0-pins-50-to-61-uhs {
developer637f5552021-05-27 17:45:27 +0800476 mux {
477 function = "flash";
478 groups = "emmc_51";
479 };
480 };
developer8b9f2852021-06-03 21:53:08 +0800481
482 pcm_pins: pcm-pins-62-to-65 {
483 mux {
484 function = "pcm";
485 groups = "pcm";
486 };
487 };
developerfd40db22021-04-29 10:08:25 +0800488};