developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0 OR MIT) |
| 2 | /* |
| 3 | * Copyright (C) 2021 MediaTek Inc. |
| 4 | * Author: Sam.Shih <sam.shih@mediatek.com> |
| 5 | */ |
| 6 | |
| 7 | #include <dt-bindings/interrupt-controller/irq.h> |
| 8 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 9 | #include <dt-bindings/phy/phy.h> |
| 10 | #include <dt-bindings/reset/ti-syscon.h> |
| 11 | #include <dt-bindings/clock/mt7988-clk.h> |
| 12 | #include <dt-bindings/pinctrl/mt65xx.h> |
| 13 | #include <dt-bindings/thermal/thermal.h> |
| 14 | #include <dt-bindings/regulator/richtek,rt5190a-regulator.h> |
| 15 | #include <dt-bindings/power/mt7988-power.h> |
| 16 | |
| 17 | / { |
| 18 | compatible = "mediatek,mt7988-rfb"; |
| 19 | interrupt-parent = <&gic>; |
| 20 | #address-cells = <2>; |
| 21 | #size-cells = <2>; |
| 22 | cpus { |
| 23 | #address-cells = <1>; |
| 24 | #size-cells = <0>; |
| 25 | cpu@0 { |
| 26 | device_type = "cpu"; |
| 27 | compatible = "arm,cortex-a73"; |
| 28 | enable-method = "psci"; |
developer | 36e6ca2 | 2023-04-26 18:04:30 +0800 | [diff] [blame] | 29 | next-level-cache = <&l2_cache>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 30 | reg = <0x0>; |
| 31 | clocks = <&mcusys CK_MCU_ARM_DIV_SEL>, |
| 32 | <&topckgen CK_TOP_CB_NET1_D4>, |
| 33 | <&apmixedsys CK_APMIXED_ARM_B>, |
| 34 | <&mcusys CK_MCU_BUS_DIV_SEL>, |
| 35 | <&apmixedsys CK_APMIXED_CCIPLL2_B>; |
| 36 | clock-names = "cpu", "intermediate", "armpll", "cci", |
| 37 | "ccipll"; |
| 38 | operating-points-v2 = <&cluster0_opp>; |
| 39 | nvmem-cells = <&cpufreq_calibration>; |
| 40 | nvmem-cell-names = "calibration-data"; |
| 41 | }; |
| 42 | |
| 43 | cpu@1 { |
| 44 | device_type = "cpu"; |
| 45 | compatible = "arm,cortex-a73"; |
| 46 | enable-method = "psci"; |
developer | 36e6ca2 | 2023-04-26 18:04:30 +0800 | [diff] [blame] | 47 | next-level-cache = <&l2_cache>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 48 | reg = <0x1>; |
| 49 | clocks = <&mcusys CK_MCU_ARM_DIV_SEL>, |
| 50 | <&topckgen CK_TOP_CB_NET1_D4>, |
| 51 | <&apmixedsys CK_APMIXED_ARM_B>, |
| 52 | <&mcusys CK_MCU_BUS_DIV_SEL>, |
| 53 | <&apmixedsys CK_APMIXED_CCIPLL2_B>; |
| 54 | clock-names = "cpu", "intermediate", "armpll", "cci", |
| 55 | "ccipll"; |
| 56 | operating-points-v2 = <&cluster0_opp>; |
| 57 | nvmem-cells = <&cpufreq_calibration>; |
| 58 | nvmem-cell-names = "calibration-data"; |
| 59 | }; |
| 60 | |
| 61 | cpu@2 { |
| 62 | device_type = "cpu"; |
| 63 | compatible = "arm,cortex-a73"; |
| 64 | enable-method = "psci"; |
developer | 36e6ca2 | 2023-04-26 18:04:30 +0800 | [diff] [blame] | 65 | next-level-cache = <&l2_cache>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 66 | reg = <0x2>; |
| 67 | clocks = <&mcusys CK_MCU_ARM_DIV_SEL>, |
| 68 | <&topckgen CK_TOP_CB_NET1_D4>, |
| 69 | <&apmixedsys CK_APMIXED_ARM_B>, |
| 70 | <&mcusys CK_MCU_BUS_DIV_SEL>, |
| 71 | <&apmixedsys CK_APMIXED_CCIPLL2_B>; |
| 72 | clock-names = "cpu", "intermediate", "armpll", "cci", |
| 73 | "ccipll"; |
| 74 | operating-points-v2 = <&cluster0_opp>; |
| 75 | nvmem-cells = <&cpufreq_calibration>; |
| 76 | nvmem-cell-names = "calibration-data"; |
| 77 | }; |
| 78 | |
| 79 | cpu@3 { |
| 80 | device_type = "cpu"; |
| 81 | compatible = "arm,cortex-a73"; |
| 82 | enable-method = "psci"; |
developer | 36e6ca2 | 2023-04-26 18:04:30 +0800 | [diff] [blame] | 83 | next-level-cache = <&l2_cache>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 84 | reg = <0x3>; |
| 85 | clocks = <&mcusys CK_MCU_ARM_DIV_SEL>, |
| 86 | <&topckgen CK_TOP_CB_NET1_D4>, |
| 87 | <&apmixedsys CK_APMIXED_ARM_B>, |
| 88 | <&mcusys CK_MCU_BUS_DIV_SEL>, |
| 89 | <&apmixedsys CK_APMIXED_CCIPLL2_B>; |
| 90 | clock-names = "cpu", "intermediate", "armpll", "cci", |
| 91 | "ccipll"; |
| 92 | operating-points-v2 = <&cluster0_opp>; |
| 93 | nvmem-cells = <&cpufreq_calibration>; |
| 94 | nvmem-cell-names = "calibration-data"; |
| 95 | }; |
| 96 | |
developer | 36e6ca2 | 2023-04-26 18:04:30 +0800 | [diff] [blame] | 97 | l2_cache: l2-cache { |
| 98 | compatible = "cache"; |
| 99 | cache-level = <2>; |
| 100 | }; |
| 101 | |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 102 | cluster0_opp: opp_table0 { |
| 103 | compatible = "operating-points-v2"; |
| 104 | opp-shared; |
| 105 | opp00 { |
| 106 | opp-hz = /bits/ 64 <800000000>; |
| 107 | opp-microvolt = <850000>; |
| 108 | }; |
| 109 | opp01 { |
| 110 | opp-hz = /bits/ 64 <1100000000>; |
| 111 | opp-microvolt = <850000>; |
| 112 | }; |
| 113 | opp02 { |
| 114 | opp-hz = /bits/ 64 <1500000000>; |
| 115 | opp-microvolt = <850000>; |
| 116 | }; |
| 117 | opp03 { |
| 118 | opp-hz = /bits/ 64 <1800000000>; |
| 119 | opp-microvolt = <900000>; |
| 120 | }; |
| 121 | }; |
| 122 | }; |
| 123 | |
developer | b655533 | 2022-11-30 15:52:42 +0800 | [diff] [blame] | 124 | pmu { |
| 125 | compatible = "arm,cortex-a73-pmu"; |
| 126 | interrupt-parent = <&gic>; |
developer | e653e62 | 2023-04-20 21:38:45 +0800 | [diff] [blame] | 127 | interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; |
developer | b655533 | 2022-11-30 15:52:42 +0800 | [diff] [blame] | 128 | }; |
| 129 | |
developer | 0fef522 | 2023-04-26 14:48:31 +0800 | [diff] [blame] | 130 | hwver: hwver { |
| 131 | compatible = "mediatek,hwver", "syscon"; |
| 132 | reg = <0 0x8000000 0 0x1000>; |
| 133 | }; |
| 134 | |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 135 | thermal-zones { |
| 136 | cpu_thermal: cpu-thermal { |
| 137 | polling-delay-passive = <1000>; |
| 138 | polling-delay = <1000>; |
| 139 | thermal-sensors = <&lvts 0>; |
| 140 | trips { |
| 141 | cpu_trip_crit: crit { |
| 142 | temperature = <125000>; |
| 143 | hysteresis = <2000>; |
| 144 | type = "critical"; |
| 145 | }; |
| 146 | |
| 147 | cpu_trip_hot: hot { |
| 148 | temperature = <120000>; |
| 149 | hysteresis = <2000>; |
| 150 | type = "hot"; |
| 151 | }; |
| 152 | |
| 153 | cpu_trip_active_high: active-high { |
| 154 | temperature = <115000>; |
| 155 | hysteresis = <2000>; |
| 156 | type = "active"; |
| 157 | }; |
| 158 | |
| 159 | cpu_trip_active_low: active-low { |
| 160 | temperature = <85000>; |
| 161 | hysteresis = <2000>; |
| 162 | type = "active"; |
| 163 | }; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 164 | }; |
| 165 | |
| 166 | cooling-maps { |
| 167 | cpu-active-high { |
| 168 | /* active: set fan to cooling level 2 */ |
| 169 | cooling-device = <&fan 2 2>; |
| 170 | trip = <&cpu_trip_active_high>; |
| 171 | }; |
| 172 | |
| 173 | cpu-active-low { |
| 174 | /* active: set fan to cooling level 1 */ |
| 175 | cooling-device = <&fan 1 1>; |
| 176 | trip = <&cpu_trip_active_low>; |
| 177 | }; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 178 | }; |
| 179 | |
| 180 | }; |
| 181 | }; |
| 182 | |
| 183 | mmc0: mmc@11230000 { |
| 184 | compatible = "mediatek,mt7986-mmc"; |
| 185 | reg = <0 0x11230000 0 0x1000>, |
| 186 | <0 0x11D60000 0 0x1000>; |
| 187 | interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; |
| 188 | clocks = <&infracfg_ao CK_INFRA_MSDC400>, |
| 189 | <&infracfg_ao CK_INFRA_MSDC2_HCK>, |
| 190 | <&infracfg_ao CK_INFRA_133M_MSDC_0_HCK>, |
| 191 | <&infracfg_ao CK_INFRA_66M_MSDC_0_HCK>; |
| 192 | clock-names = "source", "hclk", "ahb_cg", "axi_cg"; |
| 193 | status = "disabled"; |
| 194 | }; |
| 195 | |
| 196 | wed: wed@15010000 { |
| 197 | compatible = "mediatek,wed"; |
| 198 | wed_num = <3>; |
| 199 | /* add this property for wed get the pci slot number. */ |
| 200 | pci_slot_map = <0>, <1>, <2>; |
| 201 | reg = <0 0x15010000 0 0x2000>, |
| 202 | <0 0x15012000 0 0x2000>, |
| 203 | <0 0x15014000 0 0x2000>; |
| 204 | interrupt-parent = <&gic>; |
| 205 | interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, |
| 206 | <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, |
| 207 | <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>; |
| 208 | }; |
| 209 | |
| 210 | wed2: wed2@15012000 { |
| 211 | compatible = "mediatek,wed2"; |
| 212 | wed_num = <3>; |
| 213 | /* add this property for wed get the pci slot number. */ |
| 214 | reg = <0 0x15010000 0 0x2000>, |
| 215 | <0 0x15012000 0 0x2000>, |
| 216 | <0 0x15014000 0 0x2000>; |
| 217 | interrupt-parent = <&gic>; |
| 218 | interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, |
| 219 | <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, |
| 220 | <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>; |
| 221 | }; |
| 222 | |
| 223 | wed3: wed3@15014000 { |
| 224 | compatible = "mediatek,wed3"; |
| 225 | wed_num = <3>; |
| 226 | /* add this property for wed get the pci slot number. */ |
| 227 | reg = <0 0x15010000 0 0x2000>, |
| 228 | <0 0x15012000 0 0x2000>, |
| 229 | <0 0x15014000 0 0x2000>; |
| 230 | interrupt-parent = <&gic>; |
| 231 | interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, |
| 232 | <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, |
| 233 | <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>; |
| 234 | }; |
| 235 | |
| 236 | wdma: wdma@15104800 { |
| 237 | compatible = "mediatek,wed-wdma"; |
| 238 | reg = <0 0x15104800 0 0x400>, |
| 239 | <0 0x15104c00 0 0x400>, |
| 240 | <0 0x15105000 0 0x400>; |
| 241 | }; |
| 242 | |
| 243 | ap2woccif: ap2woccif@151A5000 { |
| 244 | compatible = "mediatek,ap2woccif"; |
| 245 | reg = <0 0x151A5000 0 0x1000>, |
| 246 | <0 0x152A5000 0 0x1000>, |
| 247 | <0 0x153A5000 0 0x1000>; |
| 248 | interrupt-parent = <&gic>; |
| 249 | interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, |
| 250 | <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, |
| 251 | <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; |
| 252 | }; |
| 253 | |
| 254 | wocpu0_ilm: wocpu0_ilm@151E0000 { |
| 255 | compatible = "mediatek,wocpu0_ilm"; |
| 256 | reg = <0 0x151E0000 0 0x8000>; |
| 257 | }; |
| 258 | |
| 259 | wocpu1_ilm: wocpu1_ilm@152E0000 { |
| 260 | compatible = "mediatek,wocpu1_ilm"; |
| 261 | reg = <0 0x152E0000 0 0x8000>; |
| 262 | }; |
| 263 | |
| 264 | wocpu2_ilm: wocpu2_ilm@153E0000 { |
| 265 | compatible = "mediatek,wocpu2_ilm"; |
| 266 | reg = <0 0x153E0000 0 0x8000>; |
| 267 | }; |
| 268 | |
| 269 | wocpu_dlm: wocpu_dlm@151E8000 { |
| 270 | compatible = "mediatek,wocpu_dlm"; |
| 271 | reg = <0 0x151E8000 0 0x2000>, |
| 272 | <0 0x152E8000 0 0x2000>, |
| 273 | <0 0x153E8000 0 0x2000>; |
| 274 | |
| 275 | resets = <ðsysrst 0>; |
| 276 | reset-names = "wocpu_rst"; |
| 277 | }; |
| 278 | |
| 279 | cpu_boot: wocpu_boot@15194000 { |
| 280 | compatible = "mediatek,wocpu_boot"; |
| 281 | reg = <0 0x15194000 0 0x1000>, |
| 282 | <0 0x15294000 0 0x1000>, |
| 283 | <0 0x15394000 0 0x1000>; |
| 284 | }; |
| 285 | |
| 286 | reserved-memory { |
| 287 | #address-cells = <2>; |
| 288 | #size-cells = <2>; |
| 289 | ranges; |
| 290 | |
developer | 739ffc6 | 2023-03-01 20:42:18 +0800 | [diff] [blame] | 291 | ramoops: ramoops@42ff0000{ |
| 292 | compatible = "ramoops"; |
| 293 | reg = <0x0 0x42ff0000 0x0 0x10000>; |
| 294 | record-size = <0x2000>; |
| 295 | console-size = <0x2000>; |
| 296 | pmsg-size = <0x2000>; |
| 297 | }; |
| 298 | |
developer | 93dc175 | 2023-07-24 19:19:00 +0800 | [diff] [blame] | 299 | /* 512 KiB reserved for ARM Trusted Firmware (BL31 + BL32) */ |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 300 | secmon_reserved: secmon@43000000 { |
developer | 93dc175 | 2023-07-24 19:19:00 +0800 | [diff] [blame] | 301 | reg = <0 0x43000000 0 0x80000>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 302 | no-map; |
| 303 | }; |
| 304 | |
| 305 | wmcpu_emi: wmcpu-reserved@47CC0000 { |
| 306 | compatible = "mediatek,wmcpu-reserved"; |
| 307 | no-map; |
| 308 | reg = <0 0x47CC0000 0 0x00100000>; |
| 309 | }; |
| 310 | |
| 311 | wocpu0_emi: wocpu0_emi@4F600000 { |
| 312 | compatible = "mediatek,wocpu0_emi"; |
| 313 | no-map; |
| 314 | reg = <0 0x4F600000 0 0x40000>; |
| 315 | shared = <0>; |
| 316 | }; |
| 317 | |
| 318 | wocpu1_emi: wocpu1_emi@4F640000 { |
| 319 | compatible = "mediatek,wocpu1_emi"; |
| 320 | no-map; |
| 321 | reg = <0 0x4F640000 0 0x40000>; |
| 322 | shared = <0>; |
| 323 | }; |
| 324 | |
| 325 | wocpu2_emi: wocpu2_emi@4F680000 { |
| 326 | compatible = "mediatek,wocpu2_emi"; |
| 327 | no-map; |
| 328 | reg = <0 0x4F680000 0 0x40000>; |
| 329 | shared = <0>; |
| 330 | }; |
| 331 | |
| 332 | wocpu_data: wocpu_data@4F700000 { |
| 333 | compatible = "mediatek,wocpu_data"; |
| 334 | no-map; |
| 335 | reg = <0 0x4F700000 0 0x800000>; |
| 336 | shared = <1>; |
| 337 | }; |
| 338 | }; |
| 339 | |
| 340 | psci { |
| 341 | compatible = "arm,psci-0.2"; |
| 342 | method = "smc"; |
| 343 | }; |
| 344 | |
| 345 | system_clk: dummy_system_clk { |
| 346 | compatible = "fixed-clock"; |
| 347 | clock-frequency = <40000000>; |
| 348 | #clock-cells = <0>; |
| 349 | }; |
| 350 | |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 351 | timer { |
| 352 | compatible = "arm,armv8-timer"; |
| 353 | interrupt-parent = <&gic>; |
| 354 | interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, |
| 355 | <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, |
| 356 | <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, |
| 357 | <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; |
| 358 | |
| 359 | }; |
| 360 | |
developer | abfa233 | 2023-08-09 09:11:12 +0800 | [diff] [blame] | 361 | tops: tops@09100000 { |
| 362 | compatible = "mediatek,tops"; |
| 363 | reg = <0 0x09100000 0 0x01000000>; |
| 364 | reg-names = "tops-base"; |
| 365 | clocks = <&topckgen CK_TOP_BUS_TOPS_SEL>, |
| 366 | <&topckgen CK_TOP_TOPS_P2_26M_SEL>, |
| 367 | <&topckgen CK_TOP_NETSYS_TOPS_400M_SEL>, |
| 368 | <&topckgen CK_TOP_NPU_TOPS_SEL>, |
| 369 | <&topckgen CK_TOP_CK_NPU_SEL_CM_TOPS_SEL>; |
| 370 | clock-names = "bus", "sram", "xdma", "offload", "mgmt"; |
| 371 | power-domains = <&topmisc MT7988_POWER_DOMAIN_TOPS0>, |
| 372 | <&topmisc MT7988_POWER_DOMAIN_TOPS1>; |
| 373 | |
| 374 | interrupt-parent = <&gic>; |
| 375 | interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, |
| 376 | <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, |
| 377 | <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>; |
| 378 | interrupt-names = "tdma-tx-pause", "mbox", "wdt"; |
| 379 | |
| 380 | dmas = <&hpdma1 0>; |
| 381 | dma-names = "tnl-sync"; |
| 382 | |
| 383 | fe_mem = <ð>; |
developer | d80acd0 | 2024-02-20 14:28:44 +0800 | [diff] [blame] | 384 | hnat = <&hnat>; |
developer | abfa233 | 2023-08-09 09:11:12 +0800 | [diff] [blame] | 385 | }; |
| 386 | |
| 387 | tops-mbox { |
| 388 | compatible = "mediatek,tops-mbox"; |
| 389 | interrupt-parent = <&gic>; |
| 390 | interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; |
| 391 | interrupt-names = "mbox"; |
| 392 | tops = <&tops>; |
| 393 | }; |
| 394 | |
| 395 | hpdma1: hpdma@09106000 { |
| 396 | compatible = "mediatek,hpdma-top"; |
| 397 | reg = <0 0x09106000 0 0x1000>; |
| 398 | reg-names = "base"; |
| 399 | #dma-cells = <1>; |
| 400 | }; |
| 401 | |
| 402 | hpdma2: hpdma@09606000 { |
| 403 | compatible = "mediatek,hpdma-sub"; |
| 404 | reg = <0 0x09606000 0 0x1000>; |
| 405 | reg-names = "base"; |
| 406 | #dma-cells = <2>; |
| 407 | }; |
| 408 | |
| 409 | tops-ocd@0e500000 { |
| 410 | compatible = "mediatek,tops-ocd"; |
| 411 | reg = <0 0x0e500000 0 0x15000>; |
| 412 | reg-names = "tops-ocd-base"; |
| 413 | clocks = <&infracfg_ao CK_INFRA_AUD_L>; |
| 414 | clock-names = "debugsys"; |
| 415 | }; |
| 416 | |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 417 | watchdog: watchdog@1001c000 { |
| 418 | compatible = "mediatek,mt7622-wdt", |
| 419 | "mediatek,mt6589-wdt", |
| 420 | "syscon"; |
| 421 | reg = <0 0x1001c000 0 0x1000>; |
developer | 0972de7 | 2023-10-11 13:36:28 +0800 | [diff] [blame] | 422 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 423 | #reset-cells = <1>; |
| 424 | }; |
| 425 | |
| 426 | phyfw: phy-firmware@f000000 { |
| 427 | compatible = "mediatek,2p5gphy-fw"; |
developer | e06aa09 | 2023-11-13 17:30:23 +0800 | [diff] [blame] | 428 | reg = <0 0x0f100000 0 0x20000>, |
| 429 | <0 0x0f0f0018 0 0x20>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 430 | }; |
| 431 | |
developer | 2302129 | 2022-10-21 19:10:10 +0800 | [diff] [blame] | 432 | boottrap: boottrap@1001f6f0 { |
| 433 | compatible = "mediatek,boottrap"; |
| 434 | reg = <0 0x1001f6f0 0 0x20>; |
| 435 | }; |
| 436 | |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 437 | gic: interrupt-controller@c000000 { |
| 438 | compatible = "arm,gic-v3"; |
| 439 | #interrupt-cells = <3>; |
| 440 | interrupt-parent = <&gic>; |
| 441 | interrupt-controller; |
| 442 | reg = <0 0x0c000000 0 0x40000>, /* GICD */ |
| 443 | <0 0x0c080000 0 0x200000>; /* GICR */ |
| 444 | |
| 445 | interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| 446 | }; |
| 447 | |
| 448 | trng: trng@1020f000 { |
| 449 | compatible = "mediatek,mt7988-rng"; |
| 450 | }; |
| 451 | |
| 452 | uart0: serial@11000000 { |
| 453 | compatible = "mediatek,mt7986-uart", |
| 454 | "mediatek,mt6577-uart"; |
| 455 | reg = <0 0x11000000 0 0x100>; |
| 456 | interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; |
developer | 23b1e82 | 2022-11-30 13:39:54 +0800 | [diff] [blame] | 457 | clocks = <&infracfg_ao CK_INFRA_52M_UART0_CK>; |
| 458 | clock-names = "bus"; |
| 459 | assigned-clocks = <&topckgen CK_TOP_UART_SEL>, |
| 460 | <&infracfg_ao CK_INFRA_MUX_UART0_SEL>; |
| 461 | assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>, |
| 462 | <&infracfg CK_INFRA_UART_O0>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 463 | status = "disabled"; |
| 464 | }; |
| 465 | |
| 466 | uart1: serial@11000100 { |
| 467 | compatible = "mediatek,mt7986-uart", |
| 468 | "mediatek,mt6577-uart"; |
| 469 | reg = <0 0x11000100 0 0x100>; |
| 470 | interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; |
developer | 23b1e82 | 2022-11-30 13:39:54 +0800 | [diff] [blame] | 471 | clocks = <&infracfg_ao CK_INFRA_52M_UART1_CK>; |
| 472 | clock-names = "bus"; |
| 473 | assigned-clocks = <&topckgen CK_TOP_UART_SEL>, |
| 474 | <&infracfg_ao CK_INFRA_MUX_UART1_SEL>; |
| 475 | assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>, |
| 476 | <&infracfg CK_INFRA_UART_O1>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 477 | status = "disabled"; |
| 478 | }; |
| 479 | |
| 480 | uart2: serial@11000200 { |
| 481 | compatible = "mediatek,mt7986-uart", |
| 482 | "mediatek,mt6577-uart"; |
| 483 | reg = <0 0x11000200 0 0x100>; |
| 484 | interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; |
developer | 23b1e82 | 2022-11-30 13:39:54 +0800 | [diff] [blame] | 485 | clocks = <&infracfg_ao CK_INFRA_52M_UART2_CK>; |
| 486 | clock-names = "bus"; |
| 487 | assigned-clocks = <&topckgen CK_TOP_UART_SEL>, |
| 488 | <&infracfg_ao CK_INFRA_MUX_UART2_SEL>; |
| 489 | assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>, |
| 490 | <&infracfg CK_INFRA_UART_O2>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 491 | status = "disabled"; |
| 492 | }; |
| 493 | |
| 494 | i2c0: i2c@11003000 { |
| 495 | compatible = "mediatek,mt7988-i2c", |
| 496 | "mediatek,mt7981-i2c"; |
| 497 | reg = <0 0x11003000 0 0x1000>, |
| 498 | <0 0x10217080 0 0x80>; |
| 499 | interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; |
| 500 | clock-div = <1>; |
developer | 1fca705 | 2022-12-23 17:57:35 +0800 | [diff] [blame] | 501 | clocks = <&infracfg_ao CK_INFRA_I2C_BCK>, |
| 502 | <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 503 | clock-names = "main", "dma"; |
| 504 | #address-cells = <1>; |
| 505 | #size-cells = <0>; |
| 506 | status = "disabled"; |
| 507 | }; |
| 508 | |
| 509 | i2c1: i2c@11004000 { |
| 510 | compatible = "mediatek,mt7988-i2c", |
| 511 | "mediatek,mt7981-i2c"; |
| 512 | reg = <0 0x11004000 0 0x1000>, |
| 513 | <0 0x10217100 0 0x80>; |
| 514 | interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; |
| 515 | clock-div = <1>; |
developer | 1fca705 | 2022-12-23 17:57:35 +0800 | [diff] [blame] | 516 | clocks = <&infracfg_ao CK_INFRA_I2C_BCK>, |
| 517 | <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 518 | clock-names = "main", "dma"; |
| 519 | #address-cells = <1>; |
| 520 | #size-cells = <0>; |
| 521 | status = "disabled"; |
| 522 | }; |
| 523 | |
| 524 | i2c2: i2c@11005000 { |
| 525 | compatible = "mediatek,mt7988-i2c", |
| 526 | "mediatek,mt7981-i2c"; |
| 527 | reg = <0 0x11005000 0 0x1000>, |
| 528 | <0 0x10217180 0 0x80>; |
| 529 | interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; |
| 530 | clock-div = <1>; |
developer | 1fca705 | 2022-12-23 17:57:35 +0800 | [diff] [blame] | 531 | clocks = <&infracfg_ao CK_INFRA_I2C_BCK>, |
| 532 | <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 533 | clock-names = "main", "dma"; |
| 534 | #address-cells = <1>; |
| 535 | #size-cells = <0>; |
| 536 | status = "disabled"; |
| 537 | }; |
| 538 | |
| 539 | pwm: pwm@10048000 { |
| 540 | compatible = "mediatek,mt7988-pwm"; |
| 541 | reg = <0 0x10048000 0 0x1000>; |
| 542 | #pwm-cells = <2>; |
developer | 1ad6fe4 | 2022-11-02 11:33:26 +0800 | [diff] [blame] | 543 | clocks = <&infracfg_ao CK_INFRA_66M_PWM_BCK>, |
| 544 | <&infracfg_ao CK_INFRA_66M_PWM_HCK>, |
| 545 | <&infracfg_ao CK_INFRA_66M_PWM_CK1>, |
| 546 | <&infracfg_ao CK_INFRA_66M_PWM_CK2>, |
| 547 | <&infracfg_ao CK_INFRA_66M_PWM_CK3>, |
| 548 | <&infracfg_ao CK_INFRA_66M_PWM_CK4>, |
| 549 | <&infracfg_ao CK_INFRA_66M_PWM_CK5>, |
| 550 | <&infracfg_ao CK_INFRA_66M_PWM_CK6>, |
| 551 | <&infracfg_ao CK_INFRA_66M_PWM_CK7>, |
| 552 | <&infracfg_ao CK_INFRA_66M_PWM_CK8>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 553 | clock-names = "top", "main", "pwm1", "pwm2", "pwm3", |
| 554 | "pwm4","pwm5","pwm6","pwm7","pwm8"; |
| 555 | status = "disabled"; |
| 556 | }; |
| 557 | |
| 558 | fan: pwm-fan { |
| 559 | compatible = "pwm-fan"; |
| 560 | /* cooling level (0, 1, 2) : (0% duty, 50% duty, 100% duty) */ |
| 561 | cooling-levels = <0 128 255>; |
| 562 | #cooling-cells = <2>; |
| 563 | #thermal-sensor-cells = <1>; |
| 564 | status = "disabled"; |
| 565 | }; |
| 566 | |
| 567 | lvts: lvts@1100a000 { |
| 568 | compatible = "mediatek,mt7988-lvts"; |
| 569 | #thermal-sensor-cells = <1>; |
| 570 | reg = <0 0x1100a000 0 0x1000>; |
developer | 1bbcf51 | 2022-11-18 16:09:33 +0800 | [diff] [blame] | 571 | clocks = <&infracfg_ao CK_INFRA_26M_THERM_SYSTEM>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 572 | clock-names = "lvts_clk"; |
| 573 | nvmem-cells = <&lvts_calibration>; |
| 574 | nvmem-cell-names = "e_data1"; |
| 575 | }; |
| 576 | |
| 577 | crypto: crypto@15600000 { |
developer | 98c1126 | 2023-08-17 14:31:31 +0800 | [diff] [blame] | 578 | compatible = "inside-secure,safexcel-eip197b", |
| 579 | "security-ip-197-srv"; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 580 | reg = <0 0x15600000 0 0x180000>; |
| 581 | interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, |
| 582 | <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, |
| 583 | <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, |
| 584 | <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>; |
| 585 | interrupt-names = "ring0", "ring1", "ring2", "ring3"; |
| 586 | status = "okay"; |
developer | 98c1126 | 2023-08-17 14:31:31 +0800 | [diff] [blame] | 587 | eth = <ð>; |
developer | ddc0d84 | 2024-02-26 19:01:58 +0800 | [diff] [blame^] | 588 | hnat = <&hnat>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 589 | }; |
| 590 | |
developer | 3594afb | 2022-10-25 13:22:53 +0800 | [diff] [blame] | 591 | afe: audio-controller@11210000 { |
developer | 77fc728 | 2023-11-16 14:34:23 +0800 | [diff] [blame] | 592 | compatible = "mediatek,mt7988-afe", "mediatek,mt7986-afe"; |
developer | 3594afb | 2022-10-25 13:22:53 +0800 | [diff] [blame] | 593 | reg = <0 0x11210000 0 0x9000>; |
| 594 | interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; |
| 595 | clocks = <&infracfg_ao CK_INFRA_66M_AUD_SLV_BCK>, |
| 596 | <&infracfg_ao CK_INFRA_AUD_26M>, |
| 597 | <&infracfg_ao CK_INFRA_AUD_L>, |
| 598 | <&infracfg_ao CK_INFRA_AUD_AUD>, |
| 599 | <&infracfg_ao CK_INFRA_AUD_EG2>, |
| 600 | <&topckgen CK_TOP_AUD_SEL>, |
| 601 | <&topckgen CK_TOP_AUD_I2S_M>; |
| 602 | clock-names = "aud_bus_ck", |
| 603 | "aud_26m_ck", |
| 604 | "aud_l_ck", |
| 605 | "aud_aud_ck", |
| 606 | "aud_eg2_ck", |
| 607 | "aud_sel", |
| 608 | "aud_i2s_m"; |
| 609 | assigned-clocks = <&topckgen CK_TOP_AUD_SEL>, |
| 610 | <&topckgen CK_TOP_A1SYS_SEL>, |
| 611 | <&topckgen CK_TOP_AUD_L_SEL>, |
| 612 | <&topckgen CK_TOP_A_TUNER_SEL>; |
| 613 | assigned-clock-parents = <&topckgen CK_TOP_CB_APLL2_196M>, |
| 614 | <&topckgen CK_TOP_CB_APLL2_D4>, |
| 615 | <&topckgen CK_TOP_CB_APLL2_196M>, |
| 616 | <&topckgen CK_TOP_CB_APLL2_D4>; |
| 617 | status = "disabled"; |
| 618 | }; |
| 619 | |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 620 | pcie0: pcie@11300000 { |
| 621 | compatible = "mediatek,mt7988-pcie", |
| 622 | "mediatek,mt7986-pcie"; |
| 623 | device_type = "pci"; |
| 624 | #address-cells = <3>; |
| 625 | #size-cells = <2>; |
| 626 | reg = <0 0x11300000 0 0x2000>; |
| 627 | reg-names = "pcie-mac"; |
| 628 | linux,pci-domain = <0>; |
| 629 | interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; |
| 630 | bus-range = <0x00 0xff>; |
| 631 | ranges = <0x81000000 0x00 0x30000000 0x00 |
| 632 | 0x30000000 0x00 0x00200000>, |
| 633 | <0x82000000 0x00 0x30200000 0x00 |
| 634 | 0x30200000 0x00 0x07e00000>; |
developer | ca2082b | 2022-11-01 11:23:49 +0800 | [diff] [blame] | 635 | clocks = <&infracfg_ao CK_INFRA_PCIE_PIPE_P0>, |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 636 | <&infracfg_ao CK_INFRA_PCIE_GFMUX_TL_P0>, |
developer | ca2082b | 2022-11-01 11:23:49 +0800 | [diff] [blame] | 637 | <&infracfg_ao CK_INFRA_PCIE_PERI_26M_CK_P0>, |
| 638 | <&infracfg_ao CK_INFRA_133M_PCIE_CK_P0>; |
| 639 | clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m"; |
| 640 | status = "disabled"; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 641 | |
| 642 | #interrupt-cells = <1>; |
| 643 | interrupt-map-mask = <0 0 0 0x7>; |
| 644 | interrupt-map = <0 0 0 1 &pcie_intc0 0>, |
| 645 | <0 0 0 2 &pcie_intc0 1>, |
| 646 | <0 0 0 3 &pcie_intc0 2>, |
| 647 | <0 0 0 4 &pcie_intc0 3>; |
| 648 | pcie_intc0: interrupt-controller { |
| 649 | #address-cells = <0>; |
| 650 | #interrupt-cells = <1>; |
| 651 | interrupt-controller; |
| 652 | }; |
developer | de8a106 | 2023-01-31 17:00:33 +0800 | [diff] [blame] | 653 | |
| 654 | slot0: pcie@0,0 { |
| 655 | reg = <0x0000 0 0 0 0>; |
| 656 | }; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 657 | }; |
| 658 | |
| 659 | pcie1: pcie@11310000 { |
| 660 | compatible = "mediatek,mt7988-pcie", |
| 661 | "mediatek,mt7986-pcie"; |
| 662 | device_type = "pci"; |
| 663 | #address-cells = <3>; |
| 664 | #size-cells = <2>; |
| 665 | reg = <0 0x11310000 0 0x2000>; |
| 666 | reg-names = "pcie-mac"; |
| 667 | linux,pci-domain = <1>; |
| 668 | interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; |
| 669 | bus-range = <0x00 0xff>; |
| 670 | ranges = <0x81000000 0x00 0x38000000 0x00 |
| 671 | 0x38000000 0x00 0x00200000>, |
| 672 | <0x82000000 0x00 0x38200000 0x00 |
| 673 | 0x38200000 0x00 0x07e00000>; |
developer | ca2082b | 2022-11-01 11:23:49 +0800 | [diff] [blame] | 674 | clocks = <&infracfg_ao CK_INFRA_PCIE_PIPE_P1>, |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 675 | <&infracfg_ao CK_INFRA_PCIE_GFMUX_TL_P1>, |
developer | ca2082b | 2022-11-01 11:23:49 +0800 | [diff] [blame] | 676 | <&infracfg_ao CK_INFRA_PCIE_PERI_26M_CK_P1>, |
| 677 | <&infracfg_ao CK_INFRA_133M_PCIE_CK_P1>; |
| 678 | clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m"; |
| 679 | status = "disabled"; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 680 | |
| 681 | #interrupt-cells = <1>; |
| 682 | interrupt-map-mask = <0 0 0 0x7>; |
| 683 | interrupt-map = <0 0 0 1 &pcie_intc1 0>, |
| 684 | <0 0 0 2 &pcie_intc1 1>, |
| 685 | <0 0 0 3 &pcie_intc1 2>, |
| 686 | <0 0 0 4 &pcie_intc1 3>; |
| 687 | pcie_intc1: interrupt-controller { |
| 688 | #address-cells = <0>; |
| 689 | #interrupt-cells = <1>; |
| 690 | interrupt-controller; |
| 691 | }; |
developer | e36c762 | 2023-10-04 15:22:00 +0800 | [diff] [blame] | 692 | |
| 693 | slot1: pcie@0,0 { |
| 694 | reg = <0x0000 0 0 0 0>; |
| 695 | }; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 696 | }; |
| 697 | |
| 698 | pcie2: pcie@11280000 { |
| 699 | compatible = "mediatek,mt7988-pcie", |
| 700 | "mediatek,mt7986-pcie"; |
| 701 | device_type = "pci"; |
| 702 | #address-cells = <3>; |
| 703 | #size-cells = <2>; |
| 704 | reg = <0 0x11280000 0 0x2000>; |
| 705 | reg-names = "pcie-mac"; |
| 706 | linux,pci-domain = <3>; |
| 707 | interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; |
| 708 | bus-range = <0x00 0xff>; |
| 709 | ranges = <0x81000000 0x00 0x20000000 0x00 |
| 710 | 0x20000000 0x00 0x00200000>, |
| 711 | <0x82000000 0x00 0x20200000 0x00 |
| 712 | 0x20200000 0x00 0x07e00000>; |
developer | ca2082b | 2022-11-01 11:23:49 +0800 | [diff] [blame] | 713 | clocks = <&infracfg_ao CK_INFRA_PCIE_PIPE_P2>, |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 714 | <&infracfg_ao CK_INFRA_PCIE_GFMUX_TL_P2>, |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 715 | <&infracfg_ao CK_INFRA_PCIE_PERI_26M_CK_P2>, |
developer | ca2082b | 2022-11-01 11:23:49 +0800 | [diff] [blame] | 716 | <&infracfg_ao CK_INFRA_133M_PCIE_CK_P2>; |
| 717 | clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m"; |
| 718 | status = "disabled"; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 719 | |
| 720 | phys = <&xphyu3port0 PHY_TYPE_PCIE>; |
| 721 | phy-names = "pcie-phy"; |
| 722 | |
| 723 | #interrupt-cells = <1>; |
| 724 | interrupt-map-mask = <0 0 0 0x7>; |
| 725 | interrupt-map = <0 0 0 1 &pcie_intc2 0>, |
| 726 | <0 0 0 2 &pcie_intc2 1>, |
| 727 | <0 0 0 3 &pcie_intc2 2>, |
| 728 | <0 0 0 4 &pcie_intc2 3>; |
| 729 | pcie_intc2: interrupt-controller { |
| 730 | #address-cells = <0>; |
| 731 | #interrupt-cells = <1>; |
| 732 | interrupt-controller; |
| 733 | }; |
| 734 | }; |
| 735 | |
| 736 | pcie3: pcie@11290000 { |
| 737 | compatible = "mediatek,mt7988-pcie", |
| 738 | "mediatek,mt7986-pcie"; |
| 739 | device_type = "pci"; |
| 740 | #address-cells = <3>; |
| 741 | #size-cells = <2>; |
| 742 | reg = <0 0x11290000 0 0x2000>; |
| 743 | reg-names = "pcie-mac"; |
| 744 | linux,pci-domain = <2>; |
| 745 | interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; |
| 746 | bus-range = <0x00 0xff>; |
| 747 | ranges = <0x81000000 0x00 0x28000000 0x00 |
| 748 | 0x28000000 0x00 0x00200000>, |
| 749 | <0x82000000 0x00 0x28200000 0x00 |
| 750 | 0x28200000 0x00 0x07e00000>; |
developer | ca2082b | 2022-11-01 11:23:49 +0800 | [diff] [blame] | 751 | clocks = <&infracfg_ao CK_INFRA_PCIE_PIPE_P3>, |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 752 | <&infracfg_ao CK_INFRA_PCIE_GFMUX_TL_P3>, |
developer | ca2082b | 2022-11-01 11:23:49 +0800 | [diff] [blame] | 753 | <&infracfg_ao CK_INFRA_PCIE_PERI_26M_CK_P3>, |
| 754 | <&infracfg_ao CK_INFRA_133M_PCIE_CK_P3>; |
| 755 | clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m"; |
| 756 | status = "disabled"; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 757 | |
| 758 | #interrupt-cells = <1>; |
| 759 | interrupt-map-mask = <0 0 0 0x7>; |
| 760 | interrupt-map = <0 0 0 1 &pcie_intc3 0>, |
| 761 | <0 0 0 2 &pcie_intc3 1>, |
| 762 | <0 0 0 3 &pcie_intc3 2>, |
| 763 | <0 0 0 4 &pcie_intc3 3>; |
| 764 | pcie_intc3: interrupt-controller { |
| 765 | #address-cells = <0>; |
| 766 | #interrupt-cells = <1>; |
| 767 | interrupt-controller; |
| 768 | }; |
| 769 | }; |
| 770 | |
| 771 | pio: pinctrl@1001f000 { |
| 772 | compatible = "mediatek,mt7988-pinctrl"; |
| 773 | reg = <0 0x1001f000 0 0x1000>, |
| 774 | <0 0x11c10000 0 0x1000>, |
| 775 | <0 0x11d00000 0 0x1000>, |
| 776 | <0 0x11d20000 0 0x1000>, |
| 777 | <0 0x11e00000 0 0x1000>, |
| 778 | <0 0x11f00000 0 0x1000>, |
| 779 | <0 0x1000b000 0 0x1000>; |
| 780 | reg-names = "gpio_base", "iocfg_tr_base", "iocfg_br_base", |
| 781 | "iocfg_rb_base", "iocfg_lb_base", "iocfg_tl_base", |
| 782 | "eint"; |
| 783 | gpio-controller; |
| 784 | #gpio-cells = <2>; |
developer | d73d053 | 2023-06-09 15:41:43 +0800 | [diff] [blame] | 785 | gpio-ranges = <&pio 0 0 84>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 786 | interrupt-controller; |
developer | a9e4114 | 2022-11-01 09:46:14 +0800 | [diff] [blame] | 787 | interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 788 | interrupt-parent = <&gic>; |
| 789 | #interrupt-cells = <2>; |
| 790 | }; |
| 791 | |
| 792 | ethsys: syscon@15000000 { |
| 793 | #address-cells = <1>; |
| 794 | #size-cells = <1>; |
| 795 | compatible = "mediatek,mt7988-ethsys", |
| 796 | "syscon"; |
| 797 | reg = <0 0x15000000 0 0x1000>; |
| 798 | #clock-cells = <1>; |
| 799 | #reset-cells = <1>; |
| 800 | |
| 801 | ethsysrst: reset-controller { |
| 802 | compatible = "ti,syscon-reset"; |
| 803 | #reset-cells = <1>; |
| 804 | ti,reset-bits = |
| 805 | <0x34 4 0x34 4 0x34 4 |
| 806 | (ASSERT_SET | DEASSERT_CLEAR | STATUS_SET)>; |
| 807 | }; |
| 808 | }; |
| 809 | |
| 810 | ethwarp: syscon@15031000 { |
| 811 | compatible = "mediatek,mt7988-ethwarp", "syscon"; |
| 812 | reg = <0 0x15031000 0 0x1000>; |
| 813 | #clock-cells = <1>; |
| 814 | }; |
| 815 | |
| 816 | switch0: switch0@15020000 { |
| 817 | #address-cells = <1>; |
| 818 | #size-cells = <1>; |
| 819 | compatible = "mediatek,mt7988-switch", "syscon"; |
| 820 | reg = <0 0x15020000 0 0x8000>; |
| 821 | }; |
| 822 | |
| 823 | eth: ethernet@15100000 { |
| 824 | compatible = "mediatek,mt7988-eth"; |
| 825 | reg = <0 0x15100000 0 0x80000>, |
| 826 | <0 0x15400000 0 0x380000>; |
developer | 94806ec | 2023-05-19 14:16:44 +0800 | [diff] [blame] | 827 | interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, |
| 828 | <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, |
| 829 | <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, |
| 830 | <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, |
| 831 | <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 832 | <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, |
| 833 | <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, |
| 834 | <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; |
developer | 1bbcf51 | 2022-11-18 16:09:33 +0800 | [diff] [blame] | 835 | clocks = <ðsys CK_ETHDMA_XGP1_EN>, |
| 836 | <ðsys CK_ETHDMA_XGP2_EN>, |
| 837 | <ðsys CK_ETHDMA_XGP3_EN>, |
| 838 | <ðsys CK_ETHDMA_FE_EN>, |
| 839 | <ðsys CK_ETHDMA_GP2_EN>, |
| 840 | <ðsys CK_ETHDMA_GP1_EN>, |
| 841 | <ðsys CK_ETHDMA_GP3_EN>, |
| 842 | <ðsys CK_ETHDMA_ESW_EN>, |
| 843 | <ðsys CK_ETHDMA_CRYPT0_EN>, |
| 844 | <&sgmiisys0 CK_SGM0_TX_EN>, |
| 845 | <&sgmiisys0 CK_SGM0_RX_EN>, |
| 846 | <&sgmiisys1 CK_SGM1_TX_EN>, |
| 847 | <&sgmiisys1 CK_SGM1_RX_EN>, |
developer | 5cfc67a | 2022-12-29 19:06:51 +0800 | [diff] [blame] | 848 | <ðwarp CK_ETHWARP_WOCPU2_EN>, |
| 849 | <ðwarp CK_ETHWARP_WOCPU1_EN>, |
| 850 | <ðwarp CK_ETHWARP_WOCPU0_EN>, |
developer | 1bbcf51 | 2022-11-18 16:09:33 +0800 | [diff] [blame] | 851 | <&topckgen CK_TOP_USXGMII_SBUS_0_SEL>, |
| 852 | <&topckgen CK_TOP_USXGMII_SBUS_1_SEL>, |
| 853 | <&topckgen CK_TOP_SGM_0_SEL>, |
developer | 5cfc67a | 2022-12-29 19:06:51 +0800 | [diff] [blame] | 854 | <&topckgen CK_TOP_SGM_1_SEL>, |
| 855 | <&topckgen CK_TOP_XFI_PHY_0_XTAL_SEL>, |
| 856 | <&topckgen CK_TOP_XFI_PHY_1_XTAL_SEL>, |
| 857 | <&topckgen CK_TOP_ETH_GMII_SEL>, |
| 858 | <&topckgen CK_TOP_ETH_REFCK_50M_SEL>, |
| 859 | <&topckgen CK_TOP_ETH_SYS_200M_SEL>, |
| 860 | <&topckgen CK_TOP_ETH_SYS_SEL>, |
| 861 | <&topckgen CK_TOP_ETH_XGMII_SEL>, |
| 862 | <&topckgen CK_TOP_ETH_MII_SEL>, |
| 863 | <&topckgen CK_TOP_NETSYS_SEL>, |
| 864 | <&topckgen CK_TOP_NETSYS_500M_SEL>, |
| 865 | <&topckgen CK_TOP_NETSYS_PAO_2X_SEL>, |
| 866 | <&topckgen CK_TOP_NETSYS_SYNC_250M_SEL>, |
| 867 | <&topckgen CK_TOP_NETSYS_PPEFB_250M_SEL>, |
developer | 0e36298 | 2024-01-04 11:04:10 +0800 | [diff] [blame] | 868 | <&topckgen CK_TOP_NETSYS_WARP_SEL>, |
developer | a4f5219 | 2024-02-26 15:31:13 +0800 | [diff] [blame] | 869 | <&topckgen CK_TOP_MACSEC_SEL>; |
developer | 1bbcf51 | 2022-11-18 16:09:33 +0800 | [diff] [blame] | 870 | clock-names = "xgp1", "xgp2", "xgp3", "fe", "gp2", "gp1", |
| 871 | "gp3", "esw", "crypto", "sgmii_tx250m", |
| 872 | "sgmii_rx250m", "sgmii2_tx250m", "sgmii2_rx250m", |
developer | 5cfc67a | 2022-12-29 19:06:51 +0800 | [diff] [blame] | 873 | "ethwarp_wocpu2", "ethwarp_wocpu1", |
| 874 | "ethwarp_wocpu0", "top_usxgmii0_sel", |
| 875 | "top_usxgmii1_sel", "top_sgm0_sel", |
| 876 | "top_sgm1_sel", "top_xfi_phy0_xtal_sel", |
| 877 | "top_xfi_phy1_xtal_sel", "top_eth_gmii_sel", |
| 878 | "top_eth_refck_50m_sel", "top_eth_sys_200m_sel", |
| 879 | "top_eth_sys_sel", "top_eth_xgmii_sel", |
| 880 | "top_eth_mii_sel", "top_netsys_sel", |
| 881 | "top_netsys_500m_sel", "top_netsys_pao_2x_sel", |
| 882 | "top_netsys_sync_250m_sel", |
| 883 | "top_netsys_ppefb_250m_sel", |
developer | 0e36298 | 2024-01-04 11:04:10 +0800 | [diff] [blame] | 884 | "top_netsys_warp_sel", |
developer | a4f5219 | 2024-02-26 15:31:13 +0800 | [diff] [blame] | 885 | "top_macsec_sel"; |
developer | 1bbcf51 | 2022-11-18 16:09:33 +0800 | [diff] [blame] | 886 | assigned-clocks = <&topckgen CK_TOP_NETSYS_2X_SEL>, |
| 887 | <&topckgen CK_TOP_NETSYS_GSW_SEL>, |
| 888 | <&topckgen CK_TOP_USXGMII_SBUS_0_SEL>, |
| 889 | <&topckgen CK_TOP_USXGMII_SBUS_1_SEL>, |
| 890 | <&topckgen CK_TOP_SGM_0_SEL>, |
developer | 0e36298 | 2024-01-04 11:04:10 +0800 | [diff] [blame] | 891 | <&topckgen CK_TOP_SGM_1_SEL>, |
developer | a4f5219 | 2024-02-26 15:31:13 +0800 | [diff] [blame] | 892 | <&topckgen CK_TOP_MACSEC_SEL>; |
developer | 1bbcf51 | 2022-11-18 16:09:33 +0800 | [diff] [blame] | 893 | assigned-clock-parents = <&topckgen CK_TOP_CB_NET2_800M>, |
| 894 | <&topckgen CK_TOP_CB_NET1_D4>, |
| 895 | <&topckgen CK_TOP_NET1_D8_D4>, |
| 896 | <&topckgen CK_TOP_NET1_D8_D4>, |
| 897 | <&topckgen CK_TOP_CB_SGM_325M>, |
developer | 0e36298 | 2024-01-04 11:04:10 +0800 | [diff] [blame] | 898 | <&topckgen CK_TOP_CB_SGM_325M>, |
developer | a4f5219 | 2024-02-26 15:31:13 +0800 | [diff] [blame] | 899 | <&topckgen CK_TOP_CB_SGM_325M>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 900 | mediatek,ethsys = <ðsys>; |
| 901 | mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; |
| 902 | mediatek,usxgmiisys = <&usxgmiisys0>, <&usxgmiisys1>; |
| 903 | mediatek,xfi_pextp = <&xfi_pextp0>, <&xfi_pextp1>; |
| 904 | mediatek,xfi_pll = <&xfi_pll>; |
| 905 | mediatek,infracfg = <&topmisc>; |
| 906 | mediatek,toprgu = <&watchdog>; |
developer | 0fef522 | 2023-04-26 14:48:31 +0800 | [diff] [blame] | 907 | mediatek,hwver = <&hwver>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 908 | #reset-cells = <1>; |
| 909 | #address-cells = <1>; |
| 910 | #size-cells = <0>; |
| 911 | status = "disabled"; |
| 912 | }; |
| 913 | |
| 914 | hnat: hnat@15000000 { |
| 915 | compatible = "mediatek,mtk-hnat_v5"; |
| 916 | reg = <0 0x15100000 0 0x80000>; |
| 917 | resets = <ðsys 0>; |
| 918 | reset-names = "mtketh"; |
| 919 | status = "disabled"; |
| 920 | }; |
| 921 | |
developer | abfa233 | 2023-08-09 09:11:12 +0800 | [diff] [blame] | 922 | pce: pce@15100000 { |
| 923 | compatible = "mediatek,pce"; |
| 924 | |
| 925 | fe_mem = <ð>; |
| 926 | }; |
| 927 | |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 928 | sgmiisys0: syscon@10060000 { |
| 929 | compatible = "mediatek,mt7988-sgmiisys", |
| 930 | "mediatek,mt7988-sgmiisys_0", |
| 931 | "syscon"; |
| 932 | reg = <0 0x10060000 0 0x1000>; |
| 933 | #clock-cells = <1>; |
| 934 | }; |
| 935 | |
| 936 | sgmiisys1: syscon@10070000 { |
| 937 | compatible = "mediatek,mt7988-sgmiisys", |
| 938 | "mediatek,mt7988-sgmiisys_1", |
| 939 | "syscon"; |
| 940 | reg = <0 0x10070000 0 0x1000>; |
| 941 | #clock-cells = <1>; |
| 942 | }; |
| 943 | |
| 944 | usxgmiisys0: usxgmiisys@10080000 { |
| 945 | compatible = "mediatek,mt7988-usxgmiisys", |
| 946 | "mediatek,mt7988-usxgmiisys_0", |
| 947 | "syscon"; |
| 948 | reg = <0 0x10080000 0 0x1000>; |
| 949 | #clock-cells = <1>; |
| 950 | }; |
| 951 | |
| 952 | usxgmiisys1: usxgmiisys@10081000 { |
| 953 | compatible = "mediatek,mt7988-usxgmiisys", |
| 954 | "mediatek,mt7988-usxgmiisys_1", |
| 955 | "syscon"; |
| 956 | reg = <0 0x10081000 0 0x1000>; |
| 957 | #clock-cells = <1>; |
| 958 | }; |
| 959 | |
| 960 | xfi_pextp0: xfi_pextp@11f20000 { |
| 961 | compatible = "mediatek,mt7988-xfi_pextp", |
| 962 | "mediatek,mt7988-xfi_pextp_0", |
| 963 | "syscon"; |
| 964 | reg = <0 0x11f20000 0 0x10000>; |
| 965 | #clock-cells = <1>; |
| 966 | }; |
| 967 | |
| 968 | xfi_pextp1: xfi_pextp@11f30000 { |
| 969 | compatible = "mediatek,mt7988-xfi_pextp", |
| 970 | "mediatek,mt7988-xfi_pextp_1", |
| 971 | "syscon"; |
| 972 | reg = <0 0x11f30000 0 0x10000>; |
| 973 | #clock-cells = <1>; |
| 974 | }; |
| 975 | |
| 976 | xfi_pll: xfi_pll@11f40000 { |
| 977 | compatible = "mediatek,mt7988-xfi_pll", "syscon"; |
| 978 | reg = <0 0x11f40000 0 0x1000>; |
| 979 | #clock-cells = <1>; |
| 980 | }; |
| 981 | |
| 982 | topmisc: topmisc@11d10000 { |
| 983 | compatible = "mediatek,mt7988-topmisc", "syscon", |
| 984 | "mediatek,mt7988-power-controller"; |
| 985 | reg = <0 0x11d10000 0 0x10000>; |
| 986 | #clock-cells = <1>; |
| 987 | #power-domain-cells = <1>; |
| 988 | #address-cells = <1>; |
| 989 | #size-cells = <0>; |
| 990 | /* power domain of the SoC */ |
| 991 | tops0@MT7988_POWER_DOMAIN_TOPS0 { |
| 992 | reg = <MT7988_POWER_DOMAIN_TOPS0>; |
| 993 | #power-domain-cells = <0>; |
| 994 | }; |
| 995 | tops1@MT7988_POWER_DOMAIN_TOPS1 { |
| 996 | reg = <MT7988_POWER_DOMAIN_TOPS1>; |
| 997 | #power-domain-cells = <0>; |
| 998 | }; |
| 999 | eth2p5@MT7988_POWER_DOMAIN_ETH2P5 { |
| 1000 | reg = <MT7988_POWER_DOMAIN_ETH2P5>; |
| 1001 | #power-domain-cells = <0>; |
| 1002 | }; |
| 1003 | }; |
| 1004 | |
| 1005 | snand: snfi@11001000 { |
developer | 54193ba | 2022-11-25 18:43:24 +0800 | [diff] [blame] | 1006 | compatible = "mediatek,mt7988-snand"; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 1007 | reg = <0 0x11001000 0 0x1000>, <0 0x11002000 0 0x1000>; |
| 1008 | reg-names = "nfi", "ecc"; |
| 1009 | interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; |
developer | 54193ba | 2022-11-25 18:43:24 +0800 | [diff] [blame] | 1010 | clocks = <&infracfg_ao CK_INFRA_SPINFI>, |
| 1011 | <&infracfg_ao CK_INFRA_NFI>; |
| 1012 | clock-names = "pad_clk", "nfi_clk"; |
| 1013 | assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>, |
| 1014 | <&topckgen CK_TOP_NFI1X_SEL>; |
| 1015 | assigned-clock-parents = <&topckgen CK_TOP_CB_M_D8>, |
| 1016 | <&topckgen CK_TOP_CB_M_D8>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 1017 | #address-cells = <1>; |
| 1018 | #size-cells = <0>; |
| 1019 | status = "disabled"; |
| 1020 | }; |
| 1021 | |
| 1022 | wbsys: wbsys@18000000 { |
| 1023 | compatible = "mediatek,wbsys"; |
| 1024 | reg = <0 0x18000000 0 0x1000000>; |
| 1025 | linux,pci-domain = <4>; |
| 1026 | interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, |
| 1027 | <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, |
| 1028 | <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, |
| 1029 | <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; |
| 1030 | chip_id = <0x7981>; |
| 1031 | }; |
| 1032 | |
| 1033 | wed_pcie: wed_pcie@10003000 { |
| 1034 | compatible = "mediatek,wed_pcie"; |
| 1035 | reg = <0 0x10003000 0 0x10>; |
| 1036 | }; |
| 1037 | |
developer | 4c9c1c1 | 2022-11-02 11:30:47 +0800 | [diff] [blame] | 1038 | infra_bus_prot: infra_bus_prot@1000310c { |
| 1039 | compatible = "mediatek,infracfg_ao_bus_hang_prot"; |
| 1040 | reg = <0 0x1000310c 0 0x14>; |
| 1041 | }; |
| 1042 | |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 1043 | spi0: spi@11007000 { |
| 1044 | compatible = "mediatek,ipm-spi-quad"; |
| 1045 | reg = <0 0x11007000 0 0x100>; |
| 1046 | interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; |
| 1047 | clocks = <&topckgen CK_TOP_CB_M_D2>, |
| 1048 | <&topckgen CK_TOP_SPI_SEL>, |
| 1049 | <&infracfg_ao CK_INFRA_104M_SPI0>, |
| 1050 | <&infracfg_ao CK_INFRA_66M_SPI0_HCK>; |
| 1051 | clock-names = "parent-clk", "sel-clk", "spi-clk", "spi-hclk"; |
| 1052 | status = "disabled"; |
| 1053 | }; |
| 1054 | |
| 1055 | spi1: spi@11008000 { |
| 1056 | compatible = "mediatek,ipm-spi-single"; |
| 1057 | reg = <0 0x11008000 0 0x100>; |
| 1058 | interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; |
| 1059 | clocks = <&topckgen CK_TOP_CB_M_D2>, |
| 1060 | <&topckgen CK_TOP_SPI_SEL>, |
| 1061 | <&infracfg_ao CK_INFRA_104M_SPI1>, |
| 1062 | <&infracfg_ao CK_INFRA_66M_SPI1_HCK>; |
| 1063 | clock-names = "parent-clk", "sel-clk", "spi-clk", "spi-hclk"; |
| 1064 | status = "disabled"; |
| 1065 | }; |
| 1066 | |
| 1067 | spi2: spi@11009000 { |
| 1068 | compatible = "mediatek,ipm-spi-quad"; |
| 1069 | reg = <0 0x11009000 0 0x100>; |
| 1070 | interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; |
| 1071 | clocks = <&topckgen CK_TOP_CB_M_D2>, |
| 1072 | <&topckgen CK_TOP_SPI_SEL>, |
| 1073 | <&infracfg_ao CK_INFRA_104M_SPI2_BCK>, |
| 1074 | <&infracfg_ao CK_INFRA_66M_SPI2_HCK>; |
| 1075 | clock-names = "parent-clk", "sel-clk", "spi-clk", "spi-hclk"; |
| 1076 | status = "disabled"; |
| 1077 | }; |
| 1078 | |
| 1079 | consys: consys@10000000 { |
| 1080 | compatible = "mediatek,mt7981-consys"; |
| 1081 | reg = <0 0x10000000 0 0x8600000>; |
| 1082 | memory-region = <&wmcpu_emi>; |
| 1083 | }; |
| 1084 | |
| 1085 | xhci0: xhci@11190000 { |
| 1086 | compatible = "mediatek,mt7988-xhci", |
| 1087 | "mediatek,mtk-xhci"; |
| 1088 | reg = <0 0x11190000 0 0x2e00>, |
| 1089 | <0 0x11193e00 0 0x0100>; |
| 1090 | reg-names = "mac", "ippc"; |
| 1091 | interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; |
| 1092 | phys = <&xphyu2port0 PHY_TYPE_USB2>, |
| 1093 | <&xphyu3port0 PHY_TYPE_USB3>; |
developer | c52bff4 | 2022-11-18 15:25:28 +0800 | [diff] [blame] | 1094 | clocks = <&infracfg_ao CK_INFRA_USB_SYS>, |
| 1095 | <&infracfg_ao CK_INFRA_USB_XHCI>, |
| 1096 | <&infracfg_ao CK_INFRA_USB_REF>, |
| 1097 | <&infracfg_ao CK_INFRA_66M_USB_HCK>, |
| 1098 | <&infracfg_ao CK_INFRA_133M_USB_HCK>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 1099 | clock-names = "sys_ck", |
| 1100 | "xhci_ck", |
| 1101 | "ref_ck", |
| 1102 | "mcu_ck", |
| 1103 | "dma_ck"; |
| 1104 | #address-cells = <2>; |
| 1105 | #size-cells = <2>; |
developer | 8cdcb26 | 2022-10-27 14:36:15 +0800 | [diff] [blame] | 1106 | mediatek,p0_speed_fixup; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 1107 | status = "okay"; |
| 1108 | }; |
| 1109 | |
| 1110 | usbxphy: usb-phy@11e10000 { |
| 1111 | compatible = "mediatek,mt7988", |
| 1112 | "mediatek,xsphy"; |
| 1113 | #address-cells = <2>; |
| 1114 | #size-cells = <2>; |
| 1115 | ranges; |
| 1116 | status = "okay"; |
| 1117 | |
| 1118 | xphyu2port0: usb-phy@11e10000 { |
| 1119 | reg = <0 0x11e10000 0 0x400>; |
developer | c52bff4 | 2022-11-18 15:25:28 +0800 | [diff] [blame] | 1120 | clocks = <&infracfg_ao CK_INFRA_USB_UTMI>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 1121 | clock-names = "ref"; |
| 1122 | #phy-cells = <1>; |
| 1123 | status = "okay"; |
| 1124 | }; |
| 1125 | |
| 1126 | xphyu3port0: usb-phy@11e13000 { |
| 1127 | reg = <0 0x11e13400 0 0x500>; |
developer | c52bff4 | 2022-11-18 15:25:28 +0800 | [diff] [blame] | 1128 | clocks = <&infracfg_ao CK_INFRA_USB_PIPE>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 1129 | clock-names = "ref"; |
| 1130 | #phy-cells = <1>; |
| 1131 | mediatek,syscon-type = <&topmisc 0x218 0>; |
| 1132 | status = "okay"; |
| 1133 | }; |
| 1134 | }; |
| 1135 | |
| 1136 | xhci1: xhci@11200000 { |
| 1137 | compatible = "mediatek,mt7988-xhci", |
| 1138 | "mediatek,mtk-xhci"; |
| 1139 | reg = <0 0x11200000 0 0x2e00>, |
| 1140 | <0 0x11203e00 0 0x0100>; |
| 1141 | reg-names = "mac", "ippc"; |
| 1142 | interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; |
| 1143 | phys = <&tphyu2port0 PHY_TYPE_USB2>, |
| 1144 | <&tphyu3port0 PHY_TYPE_USB3>; |
developer | c52bff4 | 2022-11-18 15:25:28 +0800 | [diff] [blame] | 1145 | clocks = <&infracfg_ao CK_INFRA_USB_SYS_CK_P1>, |
| 1146 | <&infracfg_ao CK_INFRA_USB_XHCI_CK_P1>, |
| 1147 | <&infracfg_ao CK_INFRA_USB_CK_P1>, |
| 1148 | <&infracfg_ao CK_INFRA_66M_USB_HCK_CK_P1>, |
| 1149 | <&infracfg_ao CK_INFRA_133M_USB_HCK_CK_P1>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 1150 | clock-names = "sys_ck", |
| 1151 | "xhci_ck", |
| 1152 | "ref_ck", |
| 1153 | "mcu_ck", |
| 1154 | "dma_ck"; |
| 1155 | #address-cells = <2>; |
| 1156 | #size-cells = <2>; |
| 1157 | status = "okay"; |
| 1158 | }; |
| 1159 | |
| 1160 | usbtphy: usb-phy@11c50000 { |
| 1161 | compatible = "mediatek,mt7988", |
| 1162 | "mediatek,generic-tphy-v2"; |
| 1163 | #address-cells = <2>; |
| 1164 | #size-cells = <2>; |
| 1165 | ranges; |
| 1166 | status = "okay"; |
| 1167 | |
| 1168 | tphyu2port0: usb-phy@11c50000 { |
| 1169 | reg = <0 0x11c50000 0 0x700>; |
developer | c52bff4 | 2022-11-18 15:25:28 +0800 | [diff] [blame] | 1170 | clocks = <&infracfg_ao CK_INFRA_USB_UTMI_CK_P1>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 1171 | clock-names = "ref"; |
| 1172 | #phy-cells = <1>; |
| 1173 | status = "okay"; |
| 1174 | }; |
| 1175 | |
| 1176 | tphyu3port0: usb-phy@11c50700 { |
| 1177 | reg = <0 0x11c50700 0 0x900>; |
developer | c52bff4 | 2022-11-18 15:25:28 +0800 | [diff] [blame] | 1178 | clocks = <&infracfg_ao CK_INFRA_USB_PIPE_CK_P1>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 1179 | clock-names = "ref"; |
| 1180 | #phy-cells = <1>; |
developer | 8cdcb26 | 2022-10-27 14:36:15 +0800 | [diff] [blame] | 1181 | mediatek,usb3-pll-ssc-delta; |
| 1182 | mediatek,usb3-pll-ssc-delta1; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 1183 | status = "okay"; |
| 1184 | }; |
| 1185 | }; |
| 1186 | |
| 1187 | clk40m: oscillator@0 { |
| 1188 | compatible = "fixed-clock"; |
| 1189 | #clock-cells = <0>; |
| 1190 | clock-frequency = <40000000>; |
| 1191 | clock-output-names = "clkxtal"; |
| 1192 | }; |
| 1193 | |
| 1194 | infracfg_ao: infracfg_ao@10001000 { |
| 1195 | compatible = "mediatek,mt7988-infracfg_ao", "syscon"; |
| 1196 | reg = <0 0x10001000 0 0x1000>; |
| 1197 | #clock-cells = <1>; |
| 1198 | }; |
| 1199 | |
| 1200 | infracfg: infracfg@10209000 { |
| 1201 | compatible = "mediatek,mt7988-infracfg", "syscon"; |
| 1202 | reg = <0 0x10209000 0 0x1000>; |
| 1203 | #clock-cells = <1>; |
| 1204 | }; |
| 1205 | |
| 1206 | topckgen: topckgen@1001B000 { |
| 1207 | compatible = "mediatek,mt7988-topckgen", "syscon"; |
| 1208 | reg = <0 0x1001B000 0 0x1000>; |
| 1209 | #clock-cells = <1>; |
| 1210 | }; |
| 1211 | |
| 1212 | apmixedsys: apmixedsys@1001E000 { |
| 1213 | compatible = "mediatek,mt7988-apmixedsys", "syscon"; |
| 1214 | reg = <0 0x1001E000 0 0x1000>; |
| 1215 | #clock-cells = <1>; |
| 1216 | }; |
| 1217 | |
| 1218 | mcusys: mcusys@100E0000 { |
| 1219 | compatible = "mediatek,mt7988-mcusys", "syscon"; |
| 1220 | reg = <0 0x100E0000 0 0x1000>; |
| 1221 | #clock-cells = <1>; |
| 1222 | }; |
| 1223 | |
| 1224 | clkitg: clkitg { |
| 1225 | compatible = "simple-bus"; |
| 1226 | }; |
| 1227 | |
| 1228 | efuse: efuse@11f50000 { |
| 1229 | compatible = "mediatek,efuse"; |
| 1230 | reg = <0 0x11f50000 0 0x1000>; |
| 1231 | #address-cells = <1>; |
| 1232 | #size-cells = <1>; |
| 1233 | |
| 1234 | lvts_calibration: calib@918 { |
| 1235 | reg = <0x918 0x28>; |
| 1236 | }; |
| 1237 | phy_calibration_p0: calib@940 { |
| 1238 | reg = <0x940 0x10>; |
| 1239 | }; |
| 1240 | phy_calibration_p1: calib@954 { |
| 1241 | reg = <0x954 0x10>; |
| 1242 | }; |
| 1243 | phy_calibration_p2: calib@968 { |
| 1244 | reg = <0x968 0x10>; |
| 1245 | }; |
| 1246 | phy_calibration_p3: calib@97c { |
| 1247 | reg = <0x97c 0x10>; |
| 1248 | }; |
| 1249 | cpufreq_calibration: calib@278 { |
| 1250 | reg = <0x278 0x1>; |
| 1251 | }; |
| 1252 | }; |
| 1253 | }; |
| 1254 | |
| 1255 | #include "mt7988-clkitg.dtsi" |