commit 5cfc67a982055989d7dfad62480860fd5eb36966
author developer <developer@mediatek.com> Thu Dec 29 19:06:51 2022 +0800
committer developer <developer@mediatek.com> Tue Jan 03 17:56:46 2023 +0800
tree 3245f86b4914004a0c5bb340467e251ecc0277ab
parent 03c08d49d8154da4a544e5ed67fcf0209b0c2d41

[][Kernel][mt7988][eth][Add Ethernet clock config]

[Description]
Add Ethernet clock configurations which is suggested by
clock owner - Xiufeng.

If without this patch, some Ethernet/WED functions won't
work after removing mt7988-clkitg.dtsi.

[Release-log]
N/A


Change-Id: I835888ed0d6408d2dd7eb2c704ecc0d3c6f076a8
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/6988778

target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988.dtsi

diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988.dtsi b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988.dtsi
index cec46ce..3dd999f 100644
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988.dtsi
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988.dtsi
@@ -765,15 +765,42 @@
 			 <&sgmiisys0 CK_SGM0_RX_EN>,
 			 <&sgmiisys1 CK_SGM1_TX_EN>,
 			 <&sgmiisys1 CK_SGM1_RX_EN>,
+			 <&ethwarp CK_ETHWARP_WOCPU2_EN>,
+			 <&ethwarp CK_ETHWARP_WOCPU1_EN>,
+			 <&ethwarp CK_ETHWARP_WOCPU0_EN>,
 			 <&topckgen CK_TOP_USXGMII_SBUS_0_SEL>,
 			 <&topckgen CK_TOP_USXGMII_SBUS_1_SEL>,
 			 <&topckgen CK_TOP_SGM_0_SEL>,
-			 <&topckgen CK_TOP_SGM_1_SEL>;
+			 <&topckgen CK_TOP_SGM_1_SEL>,
+			 <&topckgen CK_TOP_XFI_PHY_0_XTAL_SEL>,
+			 <&topckgen CK_TOP_XFI_PHY_1_XTAL_SEL>,
+			 <&topckgen CK_TOP_ETH_GMII_SEL>,
+			 <&topckgen CK_TOP_ETH_REFCK_50M_SEL>,
+			 <&topckgen CK_TOP_ETH_SYS_200M_SEL>,
+			 <&topckgen CK_TOP_ETH_SYS_SEL>,
+			 <&topckgen CK_TOP_ETH_XGMII_SEL>,
+			 <&topckgen CK_TOP_ETH_MII_SEL>,
+			 <&topckgen CK_TOP_NETSYS_SEL>,
+			 <&topckgen CK_TOP_NETSYS_500M_SEL>,
+			 <&topckgen CK_TOP_NETSYS_PAO_2X_SEL>,
+			 <&topckgen CK_TOP_NETSYS_SYNC_250M_SEL>,
+			 <&topckgen CK_TOP_NETSYS_PPEFB_250M_SEL>,
+			 <&topckgen CK_TOP_NETSYS_WARP_SEL>;
 		clock-names = "xgp1", "xgp2", "xgp3", "fe", "gp2", "gp1",
 			      "gp3", "esw", "crypto", "sgmii_tx250m",
 			      "sgmii_rx250m", "sgmii2_tx250m", "sgmii2_rx250m",
-			      "usxgmii0_sel", "usxgmii1_sel",
-			      "sgm0_sel", "sgm1_sel";
+			      "ethwarp_wocpu2", "ethwarp_wocpu1",
+			      "ethwarp_wocpu0", "top_usxgmii0_sel",
+			      "top_usxgmii1_sel", "top_sgm0_sel",
+			      "top_sgm1_sel", "top_xfi_phy0_xtal_sel",
+			      "top_xfi_phy1_xtal_sel", "top_eth_gmii_sel",
+			      "top_eth_refck_50m_sel", "top_eth_sys_200m_sel",
+			      "top_eth_sys_sel", "top_eth_xgmii_sel",
+			      "top_eth_mii_sel", "top_netsys_sel",
+			      "top_netsys_500m_sel", "top_netsys_pao_2x_sel",
+			      "top_netsys_sync_250m_sel",
+			      "top_netsys_ppefb_250m_sel",
+			      "top_netsys_warp_sel";
 		assigned-clocks = <&topckgen CK_TOP_NETSYS_2X_SEL>,
 				  <&topckgen CK_TOP_NETSYS_GSW_SEL>,
 				  <&topckgen CK_TOP_USXGMII_SBUS_0_SEL>,