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git01.mediatek.com / openwrt / feeds / mtk-openwrt-feeds / 1bbcf512c0f7682a1f4133522457f1829b8bb891 / . / target / linux / mediatek / files-5.4 / arch / arm64 / boot / dts / mediatek / mt7988.dtsi
blob: 28e702ef9b25e1de1da729843288a3543581a0f2 [file] [log] [blame]
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2021 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 */
6
7#include <dt-bindings/interrupt-controller/irq.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/phy/phy.h>
10#include <dt-bindings/reset/ti-syscon.h>
11#include <dt-bindings/clock/mt7988-clk.h>
12#include <dt-bindings/pinctrl/mt65xx.h>
13#include <dt-bindings/thermal/thermal.h>
14#include <dt-bindings/regulator/richtek,rt5190a-regulator.h>
15#include <dt-bindings/power/mt7988-power.h>
16
17/ {
18 compatible = "mediatek,mt7988-rfb";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
22 cpus {
23 #address-cells = <1>;
24 #size-cells = <0>;
25 cpu@0 {
26 device_type = "cpu";
27 compatible = "arm,cortex-a73";
28 enable-method = "psci";
29 reg = <0x0>;
30 clocks = <&mcusys CK_MCU_ARM_DIV_SEL>,
31 <&topckgen CK_TOP_CB_NET1_D4>,
32 <&apmixedsys CK_APMIXED_ARM_B>,
33 <&mcusys CK_MCU_BUS_DIV_SEL>,
34 <&apmixedsys CK_APMIXED_CCIPLL2_B>;
35 clock-names = "cpu", "intermediate", "armpll", "cci",
36 "ccipll";
37 operating-points-v2 = <&cluster0_opp>;
38 nvmem-cells = <&cpufreq_calibration>;
39 nvmem-cell-names = "calibration-data";
40 };
41
42 cpu@1 {
43 device_type = "cpu";
44 compatible = "arm,cortex-a73";
45 enable-method = "psci";
46 reg = <0x1>;
47 clocks = <&mcusys CK_MCU_ARM_DIV_SEL>,
48 <&topckgen CK_TOP_CB_NET1_D4>,
49 <&apmixedsys CK_APMIXED_ARM_B>,
50 <&mcusys CK_MCU_BUS_DIV_SEL>,
51 <&apmixedsys CK_APMIXED_CCIPLL2_B>;
52 clock-names = "cpu", "intermediate", "armpll", "cci",
53 "ccipll";
54 operating-points-v2 = <&cluster0_opp>;
55 nvmem-cells = <&cpufreq_calibration>;
56 nvmem-cell-names = "calibration-data";
57 };
58
59 cpu@2 {
60 device_type = "cpu";
61 compatible = "arm,cortex-a73";
62 enable-method = "psci";
63 reg = <0x2>;
64 clocks = <&mcusys CK_MCU_ARM_DIV_SEL>,
65 <&topckgen CK_TOP_CB_NET1_D4>,
66 <&apmixedsys CK_APMIXED_ARM_B>,
67 <&mcusys CK_MCU_BUS_DIV_SEL>,
68 <&apmixedsys CK_APMIXED_CCIPLL2_B>;
69 clock-names = "cpu", "intermediate", "armpll", "cci",
70 "ccipll";
71 operating-points-v2 = <&cluster0_opp>;
72 nvmem-cells = <&cpufreq_calibration>;
73 nvmem-cell-names = "calibration-data";
74 };
75
76 cpu@3 {
77 device_type = "cpu";
78 compatible = "arm,cortex-a73";
79 enable-method = "psci";
80 reg = <0x3>;
81 clocks = <&mcusys CK_MCU_ARM_DIV_SEL>,
82 <&topckgen CK_TOP_CB_NET1_D4>,
83 <&apmixedsys CK_APMIXED_ARM_B>,
84 <&mcusys CK_MCU_BUS_DIV_SEL>,
85 <&apmixedsys CK_APMIXED_CCIPLL2_B>;
86 clock-names = "cpu", "intermediate", "armpll", "cci",
87 "ccipll";
88 operating-points-v2 = <&cluster0_opp>;
89 nvmem-cells = <&cpufreq_calibration>;
90 nvmem-cell-names = "calibration-data";
91 };
92
93 cluster0_opp: opp_table0 {
94 compatible = "operating-points-v2";
95 opp-shared;
96 opp00 {
97 opp-hz = /bits/ 64 <800000000>;
98 opp-microvolt = <850000>;
99 };
100 opp01 {
101 opp-hz = /bits/ 64 <1100000000>;
102 opp-microvolt = <850000>;
103 };
104 opp02 {
105 opp-hz = /bits/ 64 <1500000000>;
106 opp-microvolt = <850000>;
107 };
108 opp03 {
109 opp-hz = /bits/ 64 <1800000000>;
110 opp-microvolt = <900000>;
111 };
112 };
113 };
114
115 thermal-zones {
116 cpu_thermal: cpu-thermal {
117 polling-delay-passive = <1000>;
118 polling-delay = <1000>;
119 thermal-sensors = <&lvts 0>;
120 trips {
121 cpu_trip_crit: crit {
122 temperature = <125000>;
123 hysteresis = <2000>;
124 type = "critical";
125 };
126
127 cpu_trip_hot: hot {
128 temperature = <120000>;
129 hysteresis = <2000>;
130 type = "hot";
131 };
132
133 cpu_trip_active_high: active-high {
134 temperature = <115000>;
135 hysteresis = <2000>;
136 type = "active";
137 };
138
139 cpu_trip_active_low: active-low {
140 temperature = <85000>;
141 hysteresis = <2000>;
142 type = "active";
143 };
144
145 cpu_trip_passive: passive {
146 temperature = <40000>;
147 hysteresis = <2000>;
148 type = "passive";
149 };
150 };
151
152 cooling-maps {
153 cpu-active-high {
154 /* active: set fan to cooling level 2 */
155 cooling-device = <&fan 2 2>;
156 trip = <&cpu_trip_active_high>;
157 };
158
159 cpu-active-low {
160 /* active: set fan to cooling level 1 */
161 cooling-device = <&fan 1 1>;
162 trip = <&cpu_trip_active_low>;
163 };
164
165 cpu-passive {
166 /* passive: set fan to cooling level 0 */
167 cooling-device = <&fan 0 0>;
168 trip = <&cpu_trip_passive>;
169 };
170 };
171
172 };
173 };
174
175 mmc0: mmc@11230000 {
176 compatible = "mediatek,mt7986-mmc";
177 reg = <0 0x11230000 0 0x1000>,
178 <0 0x11D60000 0 0x1000>;
179 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
180 clocks = <&infracfg_ao CK_INFRA_MSDC400>,
181 <&infracfg_ao CK_INFRA_MSDC2_HCK>,
182 <&infracfg_ao CK_INFRA_133M_MSDC_0_HCK>,
183 <&infracfg_ao CK_INFRA_66M_MSDC_0_HCK>;
184 clock-names = "source", "hclk", "ahb_cg", "axi_cg";
185 status = "disabled";
186 };
187
188 wed: wed@15010000 {
189 compatible = "mediatek,wed";
190 wed_num = <3>;
191 /* add this property for wed get the pci slot number. */
192 pci_slot_map = <0>, <1>, <2>;
193 reg = <0 0x15010000 0 0x2000>,
194 <0 0x15012000 0 0x2000>,
195 <0 0x15014000 0 0x2000>;
196 interrupt-parent = <&gic>;
197 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
200 };
201
202 wed2: wed2@15012000 {
203 compatible = "mediatek,wed2";
204 wed_num = <3>;
205 /* add this property for wed get the pci slot number. */
206 reg = <0 0x15010000 0 0x2000>,
207 <0 0x15012000 0 0x2000>,
208 <0 0x15014000 0 0x2000>;
209 interrupt-parent = <&gic>;
210 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
211 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
212 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
213 };
214
215 wed3: wed3@15014000 {
216 compatible = "mediatek,wed3";
217 wed_num = <3>;
218 /* add this property for wed get the pci slot number. */
219 reg = <0 0x15010000 0 0x2000>,
220 <0 0x15012000 0 0x2000>,
221 <0 0x15014000 0 0x2000>;
222 interrupt-parent = <&gic>;
223 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
224 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
225 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
226 };
227
228 wdma: wdma@15104800 {
229 compatible = "mediatek,wed-wdma";
230 reg = <0 0x15104800 0 0x400>,
231 <0 0x15104c00 0 0x400>,
232 <0 0x15105000 0 0x400>;
233 };
234
235 ap2woccif: ap2woccif@151A5000 {
236 compatible = "mediatek,ap2woccif";
237 reg = <0 0x151A5000 0 0x1000>,
238 <0 0x152A5000 0 0x1000>,
239 <0 0x153A5000 0 0x1000>;
240 interrupt-parent = <&gic>;
241 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
242 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
243 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
244 };
245
246 wocpu0_ilm: wocpu0_ilm@151E0000 {
247 compatible = "mediatek,wocpu0_ilm";
248 reg = <0 0x151E0000 0 0x8000>;
249 };
250
251 wocpu1_ilm: wocpu1_ilm@152E0000 {
252 compatible = "mediatek,wocpu1_ilm";
253 reg = <0 0x152E0000 0 0x8000>;
254 };
255
256 wocpu2_ilm: wocpu2_ilm@153E0000 {
257 compatible = "mediatek,wocpu2_ilm";
258 reg = <0 0x153E0000 0 0x8000>;
259 };
260
261 wocpu_dlm: wocpu_dlm@151E8000 {
262 compatible = "mediatek,wocpu_dlm";
263 reg = <0 0x151E8000 0 0x2000>,
264 <0 0x152E8000 0 0x2000>,
265 <0 0x153E8000 0 0x2000>;
266
267 resets = <&ethsysrst 0>;
268 reset-names = "wocpu_rst";
269 };
270
271 cpu_boot: wocpu_boot@15194000 {
272 compatible = "mediatek,wocpu_boot";
273 reg = <0 0x15194000 0 0x1000>,
274 <0 0x15294000 0 0x1000>,
275 <0 0x15394000 0 0x1000>;
276 };
277
278 reserved-memory {
279 #address-cells = <2>;
280 #size-cells = <2>;
281 ranges;
282
283 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
284 secmon_reserved: secmon@43000000 {
285 reg = <0 0x43000000 0 0x30000>;
286 no-map;
287 };
288
289 wmcpu_emi: wmcpu-reserved@47CC0000 {
290 compatible = "mediatek,wmcpu-reserved";
291 no-map;
292 reg = <0 0x47CC0000 0 0x00100000>;
293 };
294
295 wocpu0_emi: wocpu0_emi@4F600000 {
296 compatible = "mediatek,wocpu0_emi";
297 no-map;
298 reg = <0 0x4F600000 0 0x40000>;
299 shared = <0>;
300 };
301
302 wocpu1_emi: wocpu1_emi@4F640000 {
303 compatible = "mediatek,wocpu1_emi";
304 no-map;
305 reg = <0 0x4F640000 0 0x40000>;
306 shared = <0>;
307 };
308
309 wocpu2_emi: wocpu2_emi@4F680000 {
310 compatible = "mediatek,wocpu2_emi";
311 no-map;
312 reg = <0 0x4F680000 0 0x40000>;
313 shared = <0>;
314 };
315
316 wocpu_data: wocpu_data@4F700000 {
317 compatible = "mediatek,wocpu_data";
318 no-map;
319 reg = <0 0x4F700000 0 0x800000>;
320 shared = <1>;
321 };
322 };
323
324 psci {
325 compatible = "arm,psci-0.2";
326 method = "smc";
327 };
328
329 system_clk: dummy_system_clk {
330 compatible = "fixed-clock";
331 clock-frequency = <40000000>;
332 #clock-cells = <0>;
333 };
334
335 uart_clk: dummy_uart_clk {
336 compatible = "fixed-clock";
337 clock-frequency = <40000000>;
338 #clock-cells = <0>;
339 };
340
341 timer {
342 compatible = "arm,armv8-timer";
343 interrupt-parent = <&gic>;
344 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
345 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
346 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
347 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
348
349 };
350
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]351 watchdog: watchdog@1001c000 {
352 compatible = "mediatek,mt7622-wdt",
353 "mediatek,mt6589-wdt",
354 "syscon";
355 reg = <0 0x1001c000 0 0x1000>;
356 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
357 #reset-cells = <1>;
358 };
359
360 phyfw: phy-firmware@f000000 {
361 compatible = "mediatek,2p5gphy-fw";
362 reg = <0 0x0f000000 0 0x8000>,
363 <0 0x0f100000 0 0x20000>,
364 <0 0x0f0f0000 0 0x200>;
365 };
366
developer23021292022-10-21 19:10:10 +0800[diff] [blame]367 boottrap: boottrap@1001f6f0 {
368 compatible = "mediatek,boottrap";
369 reg = <0 0x1001f6f0 0 0x20>;
370 };
371
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]372 gic: interrupt-controller@c000000 {
373 compatible = "arm,gic-v3";
374 #interrupt-cells = <3>;
375 interrupt-parent = <&gic>;
376 interrupt-controller;
377 reg = <0 0x0c000000 0 0x40000>, /* GICD */
378 <0 0x0c080000 0 0x200000>; /* GICR */
379
380 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
381 };
382
383 trng: trng@1020f000 {
384 compatible = "mediatek,mt7988-rng";
385 };
386
387 uart0: serial@11000000 {
388 compatible = "mediatek,mt7986-uart",
389 "mediatek,mt6577-uart";
390 reg = <0 0x11000000 0 0x100>;
391 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
392 clocks = <&uart_clk>;
393 status = "disabled";
394 };
395
396 uart1: serial@11000100 {
397 compatible = "mediatek,mt7986-uart",
398 "mediatek,mt6577-uart";
399 reg = <0 0x11000100 0 0x100>;
400 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
401 clocks = <&uart_clk>;
402 status = "disabled";
403 };
404
405 uart2: serial@11000200 {
406 compatible = "mediatek,mt7986-uart",
407 "mediatek,mt6577-uart";
408 reg = <0 0x11000200 0 0x100>;
409 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
410 clocks = <&uart_clk>;
411 status = "disabled";
412 };
413
414 i2c0: i2c@11003000 {
415 compatible = "mediatek,mt7988-i2c",
416 "mediatek,mt7981-i2c";
417 reg = <0 0x11003000 0 0x1000>,
418 <0 0x10217080 0 0x80>;
419 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
420 clock-div = <1>;
421 clocks = <&system_clk>,
422 <&system_clk>;
423 clock-names = "main", "dma";
424 #address-cells = <1>;
425 #size-cells = <0>;
426 status = "disabled";
427 };
428
429 i2c1: i2c@11004000 {
430 compatible = "mediatek,mt7988-i2c",
431 "mediatek,mt7981-i2c";
432 reg = <0 0x11004000 0 0x1000>,
433 <0 0x10217100 0 0x80>;
434 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
435 clock-div = <1>;
436 clocks = <&system_clk>,
437 <&system_clk>;
438 clock-names = "main", "dma";
439 #address-cells = <1>;
440 #size-cells = <0>;
441 status = "disabled";
442 };
443
444 i2c2: i2c@11005000 {
445 compatible = "mediatek,mt7988-i2c",
446 "mediatek,mt7981-i2c";
447 reg = <0 0x11005000 0 0x1000>,
448 <0 0x10217180 0 0x80>;
449 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
450 clock-div = <1>;
451 clocks = <&system_clk>,
452 <&system_clk>;
453 clock-names = "main", "dma";
454 #address-cells = <1>;
455 #size-cells = <0>;
456 status = "disabled";
457 };
458
459 pwm: pwm@10048000 {
460 compatible = "mediatek,mt7988-pwm";
461 reg = <0 0x10048000 0 0x1000>;
462 #pwm-cells = <2>;
developer1ad6fe42022-11-02 11:33:26 +0800[diff] [blame]463 clocks = <&infracfg_ao CK_INFRA_66M_PWM_BCK>,
464 <&infracfg_ao CK_INFRA_66M_PWM_HCK>,
465 <&infracfg_ao CK_INFRA_66M_PWM_CK1>,
466 <&infracfg_ao CK_INFRA_66M_PWM_CK2>,
467 <&infracfg_ao CK_INFRA_66M_PWM_CK3>,
468 <&infracfg_ao CK_INFRA_66M_PWM_CK4>,
469 <&infracfg_ao CK_INFRA_66M_PWM_CK5>,
470 <&infracfg_ao CK_INFRA_66M_PWM_CK6>,
471 <&infracfg_ao CK_INFRA_66M_PWM_CK7>,
472 <&infracfg_ao CK_INFRA_66M_PWM_CK8>;
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]473 clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
474 "pwm4","pwm5","pwm6","pwm7","pwm8";
475 status = "disabled";
476 };
477
478 fan: pwm-fan {
479 compatible = "pwm-fan";
480 /* cooling level (0, 1, 2) : (0% duty, 50% duty, 100% duty) */
481 cooling-levels = <0 128 255>;
482 #cooling-cells = <2>;
483 #thermal-sensor-cells = <1>;
484 status = "disabled";
485 };
486
487 lvts: lvts@1100a000 {
488 compatible = "mediatek,mt7988-lvts";
489 #thermal-sensor-cells = <1>;
490 reg = <0 0x1100a000 0 0x1000>;
developer1bbcf512022-11-18 16:09:33 +0800[diff] [blame^]491 clocks = <&infracfg_ao CK_INFRA_26M_THERM_SYSTEM>;
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]492 clock-names = "lvts_clk";
493 nvmem-cells = <&lvts_calibration>;
494 nvmem-cell-names = "e_data1";
495 };
496
497 crypto: crypto@15600000 {
498 compatible = "inside-secure,safexcel-eip197b";
499 reg = <0 0x15600000 0 0x180000>;
500 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
501 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
502 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
503 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
504 interrupt-names = "ring0", "ring1", "ring2", "ring3";
505 status = "okay";
506 };
507
developer3594afb2022-10-25 13:22:53 +0800[diff] [blame]508 afe: audio-controller@11210000 {
509 compatible = "mediatek,mt79xx-audio";
510 reg = <0 0x11210000 0 0x9000>;
511 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
512 clocks = <&infracfg_ao CK_INFRA_66M_AUD_SLV_BCK>,
513 <&infracfg_ao CK_INFRA_AUD_26M>,
514 <&infracfg_ao CK_INFRA_AUD_L>,
515 <&infracfg_ao CK_INFRA_AUD_AUD>,
516 <&infracfg_ao CK_INFRA_AUD_EG2>,
517 <&topckgen CK_TOP_AUD_SEL>,
518 <&topckgen CK_TOP_AUD_I2S_M>;
519 clock-names = "aud_bus_ck",
520 "aud_26m_ck",
521 "aud_l_ck",
522 "aud_aud_ck",
523 "aud_eg2_ck",
524 "aud_sel",
525 "aud_i2s_m";
526 assigned-clocks = <&topckgen CK_TOP_AUD_SEL>,
527 <&topckgen CK_TOP_A1SYS_SEL>,
528 <&topckgen CK_TOP_AUD_L_SEL>,
529 <&topckgen CK_TOP_A_TUNER_SEL>;
530 assigned-clock-parents = <&topckgen CK_TOP_CB_APLL2_196M>,
531 <&topckgen CK_TOP_CB_APLL2_D4>,
532 <&topckgen CK_TOP_CB_APLL2_196M>,
533 <&topckgen CK_TOP_CB_APLL2_D4>;
534 status = "disabled";
535 };
536
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]537 pcie0: pcie@11300000 {
538 compatible = "mediatek,mt7988-pcie",
539 "mediatek,mt7986-pcie";
540 device_type = "pci";
541 #address-cells = <3>;
542 #size-cells = <2>;
543 reg = <0 0x11300000 0 0x2000>;
544 reg-names = "pcie-mac";
545 linux,pci-domain = <0>;
546 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
547 bus-range = <0x00 0xff>;
548 ranges = <0x81000000 0x00 0x30000000 0x00
549 0x30000000 0x00 0x00200000>,
550 <0x82000000 0x00 0x30200000 0x00
551 0x30200000 0x00 0x07e00000>;
552 status = "disabled";
553
554 clocks = <&topckgen CK_TOP_PEXTP_P0_SEL>,
555 <&infracfg_ao CK_INFRA_PCIE_GFMUX_TL_P0>,
556 <&infracfg_ao CK_INFRA_PCIE_PIPE_P0>,
557 <&infracfg_ao CK_INFRA_133M_PCIE_CK_P0>,
558 <&infracfg_ao CK_INFRA_PCIE_PERI_26M_CK_P0>;
559
560 #interrupt-cells = <1>;
561 interrupt-map-mask = <0 0 0 0x7>;
562 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
563 <0 0 0 2 &pcie_intc0 1>,
564 <0 0 0 3 &pcie_intc0 2>,
565 <0 0 0 4 &pcie_intc0 3>;
566 pcie_intc0: interrupt-controller {
567 #address-cells = <0>;
568 #interrupt-cells = <1>;
569 interrupt-controller;
570 };
571 };
572
573 pcie1: pcie@11310000 {
574 compatible = "mediatek,mt7988-pcie",
575 "mediatek,mt7986-pcie";
576 device_type = "pci";
577 #address-cells = <3>;
578 #size-cells = <2>;
579 reg = <0 0x11310000 0 0x2000>;
580 reg-names = "pcie-mac";
581 linux,pci-domain = <1>;
582 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
583 bus-range = <0x00 0xff>;
584 ranges = <0x81000000 0x00 0x38000000 0x00
585 0x38000000 0x00 0x00200000>,
586 <0x82000000 0x00 0x38200000 0x00
587 0x38200000 0x00 0x07e00000>;
588 status = "disabled";
589
590 clocks = <&topckgen CK_TOP_PEXTP_P1_SEL>,
591 <&infracfg_ao CK_INFRA_PCIE_GFMUX_TL_P1>,
592 <&infracfg_ao CK_INFRA_PCIE_PIPE_P1>,
593 <&infracfg_ao CK_INFRA_133M_PCIE_CK_P1>,
594 <&infracfg_ao CK_INFRA_PCIE_PERI_26M_CK_P1>;
595
596 #interrupt-cells = <1>;
597 interrupt-map-mask = <0 0 0 0x7>;
598 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
599 <0 0 0 2 &pcie_intc1 1>,
600 <0 0 0 3 &pcie_intc1 2>,
601 <0 0 0 4 &pcie_intc1 3>;
602 pcie_intc1: interrupt-controller {
603 #address-cells = <0>;
604 #interrupt-cells = <1>;
605 interrupt-controller;
606 };
607 };
608
609 pcie2: pcie@11280000 {
610 compatible = "mediatek,mt7988-pcie",
611 "mediatek,mt7986-pcie";
612 device_type = "pci";
613 #address-cells = <3>;
614 #size-cells = <2>;
615 reg = <0 0x11280000 0 0x2000>;
616 reg-names = "pcie-mac";
617 linux,pci-domain = <3>;
618 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
619 bus-range = <0x00 0xff>;
620 ranges = <0x81000000 0x00 0x20000000 0x00
621 0x20000000 0x00 0x00200000>,
622 <0x82000000 0x00 0x20200000 0x00
623 0x20200000 0x00 0x07e00000>;
624 status = "disabled";
625
626 clocks = <&topckgen CK_TOP_PEXTP_P2_SEL>,
627 <&infracfg_ao CK_INFRA_PCIE_GFMUX_TL_P2>,
628 <&infracfg_ao CK_INFRA_PCIE_PIPE_P2>,
629 <&infracfg_ao CK_INFRA_133M_PCIE_CK_P2>,
630 <&infracfg_ao CK_INFRA_PCIE_PERI_26M_CK_P2>,
631 <&infracfg_ao CK_INFRA_PCIE_PERI_26M_CK_P3>;
632
633 phys = <&xphyu3port0 PHY_TYPE_PCIE>;
634 phy-names = "pcie-phy";
635
636 #interrupt-cells = <1>;
637 interrupt-map-mask = <0 0 0 0x7>;
638 interrupt-map = <0 0 0 1 &pcie_intc2 0>,
639 <0 0 0 2 &pcie_intc2 1>,
640 <0 0 0 3 &pcie_intc2 2>,
641 <0 0 0 4 &pcie_intc2 3>;
642 pcie_intc2: interrupt-controller {
643 #address-cells = <0>;
644 #interrupt-cells = <1>;
645 interrupt-controller;
646 };
647 };
648
649 pcie3: pcie@11290000 {
650 compatible = "mediatek,mt7988-pcie",
651 "mediatek,mt7986-pcie";
652 device_type = "pci";
653 #address-cells = <3>;
654 #size-cells = <2>;
655 reg = <0 0x11290000 0 0x2000>;
656 reg-names = "pcie-mac";
657 linux,pci-domain = <2>;
658 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
659 bus-range = <0x00 0xff>;
660 ranges = <0x81000000 0x00 0x28000000 0x00
661 0x28000000 0x00 0x00200000>,
662 <0x82000000 0x00 0x28200000 0x00
663 0x28200000 0x00 0x07e00000>;
664 status = "disabled";
665
666 clocks = <&topckgen CK_TOP_PEXTP_P3_SEL>,
667 <&infracfg_ao CK_INFRA_PCIE_GFMUX_TL_P3>,
668 <&infracfg_ao CK_INFRA_PCIE_PIPE_P3>,
669 <&infracfg_ao CK_INFRA_133M_PCIE_CK_P3>,
670 <&infracfg_ao CK_INFRA_PCIE_PERI_26M_CK_P3>;
671
672 #interrupt-cells = <1>;
673 interrupt-map-mask = <0 0 0 0x7>;
674 interrupt-map = <0 0 0 1 &pcie_intc3 0>,
675 <0 0 0 2 &pcie_intc3 1>,
676 <0 0 0 3 &pcie_intc3 2>,
677 <0 0 0 4 &pcie_intc3 3>;
678 pcie_intc3: interrupt-controller {
679 #address-cells = <0>;
680 #interrupt-cells = <1>;
681 interrupt-controller;
682 };
683 };
684
685 pio: pinctrl@1001f000 {
686 compatible = "mediatek,mt7988-pinctrl";
687 reg = <0 0x1001f000 0 0x1000>,
688 <0 0x11c10000 0 0x1000>,
689 <0 0x11d00000 0 0x1000>,
690 <0 0x11d20000 0 0x1000>,
691 <0 0x11e00000 0 0x1000>,
692 <0 0x11f00000 0 0x1000>,
693 <0 0x1000b000 0 0x1000>;
694 reg-names = "gpio_base", "iocfg_tr_base", "iocfg_br_base",
695 "iocfg_rb_base", "iocfg_lb_base", "iocfg_tl_base",
696 "eint";
697 gpio-controller;
698 #gpio-cells = <2>;
699 gpio-ranges = <&pio 0 0 83>;
700 interrupt-controller;
developera9e41142022-11-01 09:46:14 +0800[diff] [blame]701 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]702 interrupt-parent = <&gic>;
703 #interrupt-cells = <2>;
704 };
705
706 ethsys: syscon@15000000 {
707 #address-cells = <1>;
708 #size-cells = <1>;
709 compatible = "mediatek,mt7988-ethsys",
710 "syscon";
711 reg = <0 0x15000000 0 0x1000>;
712 #clock-cells = <1>;
713 #reset-cells = <1>;
714
715 ethsysrst: reset-controller {
716 compatible = "ti,syscon-reset";
717 #reset-cells = <1>;
718 ti,reset-bits =
719 <0x34 4 0x34 4 0x34 4
720 (ASSERT_SET | DEASSERT_CLEAR | STATUS_SET)>;
721 };
722 };
723
724 ethwarp: syscon@15031000 {
725 compatible = "mediatek,mt7988-ethwarp", "syscon";
726 reg = <0 0x15031000 0 0x1000>;
727 #clock-cells = <1>;
728 };
729
730 switch0: switch0@15020000 {
731 #address-cells = <1>;
732 #size-cells = <1>;
733 compatible = "mediatek,mt7988-switch", "syscon";
734 reg = <0 0x15020000 0 0x8000>;
735 };
736
737 eth: ethernet@15100000 {
738 compatible = "mediatek,mt7988-eth";
739 reg = <0 0x15100000 0 0x80000>,
740 <0 0x15400000 0 0x380000>;
741 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
742 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
743 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
744 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
developer1bbcf512022-11-18 16:09:33 +0800[diff] [blame^]745 clocks = <&ethsys CK_ETHDMA_XGP1_EN>,
746 <&ethsys CK_ETHDMA_XGP2_EN>,
747 <&ethsys CK_ETHDMA_XGP3_EN>,
748 <&ethsys CK_ETHDMA_FE_EN>,
749 <&ethsys CK_ETHDMA_GP2_EN>,
750 <&ethsys CK_ETHDMA_GP1_EN>,
751 <&ethsys CK_ETHDMA_GP3_EN>,
752 <&ethsys CK_ETHDMA_ESW_EN>,
753 <&ethsys CK_ETHDMA_CRYPT0_EN>,
754 <&sgmiisys0 CK_SGM0_TX_EN>,
755 <&sgmiisys0 CK_SGM0_RX_EN>,
756 <&sgmiisys1 CK_SGM1_TX_EN>,
757 <&sgmiisys1 CK_SGM1_RX_EN>,
758 <&topckgen CK_TOP_USXGMII_SBUS_0_SEL>,
759 <&topckgen CK_TOP_USXGMII_SBUS_1_SEL>,
760 <&topckgen CK_TOP_SGM_0_SEL>,
761 <&topckgen CK_TOP_SGM_1_SEL>;
762 clock-names = "xgp1", "xgp2", "xgp3", "fe", "gp2", "gp1",
763 "gp3", "esw", "crypto", "sgmii_tx250m",
764 "sgmii_rx250m", "sgmii2_tx250m", "sgmii2_rx250m",
765 "usxgmii0_sel", "usxgmii1_sel",
766 "sgm0_sel", "sgm1_sel";
767 assigned-clocks = <&topckgen CK_TOP_NETSYS_2X_SEL>,
768 <&topckgen CK_TOP_NETSYS_GSW_SEL>,
769 <&topckgen CK_TOP_USXGMII_SBUS_0_SEL>,
770 <&topckgen CK_TOP_USXGMII_SBUS_1_SEL>,
771 <&topckgen CK_TOP_SGM_0_SEL>,
772 <&topckgen CK_TOP_SGM_1_SEL>;
773 assigned-clock-parents = <&topckgen CK_TOP_CB_NET2_800M>,
774 <&topckgen CK_TOP_CB_NET1_D4>,
775 <&topckgen CK_TOP_NET1_D8_D4>,
776 <&topckgen CK_TOP_NET1_D8_D4>,
777 <&topckgen CK_TOP_CB_SGM_325M>,
778 <&topckgen CK_TOP_CB_SGM_325M>;
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]779 mediatek,ethsys = <&ethsys>;
780 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
781 mediatek,usxgmiisys = <&usxgmiisys0>, <&usxgmiisys1>;
782 mediatek,xfi_pextp = <&xfi_pextp0>, <&xfi_pextp1>;
783 mediatek,xfi_pll = <&xfi_pll>;
784 mediatek,infracfg = <&topmisc>;
785 mediatek,toprgu = <&watchdog>;
786 #reset-cells = <1>;
787 #address-cells = <1>;
788 #size-cells = <0>;
789 status = "disabled";
790 };
791
792 hnat: hnat@15000000 {
793 compatible = "mediatek,mtk-hnat_v5";
794 reg = <0 0x15100000 0 0x80000>;
795 resets = <&ethsys 0>;
796 reset-names = "mtketh";
797 status = "disabled";
798 };
799
800 sgmiisys0: syscon@10060000 {
801 compatible = "mediatek,mt7988-sgmiisys",
802 "mediatek,mt7988-sgmiisys_0",
803 "syscon";
804 reg = <0 0x10060000 0 0x1000>;
805 #clock-cells = <1>;
806 };
807
808 sgmiisys1: syscon@10070000 {
809 compatible = "mediatek,mt7988-sgmiisys",
810 "mediatek,mt7988-sgmiisys_1",
811 "syscon";
812 reg = <0 0x10070000 0 0x1000>;
813 #clock-cells = <1>;
814 };
815
816 usxgmiisys0: usxgmiisys@10080000 {
817 compatible = "mediatek,mt7988-usxgmiisys",
818 "mediatek,mt7988-usxgmiisys_0",
819 "syscon";
820 reg = <0 0x10080000 0 0x1000>;
821 #clock-cells = <1>;
822 };
823
824 usxgmiisys1: usxgmiisys@10081000 {
825 compatible = "mediatek,mt7988-usxgmiisys",
826 "mediatek,mt7988-usxgmiisys_1",
827 "syscon";
828 reg = <0 0x10081000 0 0x1000>;
829 #clock-cells = <1>;
830 };
831
832 xfi_pextp0: xfi_pextp@11f20000 {
833 compatible = "mediatek,mt7988-xfi_pextp",
834 "mediatek,mt7988-xfi_pextp_0",
835 "syscon";
836 reg = <0 0x11f20000 0 0x10000>;
837 #clock-cells = <1>;
838 };
839
840 xfi_pextp1: xfi_pextp@11f30000 {
841 compatible = "mediatek,mt7988-xfi_pextp",
842 "mediatek,mt7988-xfi_pextp_1",
843 "syscon";
844 reg = <0 0x11f30000 0 0x10000>;
845 #clock-cells = <1>;
846 };
847
848 xfi_pll: xfi_pll@11f40000 {
849 compatible = "mediatek,mt7988-xfi_pll", "syscon";
850 reg = <0 0x11f40000 0 0x1000>;
851 #clock-cells = <1>;
852 };
853
854 topmisc: topmisc@11d10000 {
855 compatible = "mediatek,mt7988-topmisc", "syscon",
856 "mediatek,mt7988-power-controller";
857 reg = <0 0x11d10000 0 0x10000>;
858 #clock-cells = <1>;
859 #power-domain-cells = <1>;
860 #address-cells = <1>;
861 #size-cells = <0>;
862 /* power domain of the SoC */
863 tops0@MT7988_POWER_DOMAIN_TOPS0 {
864 reg = <MT7988_POWER_DOMAIN_TOPS0>;
865 #power-domain-cells = <0>;
866 };
867 tops1@MT7988_POWER_DOMAIN_TOPS1 {
868 reg = <MT7988_POWER_DOMAIN_TOPS1>;
869 #power-domain-cells = <0>;
870 };
871 eth2p5@MT7988_POWER_DOMAIN_ETH2P5 {
872 reg = <MT7988_POWER_DOMAIN_ETH2P5>;
873 #power-domain-cells = <0>;
874 };
875 };
876
877 snand: snfi@11001000 {
878 compatible = "mediatek,mt7986-snand";
879 reg = <0 0x11001000 0 0x1000>, <0 0x11002000 0 0x1000>;
880 reg-names = "nfi", "ecc";
881 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
882 clocks = <&system_clk>,
883 <&system_clk>,
884 <&system_clk>,
885 <&system_clk>;
886 clock-names = "nfi_clk", "pad_clk", "ecc_clk", "nfi_hclk";
887 #address-cells = <1>;
888 #size-cells = <0>;
889 status = "disabled";
890 };
891
892 wbsys: wbsys@18000000 {
893 compatible = "mediatek,wbsys";
894 reg = <0 0x18000000 0 0x1000000>;
895 linux,pci-domain = <4>;
896 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
897 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
898 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
899 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
900 chip_id = <0x7981>;
901 };
902
903 wed_pcie: wed_pcie@10003000 {
904 compatible = "mediatek,wed_pcie";
905 reg = <0 0x10003000 0 0x10>;
906 };
907
developer4c9c1c12022-11-02 11:30:47 +0800[diff] [blame]908 infra_bus_prot: infra_bus_prot@1000310c {
909 compatible = "mediatek,infracfg_ao_bus_hang_prot";
910 reg = <0 0x1000310c 0 0x14>;
911 };
912
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]913 spi0: spi@11007000 {
914 compatible = "mediatek,ipm-spi-quad";
915 reg = <0 0x11007000 0 0x100>;
916 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
917 clocks = <&topckgen CK_TOP_CB_M_D2>,
918 <&topckgen CK_TOP_SPI_SEL>,
919 <&infracfg_ao CK_INFRA_104M_SPI0>,
920 <&infracfg_ao CK_INFRA_66M_SPI0_HCK>;
921 clock-names = "parent-clk", "sel-clk", "spi-clk", "spi-hclk";
922 status = "disabled";
923 };
924
925 spi1: spi@11008000 {
926 compatible = "mediatek,ipm-spi-single";
927 reg = <0 0x11008000 0 0x100>;
928 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
929 clocks = <&topckgen CK_TOP_CB_M_D2>,
930 <&topckgen CK_TOP_SPI_SEL>,
931 <&infracfg_ao CK_INFRA_104M_SPI1>,
932 <&infracfg_ao CK_INFRA_66M_SPI1_HCK>;
933 clock-names = "parent-clk", "sel-clk", "spi-clk", "spi-hclk";
934 status = "disabled";
935 };
936
937 spi2: spi@11009000 {
938 compatible = "mediatek,ipm-spi-quad";
939 reg = <0 0x11009000 0 0x100>;
940 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
941 clocks = <&topckgen CK_TOP_CB_M_D2>,
942 <&topckgen CK_TOP_SPI_SEL>,
943 <&infracfg_ao CK_INFRA_104M_SPI2_BCK>,
944 <&infracfg_ao CK_INFRA_66M_SPI2_HCK>;
945 clock-names = "parent-clk", "sel-clk", "spi-clk", "spi-hclk";
946 status = "disabled";
947 };
948
949 consys: consys@10000000 {
950 compatible = "mediatek,mt7981-consys";
951 reg = <0 0x10000000 0 0x8600000>;
952 memory-region = <&wmcpu_emi>;
953 };
954
955 xhci0: xhci@11190000 {
956 compatible = "mediatek,mt7988-xhci",
957 "mediatek,mtk-xhci";
958 reg = <0 0x11190000 0 0x2e00>,
959 <0 0x11193e00 0 0x0100>;
960 reg-names = "mac", "ippc";
961 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
962 phys = <&xphyu2port0 PHY_TYPE_USB2>,
963 <&xphyu3port0 PHY_TYPE_USB3>;
964 clocks = <&system_clk>,
965 <&system_clk>,
966 <&system_clk>,
967 <&system_clk>,
968 <&system_clk>;
969 clock-names = "sys_ck",
970 "xhci_ck",
971 "ref_ck",
972 "mcu_ck",
973 "dma_ck";
974 #address-cells = <2>;
975 #size-cells = <2>;
developer8cdcb262022-10-27 14:36:15 +0800[diff] [blame]976 mediatek,p0_speed_fixup;
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]977 status = "okay";
978 };
979
980 usbxphy: usb-phy@11e10000 {
981 compatible = "mediatek,mt7988",
982 "mediatek,xsphy";
983 #address-cells = <2>;
984 #size-cells = <2>;
985 ranges;
986 status = "okay";
987
988 xphyu2port0: usb-phy@11e10000 {
989 reg = <0 0x11e10000 0 0x400>;
990 clocks = <&system_clk>;
991 clock-names = "ref";
992 #phy-cells = <1>;
993 status = "okay";
994 };
995
996 xphyu3port0: usb-phy@11e13000 {
997 reg = <0 0x11e13400 0 0x500>;
998 clocks = <&system_clk>;
999 clock-names = "ref";
1000 #phy-cells = <1>;
1001 mediatek,syscon-type = <&topmisc 0x218 0>;
1002 status = "okay";
1003 };
1004 };
1005
1006 xhci1: xhci@11200000 {
1007 compatible = "mediatek,mt7988-xhci",
1008 "mediatek,mtk-xhci";
1009 reg = <0 0x11200000 0 0x2e00>,
1010 <0 0x11203e00 0 0x0100>;
1011 reg-names = "mac", "ippc";
1012 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
1013 phys = <&tphyu2port0 PHY_TYPE_USB2>,
1014 <&tphyu3port0 PHY_TYPE_USB3>;
1015 clocks = <&system_clk>,
1016 <&system_clk>,
1017 <&system_clk>,
1018 <&system_clk>,
1019 <&system_clk>;
1020 clock-names = "sys_ck",
1021 "xhci_ck",
1022 "ref_ck",
1023 "mcu_ck",
1024 "dma_ck";
1025 #address-cells = <2>;
1026 #size-cells = <2>;
1027 status = "okay";
1028 };
1029
1030 usbtphy: usb-phy@11c50000 {
1031 compatible = "mediatek,mt7988",
1032 "mediatek,generic-tphy-v2";
1033 #address-cells = <2>;
1034 #size-cells = <2>;
1035 ranges;
1036 status = "okay";
1037
1038 tphyu2port0: usb-phy@11c50000 {
1039 reg = <0 0x11c50000 0 0x700>;
1040 clocks = <&system_clk>;
1041 clock-names = "ref";
1042 #phy-cells = <1>;
1043 status = "okay";
1044 };
1045
1046 tphyu3port0: usb-phy@11c50700 {
1047 reg = <0 0x11c50700 0 0x900>;
1048 clocks = <&system_clk>;
1049 clock-names = "ref";
1050 #phy-cells = <1>;
developer8cdcb262022-10-27 14:36:15 +0800[diff] [blame]1051 mediatek,usb3-pll-ssc-delta;
1052 mediatek,usb3-pll-ssc-delta1;
developer2cdaeb12022-10-04 20:25:05 +0800[diff] [blame]1053 status = "okay";
1054 };
1055 };
1056
1057 clk40m: oscillator@0 {
1058 compatible = "fixed-clock";
1059 #clock-cells = <0>;
1060 clock-frequency = <40000000>;
1061 clock-output-names = "clkxtal";
1062 };
1063
1064 infracfg_ao: infracfg_ao@10001000 {
1065 compatible = "mediatek,mt7988-infracfg_ao", "syscon";
1066 reg = <0 0x10001000 0 0x1000>;
1067 #clock-cells = <1>;
1068 };
1069
1070 infracfg: infracfg@10209000 {
1071 compatible = "mediatek,mt7988-infracfg", "syscon";
1072 reg = <0 0x10209000 0 0x1000>;
1073 #clock-cells = <1>;
1074 };
1075
1076 topckgen: topckgen@1001B000 {
1077 compatible = "mediatek,mt7988-topckgen", "syscon";
1078 reg = <0 0x1001B000 0 0x1000>;
1079 #clock-cells = <1>;
1080 };
1081
1082 apmixedsys: apmixedsys@1001E000 {
1083 compatible = "mediatek,mt7988-apmixedsys", "syscon";
1084 reg = <0 0x1001E000 0 0x1000>;
1085 #clock-cells = <1>;
1086 };
1087
1088 mcusys: mcusys@100E0000 {
1089 compatible = "mediatek,mt7988-mcusys", "syscon";
1090 reg = <0 0x100E0000 0 0x1000>;
1091 #clock-cells = <1>;
1092 };
1093
1094 clkitg: clkitg {
1095 compatible = "simple-bus";
1096 };
1097
1098 efuse: efuse@11f50000 {
1099 compatible = "mediatek,efuse";
1100 reg = <0 0x11f50000 0 0x1000>;
1101 #address-cells = <1>;
1102 #size-cells = <1>;
1103
1104 lvts_calibration: calib@918 {
1105 reg = <0x918 0x28>;
1106 };
1107 phy_calibration_p0: calib@940 {
1108 reg = <0x940 0x10>;
1109 };
1110 phy_calibration_p1: calib@954 {
1111 reg = <0x954 0x10>;
1112 };
1113 phy_calibration_p2: calib@968 {
1114 reg = <0x968 0x10>;
1115 };
1116 phy_calibration_p3: calib@97c {
1117 reg = <0x97c 0x10>;
1118 };
1119 cpufreq_calibration: calib@278 {
1120 reg = <0x278 0x1>;
1121 };
1122 };
1123};
1124
1125#include "mt7988-clkitg.dtsi"