[][kernel][mt7988][dts][Remove PEXTP SEL in PCIe node]
[Description]
Remove PCIe PEXTP SEL that already be enabled.
[Release-log]
N/A
Change-Id: Ie51d0decd52db15d140d7e8b9b9d952c5e5dfb02
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/6709532
diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988.dtsi b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988.dtsi
index 28e702e..acf45ea 100644
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988.dtsi
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988.dtsi
@@ -549,13 +549,12 @@
0x30000000 0x00 0x00200000>,
<0x82000000 0x00 0x30200000 0x00
0x30200000 0x00 0x07e00000>;
- status = "disabled";
-
- clocks = <&topckgen CK_TOP_PEXTP_P0_SEL>,
+ clocks = <&infracfg_ao CK_INFRA_PCIE_PIPE_P0>,
<&infracfg_ao CK_INFRA_PCIE_GFMUX_TL_P0>,
- <&infracfg_ao CK_INFRA_PCIE_PIPE_P0>,
- <&infracfg_ao CK_INFRA_133M_PCIE_CK_P0>,
- <&infracfg_ao CK_INFRA_PCIE_PERI_26M_CK_P0>;
+ <&infracfg_ao CK_INFRA_PCIE_PERI_26M_CK_P0>,
+ <&infracfg_ao CK_INFRA_133M_PCIE_CK_P0>;
+ clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m";
+ status = "disabled";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
@@ -585,13 +584,12 @@
0x38000000 0x00 0x00200000>,
<0x82000000 0x00 0x38200000 0x00
0x38200000 0x00 0x07e00000>;
- status = "disabled";
-
- clocks = <&topckgen CK_TOP_PEXTP_P1_SEL>,
+ clocks = <&infracfg_ao CK_INFRA_PCIE_PIPE_P1>,
<&infracfg_ao CK_INFRA_PCIE_GFMUX_TL_P1>,
- <&infracfg_ao CK_INFRA_PCIE_PIPE_P1>,
- <&infracfg_ao CK_INFRA_133M_PCIE_CK_P1>,
- <&infracfg_ao CK_INFRA_PCIE_PERI_26M_CK_P1>;
+ <&infracfg_ao CK_INFRA_PCIE_PERI_26M_CK_P1>,
+ <&infracfg_ao CK_INFRA_133M_PCIE_CK_P1>;
+ clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m";
+ status = "disabled";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
@@ -621,14 +619,12 @@
0x20000000 0x00 0x00200000>,
<0x82000000 0x00 0x20200000 0x00
0x20200000 0x00 0x07e00000>;
- status = "disabled";
-
- clocks = <&topckgen CK_TOP_PEXTP_P2_SEL>,
+ clocks = <&infracfg_ao CK_INFRA_PCIE_PIPE_P2>,
<&infracfg_ao CK_INFRA_PCIE_GFMUX_TL_P2>,
- <&infracfg_ao CK_INFRA_PCIE_PIPE_P2>,
- <&infracfg_ao CK_INFRA_133M_PCIE_CK_P2>,
<&infracfg_ao CK_INFRA_PCIE_PERI_26M_CK_P2>,
- <&infracfg_ao CK_INFRA_PCIE_PERI_26M_CK_P3>;
+ <&infracfg_ao CK_INFRA_133M_PCIE_CK_P2>;
+ clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m";
+ status = "disabled";
phys = <&xphyu3port0 PHY_TYPE_PCIE>;
phy-names = "pcie-phy";
@@ -661,13 +657,12 @@
0x28000000 0x00 0x00200000>,
<0x82000000 0x00 0x28200000 0x00
0x28200000 0x00 0x07e00000>;
- status = "disabled";
-
- clocks = <&topckgen CK_TOP_PEXTP_P3_SEL>,
+ clocks = <&infracfg_ao CK_INFRA_PCIE_PIPE_P3>,
<&infracfg_ao CK_INFRA_PCIE_GFMUX_TL_P3>,
- <&infracfg_ao CK_INFRA_PCIE_PIPE_P3>,
- <&infracfg_ao CK_INFRA_133M_PCIE_CK_P3>,
- <&infracfg_ao CK_INFRA_PCIE_PERI_26M_CK_P3>;
+ <&infracfg_ao CK_INFRA_PCIE_PERI_26M_CK_P3>,
+ <&infracfg_ao CK_INFRA_133M_PCIE_CK_P3>;
+ clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m";
+ status = "disabled";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;