developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2018 MediaTek Inc. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License as published by |
| 6 | * the Free Software Foundation; version 2 of the License |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | * |
| 13 | * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> |
| 14 | * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> |
| 15 | * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> |
| 16 | */ |
| 17 | |
| 18 | #ifndef MTK_ETH_DBG_H |
| 19 | #define MTK_ETH_DBG_H |
| 20 | |
| 21 | /* Debug Purpose Register */ |
| 22 | #define MTK_PSE_FQFC_CFG 0x100 |
| 23 | #define MTK_FE_CDM1_FSM 0x220 |
| 24 | #define MTK_FE_CDM2_FSM 0x224 |
developer | 77f3fd4 | 2021-10-05 15:16:05 +0800 | [diff] [blame] | 25 | #define MTK_FE_CDM3_FSM 0x238 |
| 26 | #define MTK_FE_CDM4_FSM 0x298 |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 27 | #define MTK_FE_GDM1_FSM 0x228 |
| 28 | #define MTK_FE_GDM2_FSM 0x22C |
| 29 | #define MTK_FE_PSE_FREE 0x240 |
| 30 | #define MTK_FE_DROP_FQ 0x244 |
| 31 | #define MTK_FE_DROP_FC 0x248 |
| 32 | #define MTK_FE_DROP_PPE 0x24C |
developer | 77f3fd4 | 2021-10-05 15:16:05 +0800 | [diff] [blame] | 33 | #define MTK_MAC_FSM(x) (0x1010C + ((x) * 0x100)) |
| 34 | #define MTK_SGMII_FALSE_CARRIER_CNT(x) (0x10060028 + ((x) * 0x10000)) |
| 35 | #define MTK_SGMII_EFUSE 0x11D008C8 |
| 36 | #define MTK_WED_RTQM_GLO_CFG 0x15010B00 |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 37 | |
| 38 | #if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 39 | #define MTK_PSE_IQ_STA(x) (0x180 + (x) * 0x4) |
| 40 | #define MTK_PSE_OQ_STA(x) (0x1A0 + (x) * 0x4) |
| 41 | #else |
| 42 | #define MTK_PSE_IQ_STA(x) (0x110 + (x) * 0x4) |
| 43 | #define MTK_PSE_OQ_STA(x) (0x118 + (x) * 0x4) |
| 44 | #endif |
| 45 | |
| 46 | #define MTKETH_MII_READ 0x89F3 |
| 47 | #define MTKETH_MII_WRITE 0x89F4 |
| 48 | #define MTKETH_ESW_REG_READ 0x89F1 |
| 49 | #define MTKETH_ESW_REG_WRITE 0x89F2 |
| 50 | #define MTKETH_MII_READ_CL45 0x89FC |
| 51 | #define MTKETH_MII_WRITE_CL45 0x89FD |
| 52 | #define REG_ESW_MAX 0xFC |
| 53 | |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 54 | #define PROCREG_ESW_CNT "esw_cnt" |
| 55 | #define PROCREG_TXRING "tx_ring" |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 56 | #define PROCREG_HWTXRING "hwtx_ring" |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 57 | #define PROCREG_RXRING "rx_ring" |
| 58 | #define PROCREG_DIR "mtketh" |
| 59 | #define PROCREG_DBG_REGS "dbg_regs" |
| 60 | #define PROCREG_HW_LRO_STATS "hw_lro_stats" |
| 61 | #define PROCREG_HW_LRO_AUTO_TLB "hw_lro_auto_tlb" |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 62 | #define PROCREG_RESET_EVENT "reset_event" |
developer | 77d03a7 | 2021-06-06 00:06:00 +0800 | [diff] [blame] | 63 | |
| 64 | /* HW LRO flush reason */ |
| 65 | #define MTK_HW_LRO_AGG_FLUSH (1) |
| 66 | #define MTK_HW_LRO_AGE_FLUSH (2) |
| 67 | #define MTK_HW_LRO_NOT_IN_SEQ_FLUSH (3) |
| 68 | #define MTK_HW_LRO_TIMESTAMP_FLUSH (4) |
| 69 | #define MTK_HW_LRO_NON_RULE_FLUSH (5) |
| 70 | |
| 71 | #define SET_PDMA_RXRING_MAX_AGG_CNT(eth, x, y) \ |
| 72 | { \ |
| 73 | u32 reg_val1 = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(x)); \ |
| 74 | u32 reg_val2 = mtk_r32(eth, MTK_LRO_CTRL_DW3_CFG(x)); \ |
| 75 | reg_val1 &= ~MTK_LRO_RING_AGG_CNT_L_MASK; \ |
| 76 | reg_val2 &= ~MTK_LRO_RING_AGG_CNT_H_MASK; \ |
| 77 | reg_val1 |= ((y) & 0x3f) << MTK_LRO_RING_AGG_CNT_L_OFFSET; \ |
| 78 | reg_val2 |= (((y) >> 6) & 0x03) << \ |
| 79 | MTK_LRO_RING_AGG_CNT_H_OFFSET; \ |
| 80 | mtk_w32(eth, reg_val1, MTK_LRO_CTRL_DW2_CFG(x)); \ |
| 81 | mtk_w32(eth, reg_val2, MTK_LRO_CTRL_DW3_CFG(x)); \ |
| 82 | } |
| 83 | |
| 84 | #define SET_PDMA_RXRING_AGG_TIME(eth, x, y) \ |
| 85 | { \ |
| 86 | u32 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(x)); \ |
| 87 | reg_val &= ~MTK_LRO_RING_AGG_TIME_MASK; \ |
| 88 | reg_val |= ((y) & 0xffff) << MTK_LRO_RING_AGG_TIME_OFFSET; \ |
| 89 | mtk_w32(eth, reg_val, MTK_LRO_CTRL_DW2_CFG(x)); \ |
| 90 | } |
| 91 | |
| 92 | #define SET_PDMA_RXRING_AGE_TIME(eth, x, y) \ |
| 93 | { \ |
| 94 | u32 reg_val1 = mtk_r32(eth, MTK_LRO_CTRL_DW1_CFG(x)); \ |
| 95 | u32 reg_val2 = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(x)); \ |
| 96 | reg_val1 &= ~MTK_LRO_RING_AGE_TIME_L_MASK; \ |
| 97 | reg_val2 &= ~MTK_LRO_RING_AGE_TIME_H_MASK; \ |
| 98 | reg_val1 |= ((y) & 0x3ff) << MTK_LRO_RING_AGE_TIME_L_OFFSET; \ |
| 99 | reg_val2 |= (((y) >> 10) & 0x03f) << \ |
| 100 | MTK_LRO_RING_AGE_TIME_H_OFFSET; \ |
| 101 | mtk_w32(eth, reg_val1, MTK_LRO_CTRL_DW1_CFG(x)); \ |
| 102 | mtk_w32(eth, reg_val2, MTK_LRO_CTRL_DW2_CFG(x)); \ |
| 103 | } |
| 104 | |
| 105 | #define SET_PDMA_LRO_BW_THRESHOLD(eth, x) \ |
| 106 | { \ |
| 107 | u32 reg_val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW2); \ |
| 108 | reg_val = (x); \ |
| 109 | mtk_w32(eth, reg_val, MTK_PDMA_LRO_CTRL_DW2); \ |
| 110 | } |
| 111 | |
| 112 | #define SET_PDMA_RXRING_VALID(eth, x, y) \ |
| 113 | { \ |
| 114 | u32 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(x)); \ |
| 115 | reg_val &= ~(0x1 << MTK_RX_PORT_VALID_OFFSET); \ |
| 116 | reg_val |= ((y) & 0x1) << MTK_RX_PORT_VALID_OFFSET; \ |
| 117 | mtk_w32(eth, reg_val, MTK_LRO_CTRL_DW2_CFG(x)); \ |
| 118 | } |
| 119 | |
| 120 | struct mtk_lro_alt_v1_info0 { |
| 121 | u32 dtp : 16; |
| 122 | u32 stp : 16; |
| 123 | }; |
| 124 | |
| 125 | struct mtk_lro_alt_v1_info1 { |
| 126 | u32 sip0 : 32; |
| 127 | }; |
| 128 | |
| 129 | struct mtk_lro_alt_v1_info2 { |
| 130 | u32 sip1 : 32; |
| 131 | }; |
| 132 | |
| 133 | struct mtk_lro_alt_v1_info3 { |
| 134 | u32 sip2 : 32; |
| 135 | }; |
| 136 | |
| 137 | struct mtk_lro_alt_v1_info4 { |
| 138 | u32 sip3 : 32; |
| 139 | }; |
| 140 | |
| 141 | struct mtk_lro_alt_v1_info5 { |
| 142 | u32 vlan_vid0 : 32; |
| 143 | }; |
| 144 | |
| 145 | struct mtk_lro_alt_v1_info6 { |
| 146 | u32 vlan_vid1 : 16; |
| 147 | u32 vlan_vid_vld : 4; |
| 148 | u32 cnt : 12; |
| 149 | }; |
| 150 | |
| 151 | struct mtk_lro_alt_v1_info7 { |
| 152 | u32 dw_len : 32; |
| 153 | }; |
| 154 | |
| 155 | struct mtk_lro_alt_v1_info8 { |
| 156 | u32 dip_id : 2; |
| 157 | u32 ipv6 : 1; |
| 158 | u32 ipv4 : 1; |
| 159 | u32 resv : 27; |
| 160 | u32 valid : 1; |
| 161 | }; |
| 162 | |
| 163 | struct mtk_lro_alt_v1 { |
| 164 | struct mtk_lro_alt_v1_info0 alt_info0; |
| 165 | struct mtk_lro_alt_v1_info1 alt_info1; |
| 166 | struct mtk_lro_alt_v1_info2 alt_info2; |
| 167 | struct mtk_lro_alt_v1_info3 alt_info3; |
| 168 | struct mtk_lro_alt_v1_info4 alt_info4; |
| 169 | struct mtk_lro_alt_v1_info5 alt_info5; |
| 170 | struct mtk_lro_alt_v1_info6 alt_info6; |
| 171 | struct mtk_lro_alt_v1_info7 alt_info7; |
| 172 | struct mtk_lro_alt_v1_info8 alt_info8; |
| 173 | }; |
| 174 | |
| 175 | struct mtk_lro_alt_v2_info0 { |
| 176 | u32 v2_id_h:3; |
| 177 | u32 v1_id:12; |
| 178 | u32 v0_id:12; |
| 179 | u32 v3_valid:1; |
| 180 | u32 v2_valid:1; |
| 181 | u32 v1_valid:1; |
| 182 | u32 v0_valid:1; |
| 183 | u32 valid:1; |
| 184 | }; |
| 185 | |
| 186 | struct mtk_lro_alt_v2_info1 { |
| 187 | u32 sip3_h:9; |
| 188 | u32 v6_valid:1; |
| 189 | u32 v4_valid:1; |
| 190 | u32 v3_id:12; |
| 191 | u32 v2_id_l:9; |
| 192 | }; |
| 193 | |
| 194 | struct mtk_lro_alt_v2_info2 { |
| 195 | u32 sip2_h:9; |
| 196 | u32 sip3_l:23; |
| 197 | }; |
| 198 | struct mtk_lro_alt_v2_info3 { |
| 199 | u32 sip1_h:9; |
| 200 | u32 sip2_l:23; |
| 201 | }; |
| 202 | struct mtk_lro_alt_v2_info4 { |
| 203 | u32 sip0_h:9; |
| 204 | u32 sip1_l:23; |
| 205 | }; |
| 206 | struct mtk_lro_alt_v2_info5 { |
| 207 | u32 dip3_h:9; |
| 208 | u32 sip0_l:23; |
| 209 | }; |
| 210 | struct mtk_lro_alt_v2_info6 { |
| 211 | u32 dip2_h:9; |
| 212 | u32 dip3_l:23; |
| 213 | }; |
| 214 | struct mtk_lro_alt_v2_info7 { |
| 215 | u32 dip1_h:9; |
| 216 | u32 dip2_l:23; |
| 217 | }; |
| 218 | struct mtk_lro_alt_v2_info8 { |
| 219 | u32 dip0_h:9; |
| 220 | u32 dip1_l:23; |
| 221 | }; |
| 222 | struct mtk_lro_alt_v2_info9 { |
| 223 | u32 sp_h:9; |
| 224 | u32 dip0_l:23; |
| 225 | }; |
| 226 | struct mtk_lro_alt_v2_info10 { |
| 227 | u32 resv:9; |
| 228 | u32 dp:16; |
| 229 | u32 sp_l:7; |
| 230 | }; |
| 231 | |
| 232 | struct mtk_lro_alt_v2 { |
| 233 | struct mtk_lro_alt_v2_info0 alt_info0; |
| 234 | struct mtk_lro_alt_v2_info1 alt_info1; |
| 235 | struct mtk_lro_alt_v2_info2 alt_info2; |
| 236 | struct mtk_lro_alt_v2_info3 alt_info3; |
| 237 | struct mtk_lro_alt_v2_info4 alt_info4; |
| 238 | struct mtk_lro_alt_v2_info5 alt_info5; |
| 239 | struct mtk_lro_alt_v2_info6 alt_info6; |
| 240 | struct mtk_lro_alt_v2_info7 alt_info7; |
| 241 | struct mtk_lro_alt_v2_info8 alt_info8; |
| 242 | struct mtk_lro_alt_v2_info9 alt_info9; |
| 243 | struct mtk_lro_alt_v2_info10 alt_info10; |
| 244 | }; |
| 245 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 246 | struct mtk_esw_reg { |
| 247 | unsigned int off; |
| 248 | unsigned int val; |
| 249 | }; |
| 250 | |
| 251 | struct mtk_mii_ioctl_data { |
developer | 3957a91 | 2021-05-13 16:44:31 +0800 | [diff] [blame] | 252 | u16 phy_id; |
| 253 | u16 reg_num; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 254 | unsigned int val_in; |
| 255 | unsigned int val_out; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 256 | }; |
| 257 | |
| 258 | #if defined(CONFIG_NET_DSA_MT7530) || defined(CONFIG_MT753X_GSW) |
| 259 | static inline bool mt7530_exist(struct mtk_eth *eth) |
| 260 | { |
| 261 | return true; |
| 262 | } |
| 263 | #else |
| 264 | static inline bool mt7530_exist(struct mtk_eth *eth) |
| 265 | { |
| 266 | return false; |
| 267 | } |
| 268 | #endif |
| 269 | |
developer | 599cda4 | 2022-05-24 15:13:31 +0800 | [diff] [blame] | 270 | extern u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg); |
| 271 | extern u32 _mtk_mdio_write(struct mtk_eth *eth, int phy_addr, |
| 272 | int phy_reg, u16 write_data); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 273 | |
developer | 8051e04 | 2022-04-08 13:26:36 +0800 | [diff] [blame] | 274 | extern atomic_t force; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 275 | |
| 276 | int debug_proc_init(struct mtk_eth *eth); |
| 277 | void debug_proc_exit(void); |
| 278 | |
| 279 | int mtketh_debugfs_init(struct mtk_eth *eth); |
| 280 | void mtketh_debugfs_exit(struct mtk_eth *eth); |
| 281 | int mtk_do_priv_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd); |
developer | e935698 | 2022-07-04 09:03:20 +0800 | [diff] [blame] | 282 | void hw_lro_stats_update(u32 ring_no, struct mtk_rx_dma_v2 *rxd); |
| 283 | void hw_lro_flush_stats_update(u32 ring_no, struct mtk_rx_dma_v2 *rxd); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 284 | |
| 285 | #endif /* MTK_ETH_DBG_H */ |