developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | #include <linux/bitfield.h> |
| 3 | #include <linux/module.h> |
| 4 | #include <linux/nvmem-consumer.h> |
developer | 2302129 | 2022-10-21 19:10:10 +0800 | [diff] [blame] | 5 | #include <linux/of_address.h> |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 6 | #include <linux/of_platform.h> |
developer | 941468f | 2023-04-10 15:21:02 +0800 | [diff] [blame] | 7 | #include <linux/pinctrl/consumer.h> |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 8 | #include <linux/phy.h> |
| 9 | |
developer | 043f7b9 | 2023-03-13 13:57:36 +0800 | [diff] [blame] | 10 | #define MTK_GPHY_ID_MT7530 0x03a29412 |
| 11 | #define MTK_GPHY_ID_MT7531 0x03a29441 |
| 12 | #ifdef CONFIG_MEDIATEK_GE_PHY_SOC |
| 13 | #define MTK_GPHY_ID_MT7981 0x03a29461 |
| 14 | #define MTK_GPHY_ID_MT7988 0x03a29481 |
| 15 | #endif |
| 16 | |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 17 | #define MTK_EXT_PAGE_ACCESS 0x1f |
| 18 | #define MTK_PHY_PAGE_STANDARD 0x0000 |
| 19 | #define MTK_PHY_PAGE_EXTENDED 0x0001 |
| 20 | #define MTK_PHY_PAGE_EXTENDED_2 0x0002 |
| 21 | #define MTK_PHY_PAGE_EXTENDED_3 0x0003 |
developer | 7fbc526 | 2023-03-28 23:44:26 +0800 | [diff] [blame] | 22 | /* Registers on Page 3 */ |
| 23 | #define MTK_PHY_LPI_REG_14 (0x14) |
| 24 | #define MTK_PHY_LPI_WAKE_TIMER_1000_MASK GENMASK(8, 0) |
| 25 | |
| 26 | #define MTK_PHY_LPI_REG_1c (0x1c) |
| 27 | #define MTK_PHY_SMI_DET_ON_THRESH_MASK GENMASK(13, 8) |
| 28 | /*******************************/ |
| 29 | |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 30 | #define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30 |
| 31 | #define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5 |
| 32 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 33 | #define ANALOG_INTERNAL_OPERATION_MAX_US (20) |
| 34 | #define ZCAL_CTRL_MIN (0) |
| 35 | #define ZCAL_CTRL_MAX (63) |
| 36 | #define TXRESERVE_MIN (0) |
| 37 | #define TXRESERVE_MAX (7) |
| 38 | |
| 39 | #define MTK_PHY_ANARG_RG (0x10) |
| 40 | #define MTK_PHY_TCLKOFFSET_MASK GENMASK(12, 8) |
| 41 | |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 42 | /* Registers on MDIO_MMD_VEND1 */ |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 43 | enum { |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 44 | MTK_PHY_MIDDLE_LEVEL_SHAPPER_0TO1 = 0, |
| 45 | MTK_PHY_1st_OVERSHOOT_LEVEL_0TO1, |
| 46 | MTK_PHY_2nd_OVERSHOOT_LEVEL_0TO1, |
| 47 | MTK_PHY_MIDDLE_LEVEL_SHAPPER_1TO0, |
| 48 | MTK_PHY_1st_OVERSHOOT_LEVEL_1TO0, |
| 49 | MTK_PHY_2nd_OVERSHOOT_LEVEL_1TO0, |
| 50 | MTK_PHY_MIDDLE_LEVEL_SHAPPER_0TON1, /* N means negative */ |
| 51 | MTK_PHY_1st_OVERSHOOT_LEVEL_0TON1, |
| 52 | MTK_PHY_2nd_OVERSHOOT_LEVEL_0TON1, |
| 53 | MTK_PHY_MIDDLE_LEVEL_SHAPPER_N1TO0, |
| 54 | MTK_PHY_1st_OVERSHOOT_LEVEL_N1TO0, |
| 55 | MTK_PHY_2nd_OVERSHOOT_LEVEL_N1TO0, |
| 56 | MTK_PHY_TX_MLT3_END, |
| 57 | }; |
developer | 02d8442 | 2021-12-24 11:48:07 +0800 | [diff] [blame] | 58 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 59 | #define MTK_PHY_TXVLD_DA_RG (0x12) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 60 | #define MTK_PHY_DA_TX_I2MPB_A_GBE_MASK GENMASK(15, 10) |
| 61 | #define MTK_PHY_DA_TX_I2MPB_A_TBT_MASK GENMASK(5, 0) |
| 62 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 63 | #define MTK_PHY_TX_I2MPB_TEST_MODE_A2 (0x16) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 64 | #define MTK_PHY_DA_TX_I2MPB_A_HBT_MASK GENMASK(15, 10) |
| 65 | #define MTK_PHY_DA_TX_I2MPB_A_TST_MASK GENMASK(5, 0) |
| 66 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 67 | #define MTK_PHY_TX_I2MPB_TEST_MODE_B1 (0x17) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 68 | #define MTK_PHY_DA_TX_I2MPB_B_GBE_MASK GENMASK(13, 8) |
| 69 | #define MTK_PHY_DA_TX_I2MPB_B_TBT_MASK GENMASK(5, 0) |
| 70 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 71 | #define MTK_PHY_TX_I2MPB_TEST_MODE_B2 (0x18) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 72 | #define MTK_PHY_DA_TX_I2MPB_B_HBT_MASK GENMASK(13, 8) |
| 73 | #define MTK_PHY_DA_TX_I2MPB_B_TST_MASK GENMASK(5, 0) |
| 74 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 75 | #define MTK_PHY_TX_I2MPB_TEST_MODE_C1 (0x19) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 76 | #define MTK_PHY_DA_TX_I2MPB_C_GBE_MASK GENMASK(13, 8) |
| 77 | #define MTK_PHY_DA_TX_I2MPB_C_TBT_MASK GENMASK(5, 0) |
| 78 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 79 | #define MTK_PHY_TX_I2MPB_TEST_MODE_C2 (0x20) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 80 | #define MTK_PHY_DA_TX_I2MPB_C_HBT_MASK GENMASK(13, 8) |
| 81 | #define MTK_PHY_DA_TX_I2MPB_C_TST_MASK GENMASK(5, 0) |
| 82 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 83 | #define MTK_PHY_TX_I2MPB_TEST_MODE_D1 (0x21) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 84 | #define MTK_PHY_DA_TX_I2MPB_D_GBE_MASK GENMASK(13, 8) |
| 85 | #define MTK_PHY_DA_TX_I2MPB_D_TBT_MASK GENMASK(5, 0) |
| 86 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 87 | #define MTK_PHY_TX_I2MPB_TEST_MODE_D2 (0x22) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 88 | #define MTK_PHY_DA_TX_I2MPB_D_HBT_MASK GENMASK(13, 8) |
| 89 | #define MTK_PHY_DA_TX_I2MPB_D_TST_MASK GENMASK(5, 0) |
| 90 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 91 | #define MTK_PHY_TANA_CAL_MODE (0xc1) |
| 92 | #define MTK_PHY_TANA_CAL_MODE_SHIFT (8) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 93 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 94 | #define MTK_PHY_RXADC_CTRL_RG7 (0xc6) |
developer | 5737403 | 2022-10-11 16:43:24 +0800 | [diff] [blame] | 95 | #define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8) |
| 96 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 97 | #define MTK_PHY_RXADC_CTRL_RG9 (0xc8) |
| 98 | #define MTK_PHY_DA_RX_PSBN_TBT_MASK GENMASK(14, 12) |
| 99 | #define MTK_PHY_DA_RX_PSBN_HBT_MASK GENMASK(10, 8) |
| 100 | #define MTK_PHY_DA_RX_PSBN_GBE_MASK GENMASK(6, 4) |
| 101 | #define MTK_PHY_DA_RX_PSBN_LP_MASK GENMASK(2, 0) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 102 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 103 | #define MTK_PHY_LDO_OUTPUT_V (0xd7) |
developer | ce26831 | 2022-12-20 16:26:11 +0800 | [diff] [blame] | 104 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 105 | #define MTK_PHY_RG_ANA_CAL_RG0 (0xdb) |
| 106 | #define MTK_PHY_RG_CAL_CKINV BIT(12) |
| 107 | #define MTK_PHY_RG_ANA_CALEN BIT(8) |
| 108 | #define MTK_PHY_RG_REXT_CALEN BIT(4) |
| 109 | #define MTK_PHY_RG_ZCALEN_A BIT(0) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 110 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 111 | #define MTK_PHY_RG_ANA_CAL_RG1 (0xdc) |
| 112 | #define MTK_PHY_RG_ZCALEN_B BIT(12) |
| 113 | #define MTK_PHY_RG_ZCALEN_C BIT(8) |
| 114 | #define MTK_PHY_RG_ZCALEN_D BIT(4) |
| 115 | #define MTK_PHY_RG_TXVOS_CALEN BIT(0) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 116 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 117 | #define MTK_PHY_RG_ANA_CAL_RG2 (0xdd) |
| 118 | #define MTK_PHY_RG_TXG_CALEN_A BIT(12) |
| 119 | #define MTK_PHY_RG_TXG_CALEN_B BIT(8) |
| 120 | #define MTK_PHY_RG_TXG_CALEN_C BIT(4) |
| 121 | #define MTK_PHY_RG_TXG_CALEN_D BIT(0) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 122 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 123 | #define MTK_PHY_RG_ANA_CAL_RG5 (0xe0) |
| 124 | #define MTK_PHY_RG_REXT_TRIM_MASK GENMASK(13, 8) |
| 125 | #define MTK_PHY_RG_ZCAL_CTRL_MASK GENMASK(5, 0) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 126 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 127 | #define MTK_PHY_RG_TX_FILTER (0xfe) |
developer | 6de96aa | 2022-09-29 16:46:18 +0800 | [diff] [blame] | 128 | |
developer | 7fbc526 | 2023-03-28 23:44:26 +0800 | [diff] [blame] | 129 | #define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120 (0x120) |
| 130 | #define MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK GENMASK(12, 8) |
| 131 | #define MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK GENMASK(4, 0) |
| 132 | |
| 133 | #define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122 (0x122) |
| 134 | #define MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK GENMASK(7, 0) |
| 135 | |
| 136 | #define MTK_PHY_RG_TESTMUX_ADC_CTRL (0x144) |
| 137 | #define MTK_PHY_RG_TXEN_DIG_MASK GENMASK(5, 5) |
| 138 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 139 | #define MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B (0x172) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 140 | #define MTK_PHY_CR_TX_AMP_OFFSET_A_MASK GENMASK(13, 8) |
| 141 | #define MTK_PHY_CR_TX_AMP_OFFSET_B_MASK GENMASK(6, 0) |
| 142 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 143 | #define MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D (0x173) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 144 | #define MTK_PHY_CR_TX_AMP_OFFSET_C_MASK GENMASK(13, 8) |
| 145 | #define MTK_PHY_CR_TX_AMP_OFFSET_D_MASK GENMASK(6, 0) |
| 146 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 147 | #define MTK_PHY_RG_AD_CAL_COMP (0x17a) |
| 148 | #define MTK_PHY_AD_CAL_COMP_OUT_SHIFT (8) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 149 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 150 | #define MTK_PHY_RG_AD_CAL_CLK (0x17b) |
| 151 | #define MTK_PHY_DA_CAL_CLK BIT(0) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 152 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 153 | #define MTK_PHY_RG_AD_CALIN (0x17c) |
| 154 | #define MTK_PHY_DA_CALIN_FLAG BIT(0) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 155 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 156 | #define MTK_PHY_RG_DASN_DAC_IN0_A (0x17d) |
developer | 510f5ed | 2023-04-10 11:42:19 +0800 | [diff] [blame] | 157 | #define MTK_PHY_DASN_DAC_IN0_A_MASK GENMASK(9, 0) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 158 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 159 | #define MTK_PHY_RG_DASN_DAC_IN0_B (0x17e) |
developer | 510f5ed | 2023-04-10 11:42:19 +0800 | [diff] [blame] | 160 | #define MTK_PHY_DASN_DAC_IN0_B_MASK GENMASK(9, 0) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 161 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 162 | #define MTK_PHY_RG_DASN_DAC_IN0_C (0x17f) |
developer | 510f5ed | 2023-04-10 11:42:19 +0800 | [diff] [blame] | 163 | #define MTK_PHY_DASN_DAC_IN0_C_MASK GENMASK(9, 0) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 164 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 165 | #define MTK_PHY_RG_DASN_DAC_IN0_D (0x180) |
developer | 510f5ed | 2023-04-10 11:42:19 +0800 | [diff] [blame] | 166 | #define MTK_PHY_DASN_DAC_IN0_D_MASK GENMASK(9, 0) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 167 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 168 | #define MTK_PHY_RG_DASN_DAC_IN1_A (0x181) |
developer | 510f5ed | 2023-04-10 11:42:19 +0800 | [diff] [blame] | 169 | #define MTK_PHY_DASN_DAC_IN1_A_MASK GENMASK(9, 0) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 170 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 171 | #define MTK_PHY_RG_DASN_DAC_IN1_B (0x182) |
developer | 510f5ed | 2023-04-10 11:42:19 +0800 | [diff] [blame] | 172 | #define MTK_PHY_DASN_DAC_IN1_B_MASK GENMASK(9, 0) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 173 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 174 | #define MTK_PHY_RG_DASN_DAC_IN1_C (0x183) |
developer | 510f5ed | 2023-04-10 11:42:19 +0800 | [diff] [blame] | 175 | #define MTK_PHY_DASN_DAC_IN1_C_MASK GENMASK(9, 0) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 176 | |
developer | 7fbc526 | 2023-03-28 23:44:26 +0800 | [diff] [blame] | 177 | #define MTK_PHY_RG_DASN_DAC_IN1_D (0x184) |
developer | 510f5ed | 2023-04-10 11:42:19 +0800 | [diff] [blame] | 178 | #define MTK_PHY_DASN_DAC_IN1_D_MASK GENMASK(9, 0) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 179 | |
developer | 7fbc526 | 2023-03-28 23:44:26 +0800 | [diff] [blame] | 180 | #define MTK_PHY_RG_DEV1E_REG19b (0x19b) |
| 181 | #define MTK_PHY_BYPASS_DSP_LPI_READY BIT(8) |
| 182 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 183 | #define MTK_PHY_RG_LP_IIR2_K1_L (0x22a) |
| 184 | #define MTK_PHY_RG_LP_IIR2_K1_U (0x22b) |
| 185 | #define MTK_PHY_RG_LP_IIR2_K2_L (0x22c) |
| 186 | #define MTK_PHY_RG_LP_IIR2_K2_U (0x22d) |
| 187 | #define MTK_PHY_RG_LP_IIR2_K3_L (0x22e) |
| 188 | #define MTK_PHY_RG_LP_IIR2_K3_U (0x22f) |
| 189 | #define MTK_PHY_RG_LP_IIR2_K4_L (0x230) |
| 190 | #define MTK_PHY_RG_LP_IIR2_K4_U (0x231) |
| 191 | #define MTK_PHY_RG_LP_IIR2_K5_L (0x232) |
| 192 | #define MTK_PHY_RG_LP_IIR2_K5_U (0x233) |
developer | 7581999 | 2023-03-08 20:49:03 +0800 | [diff] [blame] | 193 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 194 | #define MTK_PHY_RG_DEV1E_REG234 (0x234) |
| 195 | #define MTK_PHY_TR_OPEN_LOOP_EN_MASK GENMASK(0, 0) |
| 196 | #define MTK_PHY_LPF_X_AVERAGE_MASK GENMASK(7, 4) |
developer | 7fbc526 | 2023-03-28 23:44:26 +0800 | [diff] [blame] | 197 | #define MTK_PHY_TR_LP_IIR_EEE_EN BIT(12) |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 198 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 199 | #define MTK_PHY_RG_LPF_CNT_VAL (0x235) |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 200 | |
developer | 7fbc526 | 2023-03-28 23:44:26 +0800 | [diff] [blame] | 201 | #define MTK_PHY_RG_DEV1E_REG238 (0x238) |
| 202 | #define MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK GENMASK(8, 0) |
| 203 | #define MTK_PHY_LPI_SLV_SEND_TX_EN BIT(12) |
| 204 | |
| 205 | #define MTK_PHY_RG_DEV1E_REG239 (0x239) |
| 206 | #define MTK_PHY_LPI_SEND_LOC_TIMER_MASK GENMASK(8, 0) |
| 207 | #define MTK_PHY_LPI_TXPCS_LOC_RCV BIT(12) |
| 208 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 209 | #define MTK_PHY_RG_DEV1E_REG27C (0x27c) |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 210 | #define MTK_PHY_VGASTATE_FFE_THR_ST1_MASK GENMASK(12, 8) |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 211 | #define MTK_PHY_RG_DEV1E_REG27D (0x27d) |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 212 | #define MTK_PHY_VGASTATE_FFE_THR_ST2_MASK GENMASK(4, 0) |
developer | 68f6e10 | 2022-11-22 17:35:00 +0800 | [diff] [blame] | 213 | |
developer | 7fbc526 | 2023-03-28 23:44:26 +0800 | [diff] [blame] | 214 | #define MTK_PHY_RG_DEV1E_REG2C7 (0x2c7) |
| 215 | #define MTK_PHY_MAX_GAIN_MASK GENMASK(4, 0) |
| 216 | #define MTK_PHY_MIN_GAIN_MASK GENMASK(12, 8) |
| 217 | |
| 218 | #define MTK_PHY_RG_DEV1E_REG2D1 (0x2d1) |
| 219 | #define MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK GENMASK(7, 0) |
| 220 | #define MTK_PHY_LPI_SKIP_SD_SLV_TR BIT(8) |
| 221 | #define MTK_PHY_LPI_TR_READY BIT(9) |
| 222 | #define MTK_PHY_LPI_VCO_EEE_STG0_EN BIT(10) |
| 223 | |
| 224 | #define MTK_PHY_RG_DEV1E_REG323 (0x323) |
| 225 | #define MTK_PHY_EEE_WAKE_MAS_INT_DC BIT(0) |
| 226 | #define MTK_PHY_EEE_WAKE_SLV_INT_DC BIT(4) |
| 227 | |
| 228 | #define MTK_PHY_RG_DEV1E_REG324 (0x324) |
| 229 | #define MTK_PHY_SMI_DETCNT_MAX_MASK GENMASK(5, 0) |
| 230 | #define MTK_PHY_SMI_DET_MAX_EN BIT(8) |
| 231 | |
| 232 | #define MTK_PHY_RG_DEV1E_REG326 (0x326) |
| 233 | #define MTK_PHY_LPI_MODE_SD_ON BIT(0) |
| 234 | #define MTK_PHY_RESET_RANDUPD_CNT BIT(1) |
| 235 | #define MTK_PHY_TREC_UPDATE_ENAB_CLR BIT(2) |
| 236 | #define MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF BIT(4) |
| 237 | #define MTK_PHY_TR_READY_SKIP_AFE_WAKEUP BIT(5) |
| 238 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 239 | #define MTK_PHY_LDO_PUMP_EN_PAIRAB (0x502) |
| 240 | #define MTK_PHY_LDO_PUMP_EN_PAIRCD (0x503) |
developer | 7581999 | 2023-03-08 20:49:03 +0800 | [diff] [blame] | 241 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 242 | #define MTK_PHY_DA_TX_R50_PAIR_A (0x53d) |
| 243 | #define MTK_PHY_DA_TX_R50_PAIR_B (0x53e) |
| 244 | #define MTK_PHY_DA_TX_R50_PAIR_C (0x53f) |
| 245 | #define MTK_PHY_DA_TX_R50_PAIR_D (0x540) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 246 | |
| 247 | /* Registers on MDIO_MMD_VEND2 */ |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 248 | #define MTK_PHY_LED0_ON_CTRL (0x24) |
developer | 2302129 | 2022-10-21 19:10:10 +0800 | [diff] [blame] | 249 | #define MTK_PHY_LED0_ON_MASK GENMASK(6, 0) |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 250 | #define MTK_PHY_LED0_ON_LINK1000 BIT(0) |
| 251 | #define MTK_PHY_LED0_ON_LINK100 BIT(1) |
| 252 | #define MTK_PHY_LED0_ON_LINK10 BIT(2) |
| 253 | #define MTK_PHY_LED0_ON_LINKDOWN BIT(3) |
| 254 | #define MTK_PHY_LED0_ON_FDX BIT(4) /* Full duplex */ |
| 255 | #define MTK_PHY_LED0_ON_HDX BIT(5) /* Half duplex */ |
| 256 | #define MTK_PHY_LED0_FORCE_ON BIT(6) |
| 257 | #define MTK_PHY_LED0_POLARITY BIT(14) |
| 258 | #define MTK_PHY_LED0_ENABLE BIT(15) |
developer | 2302129 | 2022-10-21 19:10:10 +0800 | [diff] [blame] | 259 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 260 | #define MTK_PHY_LED0_BLINK_CTRL (0x25) |
| 261 | #define MTK_PHY_LED0_1000TX BIT(0) |
| 262 | #define MTK_PHY_LED0_1000RX BIT(1) |
| 263 | #define MTK_PHY_LED0_100TX BIT(2) |
| 264 | #define MTK_PHY_LED0_100RX BIT(3) |
| 265 | #define MTK_PHY_LED0_10TX BIT(4) |
| 266 | #define MTK_PHY_LED0_10RX BIT(5) |
| 267 | #define MTK_PHY_LED0_COLLISION BIT(6) |
| 268 | #define MTK_PHY_LED0_RX_CRC_ERR BIT(7) |
| 269 | #define MTK_PHY_LED0_RX_IDLE_ERR BIT(8) |
| 270 | #define MTK_PHY_LED0_FORCE_BLINK BIT(9) |
developer | 8bc5dca | 2022-10-24 17:15:12 +0800 | [diff] [blame] | 271 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 272 | #define MTK_PHY_ANA_TEST_BUS_CTRL_RG (0x100) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 273 | #define MTK_PHY_ANA_TEST_MODE_MASK GENMASK(15, 8) |
| 274 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 275 | #define MTK_PHY_RG_DASN_TXT_DMY2 (0x110) |
| 276 | #define MTK_PHY_TST_DMY2_MASK GENMASK(5, 0) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 277 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 278 | #define MTK_PHY_RG_BG_RASEL (0x115) |
| 279 | #define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 280 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 281 | /* These macro privides efuse parsing for internal phy. */ |
| 282 | #define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0)) |
| 283 | #define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0)) |
| 284 | #define EFS_DA_TX_I2MPB_C(x) (((x) >> 12) & GENMASK(5, 0)) |
| 285 | #define EFS_DA_TX_I2MPB_D(x) (((x) >> 18) & GENMASK(5, 0)) |
| 286 | #define EFS_DA_TX_AMP_OFFSET_A(x) (((x) >> 24) & GENMASK(5, 0)) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 287 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 288 | #define EFS_DA_TX_AMP_OFFSET_B(x) (((x) >> 0) & GENMASK(5, 0)) |
| 289 | #define EFS_DA_TX_AMP_OFFSET_C(x) (((x) >> 6) & GENMASK(5, 0)) |
| 290 | #define EFS_DA_TX_AMP_OFFSET_D(x) (((x) >> 12) & GENMASK(5, 0)) |
| 291 | #define EFS_DA_TX_R50_A(x) (((x) >> 18) & GENMASK(5, 0)) |
| 292 | #define EFS_DA_TX_R50_B(x) (((x) >> 24) & GENMASK(5, 0)) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 293 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 294 | #define EFS_DA_TX_R50_C(x) (((x) >> 0) & GENMASK(5, 0)) |
| 295 | #define EFS_DA_TX_R50_D(x) (((x) >> 6) & GENMASK(5, 0)) |
| 296 | #define EFS_DA_TX_R50_A_10M(x) (((x) >> 12) & GENMASK(5, 0)) |
| 297 | #define EFS_DA_TX_R50_B_10M(x) (((x) >> 18) & GENMASK(5, 0)) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 298 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 299 | #define EFS_RG_BG_RASEL(x) (((x) >> 4) & GENMASK(2, 0)) |
| 300 | #define EFS_RG_REXT_TRIM(x) (((x) >> 7) & GENMASK(5, 0)) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 301 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 302 | enum { |
| 303 | NO_PAIR, |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 304 | PAIR_A, |
| 305 | PAIR_B, |
| 306 | PAIR_C, |
| 307 | PAIR_D, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 308 | }; |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 309 | |
developer | 2302129 | 2022-10-21 19:10:10 +0800 | [diff] [blame] | 310 | enum { |
| 311 | GPHY_PORT0, |
| 312 | GPHY_PORT1, |
| 313 | GPHY_PORT2, |
| 314 | GPHY_PORT3, |
| 315 | }; |
| 316 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 317 | enum calibration_mode { |
| 318 | EFUSE_K, |
| 319 | SW_K |
| 320 | }; |
| 321 | |
| 322 | enum CAL_ITEM { |
| 323 | REXT, |
| 324 | TX_OFFSET, |
| 325 | TX_AMP, |
| 326 | TX_R50, |
| 327 | TX_VCM |
| 328 | }; |
| 329 | |
| 330 | enum CAL_MODE { |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 331 | EFUSE_M, |
| 332 | SW_M |
| 333 | }; |
| 334 | |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 335 | const u8 mt798x_zcal_to_r50[64] = { |
| 336 | 7, 8, 9, 9, 10, 10, 11, 11, |
| 337 | 12, 13, 13, 14, 14, 15, 16, 16, |
| 338 | 17, 18, 18, 19, 20, 21, 21, 22, |
| 339 | 23, 24, 24, 25, 26, 27, 28, 29, |
| 340 | 30, 31, 32, 33, 34, 35, 36, 37, |
| 341 | 38, 40, 41, 42, 43, 45, 46, 48, |
| 342 | 49, 51, 52, 54, 55, 57, 59, 61, |
| 343 | 62, 63, 63, 63, 63, 63, 63, 63 |
| 344 | }; |
| 345 | |
| 346 | const char pair[4] = {'A', 'B', 'C', 'D'}; |
| 347 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 348 | static int mtk_gephy_read_page(struct phy_device *phydev) |
| 349 | { |
| 350 | return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); |
| 351 | } |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 352 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 353 | static int mtk_gephy_write_page(struct phy_device *phydev, int page) |
| 354 | { |
| 355 | return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page); |
| 356 | } |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 357 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 358 | static void mtk_gephy_config_init(struct phy_device *phydev) |
| 359 | { |
| 360 | /* Disable EEE */ |
| 361 | phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 362 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 363 | /* Enable HW auto downshift */ |
| 364 | phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED, 0x14, 0, BIT(4)); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 365 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 366 | /* Increase SlvDPSready time */ |
| 367 | phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); |
| 368 | __phy_write(phydev, 0x10, 0xafae); |
| 369 | __phy_write(phydev, 0x12, 0x2f); |
| 370 | __phy_write(phydev, 0x10, 0x8fae); |
| 371 | phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 372 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 373 | /* Adjust 100_mse_threshold */ |
| 374 | phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x123, 0xffff); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 375 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 376 | /* Disable mcc */ |
| 377 | phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xa6, 0x300); |
| 378 | } |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 379 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 380 | static int mt7530_phy_config_init(struct phy_device *phydev) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 381 | { |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 382 | mtk_gephy_config_init(phydev); |
| 383 | |
| 384 | /* Increase post_update_timer */ |
| 385 | phy_write_paged(phydev, MTK_PHY_PAGE_EXTENDED_3, 0x11, 0x4b); |
| 386 | |
| 387 | return 0; |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 388 | } |
| 389 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 390 | static int mt7531_phy_config_init(struct phy_device *phydev) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 391 | { |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 392 | mtk_gephy_config_init(phydev); |
| 393 | |
| 394 | /* PHY link down power saving enable */ |
| 395 | phy_set_bits(phydev, 0x17, BIT(4)); |
| 396 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 0xc6, 0x300); |
| 397 | |
| 398 | /* Set TX Pair delay selection */ |
| 399 | phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x13, 0x404); |
| 400 | phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x14, 0x404); |
| 401 | |
| 402 | return 0; |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 403 | } |
| 404 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 405 | #ifdef CONFIG_MEDIATEK_GE_PHY_SOC |
| 406 | /* One calibration cycle consists of: |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 407 | * 1.Set DA_CALIN_FLAG high to start calibration. Keep it high |
| 408 | * until AD_CAL_COMP is ready to output calibration result. |
| 409 | * 2.Wait until DA_CAL_CLK is available. |
| 410 | * 3.Fetch AD_CAL_COMP_OUT. |
| 411 | */ |
| 412 | static int cal_cycle(struct phy_device *phydev, int devad, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 413 | u32 regnum, u16 mask, u16 cal_val) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 414 | { |
| 415 | unsigned long timeout; |
| 416 | int reg_val; |
| 417 | int ret; |
| 418 | |
| 419 | phy_modify_mmd(phydev, devad, regnum, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 420 | mask, cal_val); |
| 421 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, |
| 422 | MTK_PHY_DA_CALIN_FLAG); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 423 | |
| 424 | timeout = jiffies + usecs_to_jiffies(ANALOG_INTERNAL_OPERATION_MAX_US); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 425 | do { |
| 426 | reg_val = phy_read_mmd(phydev, MDIO_MMD_VEND1, |
| 427 | MTK_PHY_RG_AD_CAL_CLK); |
| 428 | } while (time_before(jiffies, timeout) && !(reg_val & BIT(0))); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 429 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 430 | if (!(reg_val & BIT(0))) { |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 431 | dev_err(&phydev->mdio.dev, "Calibration cycle timeout\n"); |
| 432 | return -ETIMEDOUT; |
| 433 | } |
| 434 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 435 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, |
| 436 | MTK_PHY_DA_CALIN_FLAG); |
| 437 | ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP) >> |
| 438 | MTK_PHY_AD_CAL_COMP_OUT_SHIFT; |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 439 | dev_dbg(&phydev->mdio.dev, "cal_val: 0x%x, ret: %d\n", cal_val, ret); |
| 440 | |
| 441 | return ret; |
| 442 | } |
| 443 | |
| 444 | static int rext_fill_result(struct phy_device *phydev, u16 *buf) |
| 445 | { |
| 446 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 447 | MTK_PHY_RG_REXT_TRIM_MASK, buf[0] << 8); |
| 448 | phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_BG_RASEL, |
| 449 | MTK_PHY_RG_BG_RASEL_MASK, buf[1]); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 450 | |
| 451 | return 0; |
| 452 | } |
| 453 | |
| 454 | static int rext_cal_efuse(struct phy_device *phydev, u32 *buf) |
| 455 | { |
| 456 | u16 rext_cal_val[2]; |
| 457 | |
| 458 | rext_cal_val[0] = EFS_RG_REXT_TRIM(buf[3]); |
| 459 | rext_cal_val[1] = EFS_RG_BG_RASEL(buf[3]); |
| 460 | rext_fill_result(phydev, rext_cal_val); |
| 461 | |
| 462 | return 0; |
| 463 | } |
| 464 | |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 465 | static int tx_offset_fill_result(struct phy_device *phydev, u16 *buf) |
| 466 | { |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 467 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 468 | MTK_PHY_CR_TX_AMP_OFFSET_A_MASK, buf[0] << 8); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 469 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 470 | MTK_PHY_CR_TX_AMP_OFFSET_B_MASK, buf[1]); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 471 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 472 | MTK_PHY_CR_TX_AMP_OFFSET_C_MASK, buf[2] << 8); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 473 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 474 | MTK_PHY_CR_TX_AMP_OFFSET_D_MASK, buf[3]); |
| 475 | |
| 476 | return 0; |
| 477 | } |
| 478 | |
| 479 | static int tx_offset_cal_efuse(struct phy_device *phydev, u32 *buf) |
| 480 | { |
| 481 | u16 tx_offset_cal_val[4]; |
| 482 | |
| 483 | tx_offset_cal_val[0] = EFS_DA_TX_AMP_OFFSET_A(buf[0]); |
| 484 | tx_offset_cal_val[1] = EFS_DA_TX_AMP_OFFSET_B(buf[1]); |
| 485 | tx_offset_cal_val[2] = EFS_DA_TX_AMP_OFFSET_C(buf[1]); |
| 486 | tx_offset_cal_val[3] = EFS_DA_TX_AMP_OFFSET_D(buf[1]); |
| 487 | |
| 488 | tx_offset_fill_result(phydev, tx_offset_cal_val); |
| 489 | |
| 490 | return 0; |
| 491 | } |
| 492 | |
| 493 | static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf) |
| 494 | { |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 495 | int i; |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 496 | int bias[16] = {0}; |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 497 | const int vals_9461[16] = { 7, 1, 4, 7, |
| 498 | 7, 1, 4, 7, |
| 499 | 7, 1, 4, 7, |
| 500 | 7, 1, 4, 7 }; |
| 501 | const int vals_9481[16] = { 10, 6, 6, 10, |
| 502 | 10, 6, 6, 10, |
| 503 | 10, 6, 6, 10, |
| 504 | 10, 6, 6, 10 }; |
| 505 | |
| 506 | switch (phydev->drv->phy_id) { |
developer | 043f7b9 | 2023-03-13 13:57:36 +0800 | [diff] [blame] | 507 | case MTK_GPHY_ID_MT7981: |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 508 | /* We add some calibration to efuse values |
| 509 | * due to board level influence. |
| 510 | * GBE: +7, TBT: +1, HBT: +4, TST: +7 |
| 511 | */ |
| 512 | memcpy(bias, (const void *)vals_9461, sizeof(bias)); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 513 | break; |
developer | 043f7b9 | 2023-03-13 13:57:36 +0800 | [diff] [blame] | 514 | case MTK_GPHY_ID_MT7988: |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 515 | memcpy(bias, (const void *)vals_9481, sizeof(bias)); |
| 516 | break; |
| 517 | default: |
| 518 | break; |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 519 | } |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 520 | |
developer | dc3e950 | 2022-12-02 18:10:42 +0800 | [diff] [blame] | 521 | /* Prevent overflow */ |
| 522 | for (i = 0; i < 12; i++) { |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 523 | if (buf[i >> 2] + bias[i] > 63) { |
| 524 | buf[i >> 2] = 63; |
developer | dc3e950 | 2022-12-02 18:10:42 +0800 | [diff] [blame] | 525 | bias[i] = 0; |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 526 | } else if (buf[i >> 2] + bias[i] < 0) { |
developer | dc3e950 | 2022-12-02 18:10:42 +0800 | [diff] [blame] | 527 | /* Bias caused by board design may change in the future. |
| 528 | * So check negative cases, too. |
| 529 | */ |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 530 | buf[i >> 2] = 0; |
developer | dc3e950 | 2022-12-02 18:10:42 +0800 | [diff] [blame] | 531 | bias[i] = 0; |
| 532 | } |
| 533 | } |
| 534 | |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 535 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 536 | MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, (buf[0] + bias[0]) << 10); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 537 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 538 | MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, buf[0] + bias[1]); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 539 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 540 | MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, (buf[0] + bias[2]) << 10); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 541 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 542 | MTK_PHY_DA_TX_I2MPB_A_TST_MASK, buf[0] + bias[3]); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 543 | |
| 544 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 545 | MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, (buf[1] + bias[4]) << 8); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 546 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 547 | MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, buf[1] + bias[5]); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 548 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 549 | MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, (buf[1] + bias[6]) << 8); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 550 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 551 | MTK_PHY_DA_TX_I2MPB_B_TST_MASK, buf[1] + bias[7]); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 552 | |
| 553 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 554 | MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, (buf[2] + bias[8]) << 8); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 555 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 556 | MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, buf[2] + bias[9]); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 557 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 558 | MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, (buf[2] + bias[10]) << 8); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 559 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 560 | MTK_PHY_DA_TX_I2MPB_C_TST_MASK, buf[2] + bias[11]); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 561 | |
| 562 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 563 | MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, (buf[3] + bias[12]) << 8); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 564 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 565 | MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, buf[3] + bias[13]); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 566 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 567 | MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, (buf[3] + bias[14]) << 8); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 568 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 569 | MTK_PHY_DA_TX_I2MPB_D_TST_MASK, buf[3] + bias[15]); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 570 | |
| 571 | return 0; |
| 572 | } |
| 573 | |
| 574 | static int tx_amp_cal_efuse(struct phy_device *phydev, u32 *buf) |
| 575 | { |
| 576 | u16 tx_amp_cal_val[4]; |
| 577 | |
| 578 | tx_amp_cal_val[0] = EFS_DA_TX_I2MPB_A(buf[0]); |
| 579 | tx_amp_cal_val[1] = EFS_DA_TX_I2MPB_B(buf[0]); |
| 580 | tx_amp_cal_val[2] = EFS_DA_TX_I2MPB_C(buf[0]); |
| 581 | tx_amp_cal_val[3] = EFS_DA_TX_I2MPB_D(buf[0]); |
| 582 | tx_amp_fill_result(phydev, tx_amp_cal_val); |
| 583 | |
| 584 | return 0; |
| 585 | } |
| 586 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 587 | static int tx_r50_fill_result(struct phy_device *phydev, u16 tx_r50_cal_val, |
| 588 | u8 txg_calen_x) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 589 | { |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 590 | int bias = 0; |
| 591 | u16 reg, val; |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 592 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 593 | switch (phydev->drv->phy_id) { |
developer | 043f7b9 | 2023-03-13 13:57:36 +0800 | [diff] [blame] | 594 | case MTK_GPHY_ID_MT7988: |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 595 | { |
| 596 | bias = -2; |
| 597 | break; |
developer | dc3e950 | 2022-12-02 18:10:42 +0800 | [diff] [blame] | 598 | } |
developer | 043f7b9 | 2023-03-13 13:57:36 +0800 | [diff] [blame] | 599 | /* MTK_GPHY_ID_MT7981 enters default case */ |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 600 | default: |
| 601 | break; |
| 602 | } |
| 603 | |
| 604 | val = clamp_val(bias + tx_r50_cal_val, 0, 63); |
| 605 | |
| 606 | switch (txg_calen_x) { |
| 607 | case PAIR_A: |
| 608 | reg = MTK_PHY_DA_TX_R50_PAIR_A; |
| 609 | break; |
| 610 | case PAIR_B: |
| 611 | reg = MTK_PHY_DA_TX_R50_PAIR_B; |
| 612 | break; |
| 613 | case PAIR_C: |
| 614 | reg = MTK_PHY_DA_TX_R50_PAIR_C; |
| 615 | break; |
| 616 | case PAIR_D: |
| 617 | reg = MTK_PHY_DA_TX_R50_PAIR_D; |
| 618 | break; |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 619 | } |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 620 | |
| 621 | phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, val | val << 8); |
| 622 | |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 623 | return 0; |
| 624 | } |
| 625 | |
| 626 | static int tx_r50_cal_efuse(struct phy_device *phydev, u32 *buf, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 627 | u8 txg_calen_x) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 628 | { |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 629 | u16 tx_r50_cal_val; |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 630 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 631 | switch (txg_calen_x) { |
| 632 | case PAIR_A: |
| 633 | tx_r50_cal_val = EFS_DA_TX_R50_A(buf[1]); |
| 634 | break; |
| 635 | case PAIR_B: |
| 636 | tx_r50_cal_val = EFS_DA_TX_R50_B(buf[1]); |
| 637 | break; |
| 638 | case PAIR_C: |
| 639 | tx_r50_cal_val = EFS_DA_TX_R50_C(buf[2]); |
| 640 | break; |
| 641 | case PAIR_D: |
| 642 | tx_r50_cal_val = EFS_DA_TX_R50_D(buf[2]); |
| 643 | break; |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 644 | } |
| 645 | tx_r50_fill_result(phydev, tx_r50_cal_val, txg_calen_x); |
| 646 | |
| 647 | return 0; |
| 648 | } |
| 649 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 650 | static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 651 | { |
| 652 | u8 lower_idx, upper_idx, txreserve_val; |
| 653 | u8 lower_ret, upper_ret; |
| 654 | int ret; |
| 655 | |
| 656 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 657 | MTK_PHY_RG_ANA_CALEN); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 658 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 659 | MTK_PHY_RG_CAL_CKINV); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 660 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 661 | MTK_PHY_RG_TXVOS_CALEN); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 662 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 663 | switch (rg_txreserve_x) { |
| 664 | case PAIR_A: |
developer | 510f5ed | 2023-04-10 11:42:19 +0800 | [diff] [blame] | 665 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, |
| 666 | MTK_PHY_RG_DASN_DAC_IN0_A, |
| 667 | MTK_PHY_DASN_DAC_IN0_A_MASK); |
| 668 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, |
| 669 | MTK_PHY_RG_DASN_DAC_IN1_A, |
| 670 | MTK_PHY_DASN_DAC_IN1_A_MASK); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 671 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, |
| 672 | MTK_PHY_RG_ANA_CAL_RG0, |
| 673 | MTK_PHY_RG_ZCALEN_A); |
| 674 | break; |
| 675 | case PAIR_B: |
developer | 510f5ed | 2023-04-10 11:42:19 +0800 | [diff] [blame] | 676 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, |
| 677 | MTK_PHY_RG_DASN_DAC_IN0_B, |
| 678 | MTK_PHY_DASN_DAC_IN0_B_MASK); |
| 679 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, |
| 680 | MTK_PHY_RG_DASN_DAC_IN1_B, |
| 681 | MTK_PHY_DASN_DAC_IN1_B_MASK); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 682 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, |
| 683 | MTK_PHY_RG_ANA_CAL_RG1, |
| 684 | MTK_PHY_RG_ZCALEN_B); |
| 685 | break; |
| 686 | case PAIR_C: |
developer | 510f5ed | 2023-04-10 11:42:19 +0800 | [diff] [blame] | 687 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, |
| 688 | MTK_PHY_RG_DASN_DAC_IN0_C, |
| 689 | MTK_PHY_DASN_DAC_IN0_C_MASK); |
| 690 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, |
| 691 | MTK_PHY_RG_DASN_DAC_IN1_C, |
| 692 | MTK_PHY_DASN_DAC_IN1_C_MASK); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 693 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, |
| 694 | MTK_PHY_RG_ANA_CAL_RG1, |
| 695 | MTK_PHY_RG_ZCALEN_C); |
| 696 | break; |
| 697 | case PAIR_D: |
developer | 510f5ed | 2023-04-10 11:42:19 +0800 | [diff] [blame] | 698 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, |
| 699 | MTK_PHY_RG_DASN_DAC_IN0_D, |
| 700 | MTK_PHY_DASN_DAC_IN0_D_MASK); |
| 701 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, |
| 702 | MTK_PHY_RG_DASN_DAC_IN1_D, |
| 703 | MTK_PHY_DASN_DAC_IN1_D_MASK); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 704 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, |
| 705 | MTK_PHY_RG_ANA_CAL_RG1, |
| 706 | MTK_PHY_RG_ZCALEN_D); |
| 707 | break; |
| 708 | default: |
| 709 | ret = -EINVAL; |
| 710 | goto restore; |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 711 | } |
| 712 | |
| 713 | lower_idx = TXRESERVE_MIN; |
| 714 | upper_idx = TXRESERVE_MAX; |
| 715 | |
| 716 | dev_dbg(&phydev->mdio.dev, "Start TX-VCM SW cal.\n"); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 717 | while ((upper_idx - lower_idx) > 1) { |
| 718 | txreserve_val = DIV_ROUND_CLOSEST(lower_idx + upper_idx, 2); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 719 | ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 720 | MTK_PHY_DA_RX_PSBN_TBT_MASK | |
| 721 | MTK_PHY_DA_RX_PSBN_HBT_MASK | |
| 722 | MTK_PHY_DA_RX_PSBN_GBE_MASK | |
| 723 | MTK_PHY_DA_RX_PSBN_LP_MASK, |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 724 | txreserve_val << 12 | txreserve_val << 8 | |
| 725 | txreserve_val << 4 | txreserve_val); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 726 | if (ret == 1) { |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 727 | upper_idx = txreserve_val; |
developer | 78aa7b9 | 2021-12-29 15:22:10 +0800 | [diff] [blame] | 728 | upper_ret = ret; |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 729 | } else if (ret == 0) { |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 730 | lower_idx = txreserve_val; |
developer | 78aa7b9 | 2021-12-29 15:22:10 +0800 | [diff] [blame] | 731 | lower_ret = ret; |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 732 | } else { |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 733 | goto restore; |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 734 | } |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 735 | } |
| 736 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 737 | if (lower_idx == TXRESERVE_MIN) { |
| 738 | lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1, |
| 739 | MTK_PHY_RXADC_CTRL_RG9, |
| 740 | MTK_PHY_DA_RX_PSBN_TBT_MASK | |
| 741 | MTK_PHY_DA_RX_PSBN_HBT_MASK | |
| 742 | MTK_PHY_DA_RX_PSBN_GBE_MASK | |
| 743 | MTK_PHY_DA_RX_PSBN_LP_MASK, |
| 744 | lower_idx << 12 | lower_idx << 8 | |
| 745 | lower_idx << 4 | lower_idx); |
| 746 | ret = lower_ret; |
| 747 | } else if (upper_idx == TXRESERVE_MAX) { |
| 748 | upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1, |
| 749 | MTK_PHY_RXADC_CTRL_RG9, |
| 750 | MTK_PHY_DA_RX_PSBN_TBT_MASK | |
| 751 | MTK_PHY_DA_RX_PSBN_HBT_MASK | |
| 752 | MTK_PHY_DA_RX_PSBN_GBE_MASK | |
| 753 | MTK_PHY_DA_RX_PSBN_LP_MASK, |
| 754 | upper_idx << 12 | upper_idx << 8 | |
| 755 | upper_idx << 4 | upper_idx); |
| 756 | ret = upper_ret; |
developer | 78aa7b9 | 2021-12-29 15:22:10 +0800 | [diff] [blame] | 757 | } |
| 758 | if (ret < 0) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 759 | goto restore; |
| 760 | |
developer | 78aa7b9 | 2021-12-29 15:22:10 +0800 | [diff] [blame] | 761 | /* We calibrate TX-VCM in different logic. Check upper index and then |
| 762 | * lower index. If this calibration is valid, apply lower index's result. |
| 763 | */ |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 764 | ret = upper_ret - lower_ret; |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 765 | if (ret == 1) { |
| 766 | ret = 0; |
developer | b5c76d4 | 2022-08-18 15:45:33 +0800 | [diff] [blame] | 767 | /* Make sure we use upper_idx in our calibration system */ |
| 768 | cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 769 | MTK_PHY_DA_RX_PSBN_TBT_MASK | |
| 770 | MTK_PHY_DA_RX_PSBN_HBT_MASK | |
| 771 | MTK_PHY_DA_RX_PSBN_GBE_MASK | |
| 772 | MTK_PHY_DA_RX_PSBN_LP_MASK, |
| 773 | upper_idx << 12 | upper_idx << 8 | |
| 774 | upper_idx << 4 | upper_idx); |
| 775 | dev_info(&phydev->mdio.dev, "TX-VCM SW cal result: 0x%x\n", |
| 776 | upper_idx); |
| 777 | } else if (lower_idx == TXRESERVE_MIN && upper_ret == 1 && |
| 778 | lower_ret == 1) { |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 779 | ret = 0; |
| 780 | cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 781 | MTK_PHY_DA_RX_PSBN_TBT_MASK | |
| 782 | MTK_PHY_DA_RX_PSBN_HBT_MASK | |
| 783 | MTK_PHY_DA_RX_PSBN_GBE_MASK | |
| 784 | MTK_PHY_DA_RX_PSBN_LP_MASK, |
| 785 | lower_idx << 12 | lower_idx << 8 | |
| 786 | lower_idx << 4 | lower_idx); |
| 787 | dev_warn(&phydev->mdio.dev, |
| 788 | "TX-VCM SW cal result at low margin 0x%x\n", |
| 789 | lower_idx); |
| 790 | } else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 && |
| 791 | lower_ret == 0) { |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 792 | ret = 0; |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 793 | dev_warn(&phydev->mdio.dev, |
| 794 | "TX-VCM SW cal result at high margin 0x%x\n", |
| 795 | upper_idx); |
| 796 | } else { |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 797 | ret = -EINVAL; |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 798 | } |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 799 | |
| 800 | restore: |
| 801 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 802 | MTK_PHY_RG_ANA_CALEN); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 803 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 804 | MTK_PHY_RG_TXVOS_CALEN); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 805 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 806 | MTK_PHY_RG_ZCALEN_A); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 807 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 808 | MTK_PHY_RG_ZCALEN_B | MTK_PHY_RG_ZCALEN_C | |
| 809 | MTK_PHY_RG_ZCALEN_D); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 810 | |
| 811 | return ret; |
| 812 | } |
| 813 | |
developer | dd59856 | 2023-03-28 23:57:03 +0800 | [diff] [blame] | 814 | static inline void mt798x_phy_common_finetune(struct phy_device *phydev) |
developer | 02d8442 | 2021-12-24 11:48:07 +0800 | [diff] [blame] | 815 | { |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 816 | u32 i; |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 817 | |
developer | dd59856 | 2023-03-28 23:57:03 +0800 | [diff] [blame] | 818 | phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); |
| 819 | /* EnabRandUpdTrig = 1 */ |
| 820 | __phy_write(phydev, 0x11, 0x2f00); |
| 821 | __phy_write(phydev, 0x12, 0xe); |
| 822 | __phy_write(phydev, 0x10, 0x8fb0); |
| 823 | |
| 824 | /* NormMseLoThresh = 85 */ |
| 825 | __phy_write(phydev, 0x11, 0x55a0); |
| 826 | __phy_write(phydev, 0x12, 0x0); |
| 827 | __phy_write(phydev, 0x10, 0x83aa); |
| 828 | |
developer | 7d14140 | 2023-04-06 20:10:38 +0800 | [diff] [blame] | 829 | /* TrFreeze = 0 */ |
| 830 | __phy_write(phydev, 0x11, 0x0); |
| 831 | __phy_write(phydev, 0x12, 0x0); |
| 832 | __phy_write(phydev, 0x10, 0x9686); |
| 833 | |
developer | dd59856 | 2023-03-28 23:57:03 +0800 | [diff] [blame] | 834 | /* SSTrKp1000Slv = 5 */ |
| 835 | __phy_write(phydev, 0x11, 0xbaef); |
| 836 | __phy_write(phydev, 0x12, 0x2e); |
| 837 | __phy_write(phydev, 0x10, 0x968c); |
| 838 | |
| 839 | /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2, |
| 840 | * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2 |
| 841 | */ |
| 842 | __phy_write(phydev, 0x11, 0xd10a); |
| 843 | __phy_write(phydev, 0x12, 0x34); |
| 844 | __phy_write(phydev, 0x10, 0x8f82); |
| 845 | |
| 846 | /* VcoSlicerThreshBitsHigh */ |
| 847 | __phy_write(phydev, 0x11, 0x5555); |
| 848 | __phy_write(phydev, 0x12, 0x55); |
| 849 | __phy_write(phydev, 0x10, 0x8ec0); |
| 850 | phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); |
| 851 | |
developer | 50fe2af | 2023-03-31 18:32:24 +0800 | [diff] [blame] | 852 | /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9*/ |
| 853 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234, |
| 854 | MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK, |
| 855 | BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9)); |
| 856 | |
developer | dd59856 | 2023-03-28 23:57:03 +0800 | [diff] [blame] | 857 | /* rg_tr_lpf_cnt_val = 512 */ |
| 858 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200); |
| 859 | |
| 860 | /* IIR2 related */ |
| 861 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82); |
| 862 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0); |
| 863 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103); |
| 864 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0); |
| 865 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82); |
| 866 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0); |
| 867 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177); |
| 868 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3); |
| 869 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82); |
| 870 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe); |
| 871 | |
| 872 | /* FFE peaking */ |
| 873 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C, |
| 874 | MTK_PHY_VGASTATE_FFE_THR_ST1_MASK, 0x1b << 8); |
| 875 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D, |
| 876 | MTK_PHY_VGASTATE_FFE_THR_ST2_MASK, 0x1e); |
| 877 | |
developer | dd59856 | 2023-03-28 23:57:03 +0800 | [diff] [blame] | 878 | /* Disable LDO pump */ |
| 879 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, 0x0); |
| 880 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, 0x0); |
| 881 | /* Adjust LDO output voltage */ |
| 882 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222); |
| 883 | } |
| 884 | |
| 885 | static inline void mt7981_phy_finetune(struct phy_device *phydev) |
| 886 | { |
developer | 02d8442 | 2021-12-24 11:48:07 +0800 | [diff] [blame] | 887 | /* 100M eye finetune: |
| 888 | * Keep middle level of TX MLT3 shapper as default. |
| 889 | * Only change TX MLT3 overshoot level here. |
| 890 | */ |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 891 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_1st_OVERSHOOT_LEVEL_0TO1, |
| 892 | 0x1ce); |
| 893 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_2nd_OVERSHOOT_LEVEL_0TO1, |
| 894 | 0x1c1); |
| 895 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_1st_OVERSHOOT_LEVEL_1TO0, |
| 896 | 0x20f); |
| 897 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_2nd_OVERSHOOT_LEVEL_1TO0, |
| 898 | 0x202); |
| 899 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_1st_OVERSHOOT_LEVEL_0TON1, |
| 900 | 0x3d0); |
| 901 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_2nd_OVERSHOOT_LEVEL_0TON1, |
| 902 | 0x3c0); |
| 903 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_1st_OVERSHOOT_LEVEL_N1TO0, |
| 904 | 0x13); |
| 905 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_2nd_OVERSHOOT_LEVEL_N1TO0, |
| 906 | 0x5); |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 907 | |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 908 | phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); |
developer | 7fbc526 | 2023-03-28 23:44:26 +0800 | [diff] [blame] | 909 | /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */ |
| 910 | __phy_write(phydev, 0x11, 0xc71); |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 911 | __phy_write(phydev, 0x12, 0xc); |
| 912 | __phy_write(phydev, 0x10, 0x8fae); |
| 913 | |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 914 | /* ResetSyncOffset = 6 */ |
| 915 | __phy_write(phydev, 0x11, 0x600); |
| 916 | __phy_write(phydev, 0x12, 0x0); |
| 917 | __phy_write(phydev, 0x10, 0x8fc0); |
| 918 | |
| 919 | /* VgaDecRate = 1 */ |
| 920 | __phy_write(phydev, 0x11, 0x4c2a); |
| 921 | __phy_write(phydev, 0x12, 0x3e); |
| 922 | __phy_write(phydev, 0x10, 0x8fa4); |
| 923 | |
developer | 7fbc526 | 2023-03-28 23:44:26 +0800 | [diff] [blame] | 924 | /* FfeUpdGainForce = 4 */ |
| 925 | __phy_write(phydev, 0x11, 0x240); |
| 926 | __phy_write(phydev, 0x12, 0x0); |
| 927 | __phy_write(phydev, 0x10, 0x9680); |
| 928 | |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 929 | phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); |
developer | 02d8442 | 2021-12-24 11:48:07 +0800 | [diff] [blame] | 930 | } |
| 931 | |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 932 | static inline void mt7988_phy_finetune(struct phy_device *phydev) |
| 933 | { |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 934 | u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182, |
| 935 | 0x020d, 0x0206, 0x0384, 0x03d0, |
| 936 | 0x03c6, 0x030a, 0x0011, 0x0005 }; |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 937 | int i; |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 938 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 939 | for (i = 0; i < MTK_PHY_TX_MLT3_END; i++) |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 940 | phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[i]); |
developer | 6de96aa | 2022-09-29 16:46:18 +0800 | [diff] [blame] | 941 | |
developer | 5737403 | 2022-10-11 16:43:24 +0800 | [diff] [blame] | 942 | /* TCT finetune */ |
developer | 6de96aa | 2022-09-29 16:46:18 +0800 | [diff] [blame] | 943 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5); |
developer | 5737403 | 2022-10-11 16:43:24 +0800 | [diff] [blame] | 944 | |
| 945 | /* Disable TX power saving */ |
| 946 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 947 | MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8); |
developer | ec2b855 | 2022-10-17 15:30:59 +0800 | [diff] [blame] | 948 | |
developer | ec2b855 | 2022-10-17 15:30:59 +0800 | [diff] [blame] | 949 | phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); |
developer | ce73ad6 | 2022-12-07 22:43:45 +0800 | [diff] [blame] | 950 | |
developer | 7fbc526 | 2023-03-28 23:44:26 +0800 | [diff] [blame] | 951 | /* SlvDSPreadyTime = 24, MasDSPreadyTime = 12 */ |
developer | ce73ad6 | 2022-12-07 22:43:45 +0800 | [diff] [blame] | 952 | __phy_write(phydev, 0x11, 0x671); |
| 953 | __phy_write(phydev, 0x12, 0xc); |
| 954 | __phy_write(phydev, 0x10, 0x8fae); |
| 955 | |
developer | ce26831 | 2022-12-20 16:26:11 +0800 | [diff] [blame] | 956 | /* ResetSyncOffset = 5 */ |
| 957 | __phy_write(phydev, 0x11, 0x500); |
developer | ce73ad6 | 2022-12-07 22:43:45 +0800 | [diff] [blame] | 958 | __phy_write(phydev, 0x12, 0x0); |
| 959 | __phy_write(phydev, 0x10, 0x8fc0); |
developer | 50fe2af | 2023-03-31 18:32:24 +0800 | [diff] [blame] | 960 | |
| 961 | /* VgaDecRate is 1 at default on mt7988 */ |
| 962 | |
developer | b5c72b0 | 2022-12-21 15:51:07 +0800 | [diff] [blame] | 963 | phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); |
developer | ce73ad6 | 2022-12-07 22:43:45 +0800 | [diff] [blame] | 964 | |
developer | ce26831 | 2022-12-20 16:26:11 +0800 | [diff] [blame] | 965 | phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_2A30); |
| 966 | /* TxClkOffset = 2 */ |
developer | b5c72b0 | 2022-12-21 15:51:07 +0800 | [diff] [blame] | 967 | __phy_modify(phydev, MTK_PHY_ANARG_RG, MTK_PHY_TCLKOFFSET_MASK, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 968 | FIELD_PREP(MTK_PHY_TCLKOFFSET_MASK, 0x2)); |
developer | ec2b855 | 2022-10-17 15:30:59 +0800 | [diff] [blame] | 969 | phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 970 | } |
developer | 7581999 | 2023-03-08 20:49:03 +0800 | [diff] [blame] | 971 | |
developer | 7fbc526 | 2023-03-28 23:44:26 +0800 | [diff] [blame] | 972 | static inline void mt798x_phy_eee(struct phy_device *phydev) |
| 973 | { |
| 974 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, |
developer | 7fa3769 | 2023-03-29 17:05:33 +0800 | [diff] [blame] | 975 | MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120, |
| 976 | MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK | |
| 977 | MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, |
| 978 | FIELD_PREP(MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK, 0x0) | |
| 979 | FIELD_PREP(MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, 0x14)); |
developer | 7fbc526 | 2023-03-28 23:44:26 +0800 | [diff] [blame] | 980 | |
| 981 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, |
developer | 7fa3769 | 2023-03-29 17:05:33 +0800 | [diff] [blame] | 982 | MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122, |
| 983 | MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, |
| 984 | FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, |
| 985 | 0xff)); |
developer | 7fbc526 | 2023-03-28 23:44:26 +0800 | [diff] [blame] | 986 | |
| 987 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, |
developer | 7fa3769 | 2023-03-29 17:05:33 +0800 | [diff] [blame] | 988 | MTK_PHY_RG_TESTMUX_ADC_CTRL, |
| 989 | MTK_PHY_RG_TXEN_DIG_MASK); |
developer | 7fbc526 | 2023-03-28 23:44:26 +0800 | [diff] [blame] | 990 | |
| 991 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, |
developer | 7fa3769 | 2023-03-29 17:05:33 +0800 | [diff] [blame] | 992 | MTK_PHY_RG_DEV1E_REG19b, MTK_PHY_BYPASS_DSP_LPI_READY); |
developer | 7fbc526 | 2023-03-28 23:44:26 +0800 | [diff] [blame] | 993 | |
| 994 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, |
developer | 7fa3769 | 2023-03-29 17:05:33 +0800 | [diff] [blame] | 995 | MTK_PHY_RG_DEV1E_REG234, MTK_PHY_TR_LP_IIR_EEE_EN); |
developer | 7fbc526 | 2023-03-28 23:44:26 +0800 | [diff] [blame] | 996 | |
| 997 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG238, |
developer | 7fa3769 | 2023-03-29 17:05:33 +0800 | [diff] [blame] | 998 | MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK | |
| 999 | MTK_PHY_LPI_SLV_SEND_TX_EN, |
| 1000 | FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120)); |
developer | 7fbc526 | 2023-03-28 23:44:26 +0800 | [diff] [blame] | 1001 | |
| 1002 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239, |
developer | 7fa3769 | 2023-03-29 17:05:33 +0800 | [diff] [blame] | 1003 | MTK_PHY_LPI_SEND_LOC_TIMER_MASK | |
| 1004 | MTK_PHY_LPI_TXPCS_LOC_RCV, |
| 1005 | FIELD_PREP(MTK_PHY_LPI_SEND_LOC_TIMER_MASK, 0x117)); |
developer | 7fbc526 | 2023-03-28 23:44:26 +0800 | [diff] [blame] | 1006 | |
| 1007 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7, |
developer | 7fa3769 | 2023-03-29 17:05:33 +0800 | [diff] [blame] | 1008 | MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK, |
| 1009 | FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) | |
| 1010 | FIELD_PREP(MTK_PHY_MIN_GAIN_MASK, 0x13)); |
developer | 7fbc526 | 2023-03-28 23:44:26 +0800 | [diff] [blame] | 1011 | |
| 1012 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2D1, |
developer | 7fa3769 | 2023-03-29 17:05:33 +0800 | [diff] [blame] | 1013 | MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK, |
| 1014 | FIELD_PREP(MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK, |
| 1015 | 0x33) | |
| 1016 | MTK_PHY_LPI_SKIP_SD_SLV_TR | MTK_PHY_LPI_TR_READY | |
| 1017 | MTK_PHY_LPI_VCO_EEE_STG0_EN); |
developer | 7fbc526 | 2023-03-28 23:44:26 +0800 | [diff] [blame] | 1018 | |
| 1019 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG323, |
developer | 7fa3769 | 2023-03-29 17:05:33 +0800 | [diff] [blame] | 1020 | MTK_PHY_EEE_WAKE_MAS_INT_DC | |
| 1021 | MTK_PHY_EEE_WAKE_SLV_INT_DC); |
developer | 7fbc526 | 2023-03-28 23:44:26 +0800 | [diff] [blame] | 1022 | |
| 1023 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG324, |
developer | 7fa3769 | 2023-03-29 17:05:33 +0800 | [diff] [blame] | 1024 | MTK_PHY_SMI_DETCNT_MAX_MASK, |
| 1025 | FIELD_PREP(MTK_PHY_SMI_DETCNT_MAX_MASK, 0x3f) | |
| 1026 | MTK_PHY_SMI_DET_MAX_EN); |
developer | 7fbc526 | 2023-03-28 23:44:26 +0800 | [diff] [blame] | 1027 | |
| 1028 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG326, |
developer | 7fa3769 | 2023-03-29 17:05:33 +0800 | [diff] [blame] | 1029 | MTK_PHY_LPI_MODE_SD_ON | MTK_PHY_RESET_RANDUPD_CNT | |
| 1030 | MTK_PHY_TREC_UPDATE_ENAB_CLR | |
| 1031 | MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF | |
| 1032 | MTK_PHY_TR_READY_SKIP_AFE_WAKEUP); |
developer | 7fbc526 | 2023-03-28 23:44:26 +0800 | [diff] [blame] | 1033 | |
| 1034 | phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); |
| 1035 | /* Regsigdet_sel_1000 = 0 */ |
| 1036 | __phy_write(phydev, 0x11, 0xb); |
| 1037 | __phy_write(phydev, 0x12, 0x0); |
| 1038 | __phy_write(phydev, 0x10, 0x9690); |
| 1039 | |
| 1040 | /* REG_EEE_st2TrKf1000 = 3 */ |
| 1041 | __phy_write(phydev, 0x11, 0x114f); |
| 1042 | __phy_write(phydev, 0x12, 0x2); |
| 1043 | __phy_write(phydev, 0x10, 0x969a); |
| 1044 | |
| 1045 | /* RegEEE_slv_wake_tr_timer_tar = 6, RegEEE_slv_remtx_timer_tar = 20 */ |
| 1046 | __phy_write(phydev, 0x11, 0x3028); |
| 1047 | __phy_write(phydev, 0x12, 0x0); |
| 1048 | __phy_write(phydev, 0x10, 0x969e); |
| 1049 | |
| 1050 | /* RegEEE_slv_wake_int_timer_tar = 8 */ |
| 1051 | __phy_write(phydev, 0x11, 0x5010); |
| 1052 | __phy_write(phydev, 0x12, 0x0); |
| 1053 | __phy_write(phydev, 0x10, 0x96a0); |
| 1054 | |
| 1055 | /* RegEEE_trfreeze_timer2 = 586 */ |
| 1056 | __phy_write(phydev, 0x11, 0x24a); |
| 1057 | __phy_write(phydev, 0x12, 0x0); |
| 1058 | __phy_write(phydev, 0x10, 0x96a8); |
| 1059 | |
| 1060 | /* RegEEE100Stg1_tar = 16 */ |
| 1061 | __phy_write(phydev, 0x11, 0x3210); |
| 1062 | __phy_write(phydev, 0x12, 0x0); |
| 1063 | __phy_write(phydev, 0x10, 0x96b8); |
| 1064 | |
| 1065 | /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 1 */ |
| 1066 | __phy_write(phydev, 0x11, 0x1463); |
| 1067 | __phy_write(phydev, 0x12, 0x0); |
| 1068 | __phy_write(phydev, 0x10, 0x96ca); |
| 1069 | |
| 1070 | /* DfeTailEnableVgaThresh1000 = 27 */ |
developer | 7d14140 | 2023-04-06 20:10:38 +0800 | [diff] [blame] | 1071 | __phy_write(phydev, 0x11, 0x36); |
developer | 7fbc526 | 2023-03-28 23:44:26 +0800 | [diff] [blame] | 1072 | __phy_write(phydev, 0x12, 0x0); |
| 1073 | __phy_write(phydev, 0x10, 0x8f80); |
| 1074 | phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); |
| 1075 | |
| 1076 | phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3); |
| 1077 | __phy_modify(phydev, MTK_PHY_LPI_REG_14, MTK_PHY_LPI_WAKE_TIMER_1000_MASK, |
developer | 7fa3769 | 2023-03-29 17:05:33 +0800 | [diff] [blame] | 1078 | FIELD_PREP(MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 0x19c)); |
developer | 7fbc526 | 2023-03-28 23:44:26 +0800 | [diff] [blame] | 1079 | |
| 1080 | __phy_modify(phydev, MTK_PHY_LPI_REG_1c, MTK_PHY_SMI_DET_ON_THRESH_MASK, |
developer | 7fa3769 | 2023-03-29 17:05:33 +0800 | [diff] [blame] | 1081 | FIELD_PREP(MTK_PHY_SMI_DET_ON_THRESH_MASK, 0xc)); |
developer | 7fbc526 | 2023-03-28 23:44:26 +0800 | [diff] [blame] | 1082 | phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); |
| 1083 | |
| 1084 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, |
developer | 7fa3769 | 2023-03-29 17:05:33 +0800 | [diff] [blame] | 1085 | MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122, |
| 1086 | MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, |
| 1087 | FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 0xff)); |
developer | 7fbc526 | 2023-03-28 23:44:26 +0800 | [diff] [blame] | 1088 | } |
| 1089 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 1090 | static inline int cal_sw(struct phy_device *phydev, enum CAL_ITEM cal_item, |
| 1091 | u8 start_pair, u8 end_pair) |
| 1092 | { |
| 1093 | u8 pair_n; |
| 1094 | int ret; |
| 1095 | |
| 1096 | for (pair_n = start_pair; pair_n <= end_pair; pair_n++) { |
| 1097 | /* TX_OFFSET & TX_AMP have no SW calibration. */ |
| 1098 | switch (cal_item) { |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 1099 | case TX_VCM: |
| 1100 | ret = tx_vcm_cal_sw(phydev, pair_n); |
| 1101 | break; |
| 1102 | default: |
| 1103 | return -EINVAL; |
| 1104 | } |
| 1105 | if (ret) |
| 1106 | return ret; |
| 1107 | } |
| 1108 | return 0; |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 1109 | } |
| 1110 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 1111 | static inline int cal_efuse(struct phy_device *phydev, enum CAL_ITEM cal_item, |
| 1112 | u8 start_pair, u8 end_pair, u32 *buf) |
| 1113 | { |
| 1114 | u8 pair_n; |
| 1115 | int ret; |
| 1116 | |
| 1117 | for (pair_n = start_pair; pair_n <= end_pair; pair_n++) { |
| 1118 | /* TX_VCM has no efuse calibration. */ |
| 1119 | switch (cal_item) { |
| 1120 | case REXT: |
| 1121 | ret = rext_cal_efuse(phydev, buf); |
| 1122 | break; |
| 1123 | case TX_OFFSET: |
| 1124 | ret = tx_offset_cal_efuse(phydev, buf); |
| 1125 | break; |
| 1126 | case TX_AMP: |
| 1127 | ret = tx_amp_cal_efuse(phydev, buf); |
| 1128 | break; |
| 1129 | case TX_R50: |
| 1130 | ret = tx_r50_cal_efuse(phydev, buf, pair_n); |
| 1131 | break; |
| 1132 | default: |
| 1133 | return -EINVAL; |
| 1134 | } |
| 1135 | if (ret) |
| 1136 | return ret; |
| 1137 | } |
| 1138 | |
| 1139 | return 0; |
| 1140 | } |
| 1141 | |
| 1142 | static int start_cal(struct phy_device *phydev, enum CAL_ITEM cal_item, |
developer | c7b857b | 2023-03-28 22:37:02 +0800 | [diff] [blame] | 1143 | enum CAL_MODE cal_mode, u8 start_pair, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 1144 | u8 end_pair, u32 *buf) |
| 1145 | { |
developer | c7b857b | 2023-03-28 22:37:02 +0800 | [diff] [blame] | 1146 | int ret; |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 1147 | char cal_prop[5][20] = { "mediatek,rext", "mediatek,tx_offset", |
| 1148 | "mediatek,tx_amp", "mediatek,tx_r50", |
| 1149 | "mediatek,tx_vcm" }; |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 1150 | |
| 1151 | switch (cal_mode) { |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 1152 | case EFUSE_M: |
developer | c7b857b | 2023-03-28 22:37:02 +0800 | [diff] [blame] | 1153 | ret = cal_efuse(phydev, cal_item, start_pair, |
developer | 7fa3769 | 2023-03-29 17:05:33 +0800 | [diff] [blame] | 1154 | end_pair, buf); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 1155 | break; |
| 1156 | case SW_M: |
developer | c7b857b | 2023-03-28 22:37:02 +0800 | [diff] [blame] | 1157 | ret = cal_sw(phydev, cal_item, start_pair, end_pair); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 1158 | break; |
| 1159 | default: |
| 1160 | return -EINVAL; |
| 1161 | } |
| 1162 | |
developer | c7b857b | 2023-03-28 22:37:02 +0800 | [diff] [blame] | 1163 | if (ret) { |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 1164 | dev_err(&phydev->mdio.dev, "[%s]cal failed\n", cal_prop[cal_item]); |
| 1165 | return -EIO; |
| 1166 | } |
| 1167 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 1168 | return 0; |
| 1169 | } |
| 1170 | |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 1171 | static int mt798x_phy_calibration(struct phy_device *phydev) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 1172 | { |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 1173 | int ret = 0; |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 1174 | u32 *buf; |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 1175 | size_t len; |
| 1176 | struct nvmem_cell *cell; |
| 1177 | |
| 1178 | if (phydev->interface != PHY_INTERFACE_MODE_GMII) |
| 1179 | return -EINVAL; |
| 1180 | |
| 1181 | cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data"); |
| 1182 | if (IS_ERR(cell)) { |
| 1183 | if (PTR_ERR(cell) == -EPROBE_DEFER) |
| 1184 | return PTR_ERR(cell); |
| 1185 | return 0; |
| 1186 | } |
| 1187 | |
| 1188 | buf = (u32 *)nvmem_cell_read(cell, &len); |
| 1189 | if (IS_ERR(buf)) |
| 1190 | return PTR_ERR(buf); |
| 1191 | nvmem_cell_put(cell); |
| 1192 | |
developer | c7b857b | 2023-03-28 22:37:02 +0800 | [diff] [blame] | 1193 | if (!buf[0] || !buf[1] || !buf[2] || !buf[3] || len < 4 * sizeof(u32)) { |
| 1194 | dev_err(&phydev->mdio.dev, "invalid efuse data\n"); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 1195 | ret = -EINVAL; |
| 1196 | goto out; |
| 1197 | } |
| 1198 | |
developer | c7b857b | 2023-03-28 22:37:02 +0800 | [diff] [blame] | 1199 | ret = start_cal(phydev, REXT, EFUSE_M, NO_PAIR, NO_PAIR, buf); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 1200 | if (ret) |
| 1201 | goto out; |
developer | 7fa3769 | 2023-03-29 17:05:33 +0800 | [diff] [blame] | 1202 | ret = start_cal(phydev, TX_OFFSET, EFUSE_M, NO_PAIR, NO_PAIR, buf); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 1203 | if (ret) |
| 1204 | goto out; |
developer | c7b857b | 2023-03-28 22:37:02 +0800 | [diff] [blame] | 1205 | ret = start_cal(phydev, TX_AMP, EFUSE_M, NO_PAIR, NO_PAIR, buf); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 1206 | if (ret) |
| 1207 | goto out; |
developer | c7b857b | 2023-03-28 22:37:02 +0800 | [diff] [blame] | 1208 | ret = start_cal(phydev, TX_R50, EFUSE_M, PAIR_A, PAIR_D, buf); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 1209 | if (ret) |
| 1210 | goto out; |
developer | c7b857b | 2023-03-28 22:37:02 +0800 | [diff] [blame] | 1211 | ret = start_cal(phydev, TX_VCM, SW_M, PAIR_A, PAIR_A, buf); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 1212 | if (ret) |
| 1213 | goto out; |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 1214 | |
| 1215 | out: |
| 1216 | kfree(buf); |
| 1217 | return ret; |
| 1218 | } |
| 1219 | |
developer | 68f6e10 | 2022-11-22 17:35:00 +0800 | [diff] [blame] | 1220 | static int mt7981_phy_probe(struct phy_device *phydev) |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 1221 | { |
developer | dd59856 | 2023-03-28 23:57:03 +0800 | [diff] [blame] | 1222 | mt798x_phy_common_finetune(phydev); |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 1223 | mt7981_phy_finetune(phydev); |
developer | 7fbc526 | 2023-03-28 23:44:26 +0800 | [diff] [blame] | 1224 | mt798x_phy_eee(phydev); |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 1225 | |
| 1226 | return mt798x_phy_calibration(phydev); |
| 1227 | } |
| 1228 | |
developer | 68f6e10 | 2022-11-22 17:35:00 +0800 | [diff] [blame] | 1229 | static int mt7988_phy_probe(struct phy_device *phydev) |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 1230 | { |
developer | 941468f | 2023-04-10 15:21:02 +0800 | [diff] [blame] | 1231 | struct device_node *np; |
| 1232 | void __iomem *boottrap; |
| 1233 | u32 reg; |
| 1234 | int port; |
| 1235 | int ret; |
| 1236 | struct pinctrl *pinctrl; |
| 1237 | |
| 1238 | /* Setup LED polarity according to boottrap's polarity */ |
| 1239 | np = of_find_compatible_node(NULL, NULL, "mediatek,boottrap"); |
| 1240 | if (!np) |
| 1241 | return -ENOENT; |
| 1242 | boottrap = of_iomap(np, 0); |
| 1243 | if (!boottrap) |
| 1244 | return -ENOMEM; |
| 1245 | reg = readl(boottrap); |
| 1246 | port = phydev->mdio.addr; |
| 1247 | if ((port == GPHY_PORT0 && reg & BIT(8)) || |
| 1248 | (port == GPHY_PORT1 && reg & BIT(9)) || |
| 1249 | (port == GPHY_PORT2 && reg & BIT(10)) || |
| 1250 | (port == GPHY_PORT3 && reg & BIT(11))) { |
| 1251 | phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, |
| 1252 | MTK_PHY_LED0_ENABLE | MTK_PHY_LED0_ON_LINK10 | |
| 1253 | MTK_PHY_LED0_ON_LINK100 | |
| 1254 | MTK_PHY_LED0_ON_LINK1000); |
| 1255 | } else { |
| 1256 | phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, |
| 1257 | MTK_PHY_LED0_ENABLE | MTK_PHY_LED0_POLARITY | |
| 1258 | MTK_PHY_LED0_ON_LINK10 | |
| 1259 | MTK_PHY_LED0_ON_LINK100 | |
| 1260 | MTK_PHY_LED0_ON_LINK1000); |
| 1261 | } |
| 1262 | phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_BLINK_CTRL, |
| 1263 | MTK_PHY_LED0_1000TX | MTK_PHY_LED0_1000RX | |
| 1264 | MTK_PHY_LED0_100TX | MTK_PHY_LED0_100RX | |
| 1265 | MTK_PHY_LED0_10TX | MTK_PHY_LED0_10RX); |
| 1266 | |
| 1267 | if (port == GPHY_PORT3) { |
| 1268 | pinctrl = devm_pinctrl_get_select_default(&phydev->mdio.bus->dev); |
| 1269 | if (IS_ERR(pinctrl)) { |
| 1270 | ret = PTR_ERR(pinctrl); |
| 1271 | dev_err(&phydev->mdio.dev, "Fail to set LED pins!\n"); |
| 1272 | return -EINVAL; |
| 1273 | } |
| 1274 | } |
| 1275 | |
developer | dd59856 | 2023-03-28 23:57:03 +0800 | [diff] [blame] | 1276 | mt798x_phy_common_finetune(phydev); |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 1277 | mt7988_phy_finetune(phydev); |
developer | 7fbc526 | 2023-03-28 23:44:26 +0800 | [diff] [blame] | 1278 | mt798x_phy_eee(phydev); |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 1279 | |
| 1280 | return mt798x_phy_calibration(phydev); |
| 1281 | } |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 1282 | #endif |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 1283 | |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 1284 | static struct phy_driver mtk_gephy_driver[] = { |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 1285 | { |
developer | 043f7b9 | 2023-03-13 13:57:36 +0800 | [diff] [blame] | 1286 | PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7530), |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 1287 | .name = "MediaTek MT7530 PHY", |
| 1288 | .config_init = mt7530_phy_config_init, |
| 1289 | /* Interrupts are handled by the switch, not the PHY |
| 1290 | * itself. |
| 1291 | */ |
| 1292 | .config_intr = genphy_no_config_intr, |
| 1293 | .handle_interrupt = genphy_no_ack_interrupt, |
| 1294 | .suspend = genphy_suspend, |
| 1295 | .resume = genphy_resume, |
| 1296 | .read_page = mtk_gephy_read_page, |
| 1297 | .write_page = mtk_gephy_write_page, |
| 1298 | }, |
| 1299 | { |
developer | 043f7b9 | 2023-03-13 13:57:36 +0800 | [diff] [blame] | 1300 | PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7531), |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 1301 | .name = "MediaTek MT7531 PHY", |
| 1302 | .config_init = mt7531_phy_config_init, |
| 1303 | /* Interrupts are handled by the switch, not the PHY |
| 1304 | * itself. |
| 1305 | */ |
| 1306 | .config_intr = genphy_no_config_intr, |
| 1307 | .handle_interrupt = genphy_no_ack_interrupt, |
| 1308 | .suspend = genphy_suspend, |
| 1309 | .resume = genphy_resume, |
| 1310 | .read_page = mtk_gephy_read_page, |
| 1311 | .write_page = mtk_gephy_write_page, |
| 1312 | }, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 1313 | #ifdef CONFIG_MEDIATEK_GE_PHY_SOC |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 1314 | { |
developer | 043f7b9 | 2023-03-13 13:57:36 +0800 | [diff] [blame] | 1315 | PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981), |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 1316 | .name = "MediaTek MT7981 PHY", |
developer | 68f6e10 | 2022-11-22 17:35:00 +0800 | [diff] [blame] | 1317 | .probe = mt7981_phy_probe, |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 1318 | .config_intr = genphy_no_config_intr, |
| 1319 | .handle_interrupt = genphy_no_ack_interrupt, |
| 1320 | .suspend = genphy_suspend, |
| 1321 | .resume = genphy_resume, |
| 1322 | .read_page = mtk_gephy_read_page, |
| 1323 | .write_page = mtk_gephy_write_page, |
| 1324 | }, |
| 1325 | { |
developer | 043f7b9 | 2023-03-13 13:57:36 +0800 | [diff] [blame] | 1326 | PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988), |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 1327 | .name = "MediaTek MT7988 PHY", |
| 1328 | .probe = mt7988_phy_probe, |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 1329 | .config_intr = genphy_no_config_intr, |
| 1330 | .handle_interrupt = genphy_no_ack_interrupt, |
| 1331 | .suspend = genphy_suspend, |
| 1332 | .resume = genphy_resume, |
| 1333 | .read_page = mtk_gephy_read_page, |
| 1334 | .write_page = mtk_gephy_write_page, |
| 1335 | }, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 1336 | #endif |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 1337 | }; |
| 1338 | |
| 1339 | module_phy_driver(mtk_gephy_driver); |
| 1340 | |
| 1341 | static struct mdio_device_id __maybe_unused mtk_gephy_tbl[] = { |
| 1342 | { PHY_ID_MATCH_VENDOR(0x03a29400) }, |
| 1343 | { } |
| 1344 | }; |
| 1345 | |
| 1346 | MODULE_DESCRIPTION("MediaTek Gigabit Ethernet PHY driver"); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame] | 1347 | MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>"); |
| 1348 | MODULE_AUTHOR("SkyLake Huang <SkyLake.Huang@mediatek.com>"); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 1349 | MODULE_AUTHOR("DENG, Qingfang <dqfext@gmail.com>"); |
| 1350 | MODULE_LICENSE("GPL"); |
| 1351 | |
| 1352 | MODULE_DEVICE_TABLE(mdio, mtk_gephy_tbl); |