[][kernel][mt7988][eth][Add tx filter finetune for switch gphy]
[Description]
Add tx filter finetune for switch gphy
[Release-log]
N/A
Change-Id: Ifbc20ca17c8d57d5687a945cf3a39a80e77e8751
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/6580413
Build: srv_hbgsm110
diff --git a/target/linux/mediatek/files-5.4/drivers/net/phy/mediatek-ge.c b/target/linux/mediatek/files-5.4/drivers/net/phy/mediatek-ge.c
index 0dc5129..062abae 100644
--- a/target/linux/mediatek/files-5.4/drivers/net/phy/mediatek-ge.c
+++ b/target/linux/mediatek/files-5.4/drivers/net/phy/mediatek-ge.c
@@ -105,6 +105,8 @@
#define MTK_PHY_RG_REXT_TRIM_MASK GENMASK(13, 8)
#define MTK_PHY_RG_ZCAL_CTRL_MASK GENMASK(5, 0)
+#define MTK_PHY_RG_TX_FILTER (0xfe)
+
#define MTK_PHY_RG_DEV1E_REG172 (0x172)
#define MTK_PHY_CR_TX_AMP_OFFSET_A_MASK GENMASK(13, 8)
#define MTK_PHY_CR_TX_AMP_OFFSET_B_MASK GENMASK(6, 0)
@@ -882,6 +884,8 @@
for(i=0; i<MTK_PHY_TX_MLT3_END; i++) {
phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[i]);
}
+
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5);
}
static int mt798x_phy_calibration(struct phy_device *phydev)