developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | #include <linux/bitfield.h> |
| 3 | #include <linux/module.h> |
| 4 | #include <linux/nvmem-consumer.h> |
developer | 2302129 | 2022-10-21 19:10:10 +0800 | [diff] [blame] | 5 | #include <linux/of_address.h> |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 6 | #include <linux/of_platform.h> |
| 7 | #include <linux/phy.h> |
| 8 | |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 9 | #define MTK_EXT_PAGE_ACCESS 0x1f |
| 10 | #define MTK_PHY_PAGE_STANDARD 0x0000 |
| 11 | #define MTK_PHY_PAGE_EXTENDED 0x0001 |
| 12 | #define MTK_PHY_PAGE_EXTENDED_2 0x0002 |
| 13 | #define MTK_PHY_PAGE_EXTENDED_3 0x0003 |
| 14 | #define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30 |
| 15 | #define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5 |
| 16 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 17 | #define ANALOG_INTERNAL_OPERATION_MAX_US (20) |
| 18 | #define ZCAL_CTRL_MIN (0) |
| 19 | #define ZCAL_CTRL_MAX (63) |
| 20 | #define TXRESERVE_MIN (0) |
| 21 | #define TXRESERVE_MAX (7) |
| 22 | |
| 23 | #define MTK_PHY_ANARG_RG (0x10) |
| 24 | #define MTK_PHY_TCLKOFFSET_MASK GENMASK(12, 8) |
| 25 | |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 26 | /* Registers on MDIO_MMD_VEND1 */ |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 27 | enum { |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 28 | MTK_PHY_MIDDLE_LEVEL_SHAPPER_0TO1 = 0, |
| 29 | MTK_PHY_1st_OVERSHOOT_LEVEL_0TO1, |
| 30 | MTK_PHY_2nd_OVERSHOOT_LEVEL_0TO1, |
| 31 | MTK_PHY_MIDDLE_LEVEL_SHAPPER_1TO0, |
| 32 | MTK_PHY_1st_OVERSHOOT_LEVEL_1TO0, |
| 33 | MTK_PHY_2nd_OVERSHOOT_LEVEL_1TO0, |
| 34 | MTK_PHY_MIDDLE_LEVEL_SHAPPER_0TON1, /* N means negative */ |
| 35 | MTK_PHY_1st_OVERSHOOT_LEVEL_0TON1, |
| 36 | MTK_PHY_2nd_OVERSHOOT_LEVEL_0TON1, |
| 37 | MTK_PHY_MIDDLE_LEVEL_SHAPPER_N1TO0, |
| 38 | MTK_PHY_1st_OVERSHOOT_LEVEL_N1TO0, |
| 39 | MTK_PHY_2nd_OVERSHOOT_LEVEL_N1TO0, |
| 40 | MTK_PHY_TX_MLT3_END, |
| 41 | }; |
developer | 02d8442 | 2021-12-24 11:48:07 +0800 | [diff] [blame] | 42 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 43 | #define MTK_PHY_TXVLD_DA_RG (0x12) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 44 | #define MTK_PHY_DA_TX_I2MPB_A_GBE_MASK GENMASK(15, 10) |
| 45 | #define MTK_PHY_DA_TX_I2MPB_A_TBT_MASK GENMASK(5, 0) |
| 46 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 47 | #define MTK_PHY_TX_I2MPB_TEST_MODE_A2 (0x16) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 48 | #define MTK_PHY_DA_TX_I2MPB_A_HBT_MASK GENMASK(15, 10) |
| 49 | #define MTK_PHY_DA_TX_I2MPB_A_TST_MASK GENMASK(5, 0) |
| 50 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 51 | #define MTK_PHY_TX_I2MPB_TEST_MODE_B1 (0x17) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 52 | #define MTK_PHY_DA_TX_I2MPB_B_GBE_MASK GENMASK(13, 8) |
| 53 | #define MTK_PHY_DA_TX_I2MPB_B_TBT_MASK GENMASK(5, 0) |
| 54 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 55 | #define MTK_PHY_TX_I2MPB_TEST_MODE_B2 (0x18) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 56 | #define MTK_PHY_DA_TX_I2MPB_B_HBT_MASK GENMASK(13, 8) |
| 57 | #define MTK_PHY_DA_TX_I2MPB_B_TST_MASK GENMASK(5, 0) |
| 58 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 59 | #define MTK_PHY_TX_I2MPB_TEST_MODE_C1 (0x19) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 60 | #define MTK_PHY_DA_TX_I2MPB_C_GBE_MASK GENMASK(13, 8) |
| 61 | #define MTK_PHY_DA_TX_I2MPB_C_TBT_MASK GENMASK(5, 0) |
| 62 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 63 | #define MTK_PHY_TX_I2MPB_TEST_MODE_C2 (0x20) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 64 | #define MTK_PHY_DA_TX_I2MPB_C_HBT_MASK GENMASK(13, 8) |
| 65 | #define MTK_PHY_DA_TX_I2MPB_C_TST_MASK GENMASK(5, 0) |
| 66 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 67 | #define MTK_PHY_TX_I2MPB_TEST_MODE_D1 (0x21) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 68 | #define MTK_PHY_DA_TX_I2MPB_D_GBE_MASK GENMASK(13, 8) |
| 69 | #define MTK_PHY_DA_TX_I2MPB_D_TBT_MASK GENMASK(5, 0) |
| 70 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 71 | #define MTK_PHY_TX_I2MPB_TEST_MODE_D2 (0x22) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 72 | #define MTK_PHY_DA_TX_I2MPB_D_HBT_MASK GENMASK(13, 8) |
| 73 | #define MTK_PHY_DA_TX_I2MPB_D_TST_MASK GENMASK(5, 0) |
| 74 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 75 | #define MTK_PHY_TANA_CAL_MODE (0xc1) |
| 76 | #define MTK_PHY_TANA_CAL_MODE_SHIFT (8) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 77 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 78 | #define MTK_PHY_RXADC_CTRL_RG7 (0xc6) |
developer | 5737403 | 2022-10-11 16:43:24 +0800 | [diff] [blame] | 79 | #define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8) |
| 80 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 81 | #define MTK_PHY_RXADC_CTRL_RG9 (0xc8) |
| 82 | #define MTK_PHY_DA_RX_PSBN_TBT_MASK GENMASK(14, 12) |
| 83 | #define MTK_PHY_DA_RX_PSBN_HBT_MASK GENMASK(10, 8) |
| 84 | #define MTK_PHY_DA_RX_PSBN_GBE_MASK GENMASK(6, 4) |
| 85 | #define MTK_PHY_DA_RX_PSBN_LP_MASK GENMASK(2, 0) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 86 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 87 | #define MTK_PHY_LDO_OUTPUT_V (0xd7) |
developer | ce26831 | 2022-12-20 16:26:11 +0800 | [diff] [blame] | 88 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 89 | #define MTK_PHY_RG_ANA_CAL_RG0 (0xdb) |
| 90 | #define MTK_PHY_RG_CAL_CKINV BIT(12) |
| 91 | #define MTK_PHY_RG_ANA_CALEN BIT(8) |
| 92 | #define MTK_PHY_RG_REXT_CALEN BIT(4) |
| 93 | #define MTK_PHY_RG_ZCALEN_A BIT(0) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 94 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 95 | #define MTK_PHY_RG_ANA_CAL_RG1 (0xdc) |
| 96 | #define MTK_PHY_RG_ZCALEN_B BIT(12) |
| 97 | #define MTK_PHY_RG_ZCALEN_C BIT(8) |
| 98 | #define MTK_PHY_RG_ZCALEN_D BIT(4) |
| 99 | #define MTK_PHY_RG_TXVOS_CALEN BIT(0) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 100 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 101 | #define MTK_PHY_RG_ANA_CAL_RG2 (0xdd) |
| 102 | #define MTK_PHY_RG_TXG_CALEN_A BIT(12) |
| 103 | #define MTK_PHY_RG_TXG_CALEN_B BIT(8) |
| 104 | #define MTK_PHY_RG_TXG_CALEN_C BIT(4) |
| 105 | #define MTK_PHY_RG_TXG_CALEN_D BIT(0) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 106 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 107 | #define MTK_PHY_RG_ANA_CAL_RG5 (0xe0) |
| 108 | #define MTK_PHY_RG_REXT_TRIM_MASK GENMASK(13, 8) |
| 109 | #define MTK_PHY_RG_ZCAL_CTRL_MASK GENMASK(5, 0) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 110 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 111 | #define MTK_PHY_RG_TX_FILTER (0xfe) |
developer | 6de96aa | 2022-09-29 16:46:18 +0800 | [diff] [blame] | 112 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 113 | #define MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B (0x172) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 114 | #define MTK_PHY_CR_TX_AMP_OFFSET_A_MASK GENMASK(13, 8) |
| 115 | #define MTK_PHY_CR_TX_AMP_OFFSET_B_MASK GENMASK(6, 0) |
| 116 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 117 | #define MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D (0x173) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 118 | #define MTK_PHY_CR_TX_AMP_OFFSET_C_MASK GENMASK(13, 8) |
| 119 | #define MTK_PHY_CR_TX_AMP_OFFSET_D_MASK GENMASK(6, 0) |
| 120 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 121 | #define MTK_PHY_RG_AD_CAL_COMP (0x17a) |
| 122 | #define MTK_PHY_AD_CAL_COMP_OUT_SHIFT (8) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 123 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 124 | #define MTK_PHY_RG_AD_CAL_CLK (0x17b) |
| 125 | #define MTK_PHY_DA_CAL_CLK BIT(0) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 126 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 127 | #define MTK_PHY_RG_AD_CALIN (0x17c) |
| 128 | #define MTK_PHY_DA_CALIN_FLAG BIT(0) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 129 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 130 | #define MTK_PHY_RG_DASN_DAC_IN0_A (0x17d) |
| 131 | #define MTK_PHY_DASN_DAC_IN0_A_MASK GENMASK(9, 0) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 132 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 133 | #define MTK_PHY_RG_DASN_DAC_IN0_B (0x17e) |
| 134 | #define MTK_PHY_DASN_DAC_IN0_B_MASK GENMASK(9, 0) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 135 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 136 | #define MTK_PHY_RG_DASN_DAC_IN0_C (0x17f) |
| 137 | #define MTK_PHY_DASN_DAC_IN0_C_MASK GENMASK(9, 0) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 138 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 139 | #define MTK_PHY_RG_DASN_DAC_IN0_D (0x180) |
| 140 | #define MTK_PHY_DASN_DAC_IN0_D_MASK GENMASK(9, 0) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 141 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 142 | #define MTK_PHY_RG_DASN_DAC_IN1_A (0x181) |
| 143 | #define MTK_PHY_DASN_DAC_IN1_A_MASK GENMASK(9, 0) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 144 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 145 | #define MTK_PHY_RG_DASN_DAC_IN1_B (0x182) |
| 146 | #define MTK_PHY_DASN_DAC_IN1_B_MASK GENMASK(9, 0) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 147 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 148 | #define MTK_PHY_RG_DASN_DAC_IN1_C (0x183) |
| 149 | #define MTK_PHY_DASN_DAC_IN1_C_MASK GENMASK(9, 0) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 150 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 151 | #define MTK_PHY_RG_DASN_DAC_IN1_D (0x180) |
| 152 | #define MTK_PHY_DASN_DAC_IN1_D_MASK GENMASK(9, 0) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 153 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 154 | #define MTK_PHY_RG_LP_IIR2_K1_L (0x22a) |
| 155 | #define MTK_PHY_RG_LP_IIR2_K1_U (0x22b) |
| 156 | #define MTK_PHY_RG_LP_IIR2_K2_L (0x22c) |
| 157 | #define MTK_PHY_RG_LP_IIR2_K2_U (0x22d) |
| 158 | #define MTK_PHY_RG_LP_IIR2_K3_L (0x22e) |
| 159 | #define MTK_PHY_RG_LP_IIR2_K3_U (0x22f) |
| 160 | #define MTK_PHY_RG_LP_IIR2_K4_L (0x230) |
| 161 | #define MTK_PHY_RG_LP_IIR2_K4_U (0x231) |
| 162 | #define MTK_PHY_RG_LP_IIR2_K5_L (0x232) |
| 163 | #define MTK_PHY_RG_LP_IIR2_K5_U (0x233) |
developer | 7581999 | 2023-03-08 20:49:03 +0800 | [diff] [blame] | 164 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 165 | #define MTK_PHY_RG_DEV1E_REG234 (0x234) |
| 166 | #define MTK_PHY_TR_OPEN_LOOP_EN_MASK GENMASK(0, 0) |
| 167 | #define MTK_PHY_LPF_X_AVERAGE_MASK GENMASK(7, 4) |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 168 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 169 | #define MTK_PHY_RG_LPF_CNT_VAL (0x235) |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 170 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 171 | #define MTK_PHY_RG_DEV1E_REG27C (0x27c) |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 172 | #define MTK_PHY_VGASTATE_FFE_THR_ST1_MASK GENMASK(12, 8) |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 173 | #define MTK_PHY_RG_DEV1E_REG27D (0x27d) |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 174 | #define MTK_PHY_VGASTATE_FFE_THR_ST2_MASK GENMASK(4, 0) |
developer | 68f6e10 | 2022-11-22 17:35:00 +0800 | [diff] [blame] | 175 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 176 | #define MTK_PHY_LDO_PUMP_EN_PAIRAB (0x502) |
| 177 | #define MTK_PHY_LDO_PUMP_EN_PAIRCD (0x503) |
developer | 7581999 | 2023-03-08 20:49:03 +0800 | [diff] [blame] | 178 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 179 | #define MTK_PHY_DA_TX_R50_PAIR_A (0x53d) |
| 180 | #define MTK_PHY_DA_TX_R50_PAIR_B (0x53e) |
| 181 | #define MTK_PHY_DA_TX_R50_PAIR_C (0x53f) |
| 182 | #define MTK_PHY_DA_TX_R50_PAIR_D (0x540) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 183 | |
| 184 | /* Registers on MDIO_MMD_VEND2 */ |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 185 | #define MTK_PHY_LED0_ON_CTRL (0x24) |
developer | 2302129 | 2022-10-21 19:10:10 +0800 | [diff] [blame] | 186 | #define MTK_PHY_LED0_ON_MASK GENMASK(6, 0) |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 187 | #define MTK_PHY_LED0_ON_LINK1000 BIT(0) |
| 188 | #define MTK_PHY_LED0_ON_LINK100 BIT(1) |
| 189 | #define MTK_PHY_LED0_ON_LINK10 BIT(2) |
| 190 | #define MTK_PHY_LED0_ON_LINKDOWN BIT(3) |
| 191 | #define MTK_PHY_LED0_ON_FDX BIT(4) /* Full duplex */ |
| 192 | #define MTK_PHY_LED0_ON_HDX BIT(5) /* Half duplex */ |
| 193 | #define MTK_PHY_LED0_FORCE_ON BIT(6) |
| 194 | #define MTK_PHY_LED0_POLARITY BIT(14) |
| 195 | #define MTK_PHY_LED0_ENABLE BIT(15) |
developer | 2302129 | 2022-10-21 19:10:10 +0800 | [diff] [blame] | 196 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 197 | #define MTK_PHY_LED0_BLINK_CTRL (0x25) |
| 198 | #define MTK_PHY_LED0_1000TX BIT(0) |
| 199 | #define MTK_PHY_LED0_1000RX BIT(1) |
| 200 | #define MTK_PHY_LED0_100TX BIT(2) |
| 201 | #define MTK_PHY_LED0_100RX BIT(3) |
| 202 | #define MTK_PHY_LED0_10TX BIT(4) |
| 203 | #define MTK_PHY_LED0_10RX BIT(5) |
| 204 | #define MTK_PHY_LED0_COLLISION BIT(6) |
| 205 | #define MTK_PHY_LED0_RX_CRC_ERR BIT(7) |
| 206 | #define MTK_PHY_LED0_RX_IDLE_ERR BIT(8) |
| 207 | #define MTK_PHY_LED0_FORCE_BLINK BIT(9) |
developer | 8bc5dca | 2022-10-24 17:15:12 +0800 | [diff] [blame] | 208 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 209 | #define MTK_PHY_ANA_TEST_BUS_CTRL_RG (0x100) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 210 | #define MTK_PHY_ANA_TEST_MODE_MASK GENMASK(15, 8) |
| 211 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 212 | #define MTK_PHY_RG_DASN_TXT_DMY2 (0x110) |
| 213 | #define MTK_PHY_TST_DMY2_MASK GENMASK(5, 0) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 214 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 215 | #define MTK_PHY_RG_BG_RASEL (0x115) |
| 216 | #define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 217 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 218 | /* These macro privides efuse parsing for internal phy. */ |
| 219 | #define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0)) |
| 220 | #define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0)) |
| 221 | #define EFS_DA_TX_I2MPB_C(x) (((x) >> 12) & GENMASK(5, 0)) |
| 222 | #define EFS_DA_TX_I2MPB_D(x) (((x) >> 18) & GENMASK(5, 0)) |
| 223 | #define EFS_DA_TX_AMP_OFFSET_A(x) (((x) >> 24) & GENMASK(5, 0)) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 224 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 225 | #define EFS_DA_TX_AMP_OFFSET_B(x) (((x) >> 0) & GENMASK(5, 0)) |
| 226 | #define EFS_DA_TX_AMP_OFFSET_C(x) (((x) >> 6) & GENMASK(5, 0)) |
| 227 | #define EFS_DA_TX_AMP_OFFSET_D(x) (((x) >> 12) & GENMASK(5, 0)) |
| 228 | #define EFS_DA_TX_R50_A(x) (((x) >> 18) & GENMASK(5, 0)) |
| 229 | #define EFS_DA_TX_R50_B(x) (((x) >> 24) & GENMASK(5, 0)) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 230 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 231 | #define EFS_DA_TX_R50_C(x) (((x) >> 0) & GENMASK(5, 0)) |
| 232 | #define EFS_DA_TX_R50_D(x) (((x) >> 6) & GENMASK(5, 0)) |
| 233 | #define EFS_DA_TX_R50_A_10M(x) (((x) >> 12) & GENMASK(5, 0)) |
| 234 | #define EFS_DA_TX_R50_B_10M(x) (((x) >> 18) & GENMASK(5, 0)) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 235 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 236 | #define EFS_RG_BG_RASEL(x) (((x) >> 4) & GENMASK(2, 0)) |
| 237 | #define EFS_RG_REXT_TRIM(x) (((x) >> 7) & GENMASK(5, 0)) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 238 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 239 | enum { |
| 240 | NO_PAIR, |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 241 | PAIR_A, |
| 242 | PAIR_B, |
| 243 | PAIR_C, |
| 244 | PAIR_D, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 245 | }; |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 246 | |
developer | 2302129 | 2022-10-21 19:10:10 +0800 | [diff] [blame] | 247 | enum { |
| 248 | GPHY_PORT0, |
| 249 | GPHY_PORT1, |
| 250 | GPHY_PORT2, |
| 251 | GPHY_PORT3, |
| 252 | }; |
| 253 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 254 | enum calibration_mode { |
| 255 | EFUSE_K, |
| 256 | SW_K |
| 257 | }; |
| 258 | |
| 259 | enum CAL_ITEM { |
| 260 | REXT, |
| 261 | TX_OFFSET, |
| 262 | TX_AMP, |
| 263 | TX_R50, |
| 264 | TX_VCM |
| 265 | }; |
| 266 | |
| 267 | enum CAL_MODE { |
| 268 | SW_EFUSE_M, |
| 269 | EFUSE_M, |
| 270 | SW_M |
| 271 | }; |
| 272 | |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 273 | const u8 mt798x_zcal_to_r50[64] = { |
| 274 | 7, 8, 9, 9, 10, 10, 11, 11, |
| 275 | 12, 13, 13, 14, 14, 15, 16, 16, |
| 276 | 17, 18, 18, 19, 20, 21, 21, 22, |
| 277 | 23, 24, 24, 25, 26, 27, 28, 29, |
| 278 | 30, 31, 32, 33, 34, 35, 36, 37, |
| 279 | 38, 40, 41, 42, 43, 45, 46, 48, |
| 280 | 49, 51, 52, 54, 55, 57, 59, 61, |
| 281 | 62, 63, 63, 63, 63, 63, 63, 63 |
| 282 | }; |
| 283 | |
| 284 | const char pair[4] = {'A', 'B', 'C', 'D'}; |
| 285 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 286 | static int mtk_gephy_read_page(struct phy_device *phydev) |
| 287 | { |
| 288 | return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); |
| 289 | } |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 290 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 291 | static int mtk_gephy_write_page(struct phy_device *phydev, int page) |
| 292 | { |
| 293 | return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page); |
| 294 | } |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 295 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 296 | static void mtk_gephy_config_init(struct phy_device *phydev) |
| 297 | { |
| 298 | /* Disable EEE */ |
| 299 | phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 300 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 301 | /* Enable HW auto downshift */ |
| 302 | phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED, 0x14, 0, BIT(4)); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 303 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 304 | /* Increase SlvDPSready time */ |
| 305 | phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); |
| 306 | __phy_write(phydev, 0x10, 0xafae); |
| 307 | __phy_write(phydev, 0x12, 0x2f); |
| 308 | __phy_write(phydev, 0x10, 0x8fae); |
| 309 | phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 310 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 311 | /* Adjust 100_mse_threshold */ |
| 312 | phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x123, 0xffff); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 313 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 314 | /* Disable mcc */ |
| 315 | phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xa6, 0x300); |
| 316 | } |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 317 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 318 | static int mt7530_phy_config_init(struct phy_device *phydev) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 319 | { |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 320 | mtk_gephy_config_init(phydev); |
| 321 | |
| 322 | /* Increase post_update_timer */ |
| 323 | phy_write_paged(phydev, MTK_PHY_PAGE_EXTENDED_3, 0x11, 0x4b); |
| 324 | |
| 325 | return 0; |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 326 | } |
| 327 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 328 | static int mt7531_phy_config_init(struct phy_device *phydev) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 329 | { |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 330 | mtk_gephy_config_init(phydev); |
| 331 | |
| 332 | /* PHY link down power saving enable */ |
| 333 | phy_set_bits(phydev, 0x17, BIT(4)); |
| 334 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 0xc6, 0x300); |
| 335 | |
| 336 | /* Set TX Pair delay selection */ |
| 337 | phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x13, 0x404); |
| 338 | phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x14, 0x404); |
| 339 | |
| 340 | return 0; |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 341 | } |
| 342 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 343 | #ifdef CONFIG_MEDIATEK_GE_PHY_SOC |
| 344 | /* One calibration cycle consists of: |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 345 | * 1.Set DA_CALIN_FLAG high to start calibration. Keep it high |
| 346 | * until AD_CAL_COMP is ready to output calibration result. |
| 347 | * 2.Wait until DA_CAL_CLK is available. |
| 348 | * 3.Fetch AD_CAL_COMP_OUT. |
| 349 | */ |
| 350 | static int cal_cycle(struct phy_device *phydev, int devad, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 351 | u32 regnum, u16 mask, u16 cal_val) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 352 | { |
| 353 | unsigned long timeout; |
| 354 | int reg_val; |
| 355 | int ret; |
| 356 | |
| 357 | phy_modify_mmd(phydev, devad, regnum, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 358 | mask, cal_val); |
| 359 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, |
| 360 | MTK_PHY_DA_CALIN_FLAG); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 361 | |
| 362 | timeout = jiffies + usecs_to_jiffies(ANALOG_INTERNAL_OPERATION_MAX_US); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 363 | do { |
| 364 | reg_val = phy_read_mmd(phydev, MDIO_MMD_VEND1, |
| 365 | MTK_PHY_RG_AD_CAL_CLK); |
| 366 | } while (time_before(jiffies, timeout) && !(reg_val & BIT(0))); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 367 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 368 | if (!(reg_val & BIT(0))) { |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 369 | dev_err(&phydev->mdio.dev, "Calibration cycle timeout\n"); |
| 370 | return -ETIMEDOUT; |
| 371 | } |
| 372 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 373 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, |
| 374 | MTK_PHY_DA_CALIN_FLAG); |
| 375 | ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP) >> |
| 376 | MTK_PHY_AD_CAL_COMP_OUT_SHIFT; |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 377 | dev_dbg(&phydev->mdio.dev, "cal_val: 0x%x, ret: %d\n", cal_val, ret); |
| 378 | |
| 379 | return ret; |
| 380 | } |
| 381 | |
| 382 | static int rext_fill_result(struct phy_device *phydev, u16 *buf) |
| 383 | { |
| 384 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 385 | MTK_PHY_RG_REXT_TRIM_MASK, buf[0] << 8); |
| 386 | phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_BG_RASEL, |
| 387 | MTK_PHY_RG_BG_RASEL_MASK, buf[1]); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 388 | |
| 389 | return 0; |
| 390 | } |
| 391 | |
| 392 | static int rext_cal_efuse(struct phy_device *phydev, u32 *buf) |
| 393 | { |
| 394 | u16 rext_cal_val[2]; |
| 395 | |
| 396 | rext_cal_val[0] = EFS_RG_REXT_TRIM(buf[3]); |
| 397 | rext_cal_val[1] = EFS_RG_BG_RASEL(buf[3]); |
| 398 | rext_fill_result(phydev, rext_cal_val); |
| 399 | |
| 400 | return 0; |
| 401 | } |
| 402 | |
| 403 | static int rext_cal_sw(struct phy_device *phydev) |
| 404 | { |
| 405 | u8 rg_zcal_ctrl_def; |
| 406 | u8 zcal_lower, zcal_upper, rg_zcal_ctrl; |
| 407 | u8 lower_ret, upper_ret; |
| 408 | u16 rext_cal_val[2]; |
| 409 | int ret; |
| 410 | |
| 411 | phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_ANA_TEST_BUS_CTRL_RG, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 412 | MTK_PHY_ANA_TEST_MODE_MASK, MTK_PHY_TANA_CAL_MODE << 8); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 413 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 414 | MTK_PHY_RG_TXVOS_CALEN); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 415 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 416 | MTK_PHY_RG_CAL_CKINV | MTK_PHY_RG_ANA_CALEN | |
| 417 | MTK_PHY_RG_REXT_CALEN); |
| 418 | phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_DASN_TXT_DMY2, |
| 419 | MTK_PHY_TST_DMY2_MASK, 0x1); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 420 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 421 | rg_zcal_ctrl_def = phy_read_mmd(phydev, MDIO_MMD_VEND1, |
| 422 | MTK_PHY_RG_ANA_CAL_RG5) & |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 423 | MTK_PHY_RG_ZCAL_CTRL_MASK; |
| 424 | zcal_lower = ZCAL_CTRL_MIN; |
| 425 | zcal_upper = ZCAL_CTRL_MAX; |
| 426 | |
| 427 | dev_dbg(&phydev->mdio.dev, "Start REXT SW cal.\n"); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 428 | while ((zcal_upper - zcal_lower) > 1) { |
| 429 | rg_zcal_ctrl = DIV_ROUND_CLOSEST(zcal_lower + zcal_upper, 2); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 430 | ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5, |
| 431 | MTK_PHY_RG_ZCAL_CTRL_MASK, rg_zcal_ctrl); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 432 | if (ret == 1) { |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 433 | zcal_upper = rg_zcal_ctrl; |
developer | 78aa7b9 | 2021-12-29 15:22:10 +0800 | [diff] [blame] | 434 | upper_ret = ret; |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 435 | } else if (ret == 0) { |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 436 | zcal_lower = rg_zcal_ctrl; |
developer | 78aa7b9 | 2021-12-29 15:22:10 +0800 | [diff] [blame] | 437 | lower_ret = ret; |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 438 | } else { |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 439 | goto restore; |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 440 | } |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 441 | } |
| 442 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 443 | if (zcal_lower == ZCAL_CTRL_MIN) { |
| 444 | lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1, |
| 445 | MTK_PHY_RG_ANA_CAL_RG5, |
| 446 | MTK_PHY_RG_ZCAL_CTRL_MASK, zcal_lower); |
| 447 | ret = lower_ret; |
| 448 | } else if (zcal_upper == ZCAL_CTRL_MAX) { |
| 449 | upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1, |
| 450 | MTK_PHY_RG_ANA_CAL_RG5, |
| 451 | MTK_PHY_RG_ZCAL_CTRL_MASK, zcal_upper); |
| 452 | ret = upper_ret; |
developer | 78aa7b9 | 2021-12-29 15:22:10 +0800 | [diff] [blame] | 453 | } |
| 454 | if (ret < 0) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 455 | goto restore; |
| 456 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 457 | ret = upper_ret - lower_ret; |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 458 | if (ret == 1) { |
| 459 | rext_cal_val[0] = zcal_upper; |
| 460 | rext_cal_val[1] = zcal_upper >> 3; |
developer | 78aa7b9 | 2021-12-29 15:22:10 +0800 | [diff] [blame] | 461 | rext_fill_result(phydev, rext_cal_val); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 462 | dev_info(&phydev->mdio.dev, "REXT SW cal result: 0x%x\n", |
| 463 | zcal_upper); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 464 | ret = 0; |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 465 | } else { |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 466 | ret = -EINVAL; |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 467 | } |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 468 | |
| 469 | restore: |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 470 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, |
| 471 | MTK_PHY_ANA_TEST_BUS_CTRL_RG, |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 472 | MTK_PHY_ANA_TEST_MODE_MASK); |
| 473 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 474 | MTK_PHY_RG_CAL_CKINV | MTK_PHY_RG_ANA_CALEN | |
| 475 | MTK_PHY_RG_REXT_CALEN); |
| 476 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_DASN_TXT_DMY2, |
| 477 | MTK_PHY_TST_DMY2_MASK); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 478 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5, |
| 479 | MTK_PHY_RG_ZCAL_CTRL_MASK, rg_zcal_ctrl_def); |
| 480 | |
| 481 | return ret; |
| 482 | } |
| 483 | |
| 484 | static int tx_offset_fill_result(struct phy_device *phydev, u16 *buf) |
| 485 | { |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 486 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 487 | MTK_PHY_CR_TX_AMP_OFFSET_A_MASK, buf[0] << 8); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 488 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 489 | MTK_PHY_CR_TX_AMP_OFFSET_B_MASK, buf[1]); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 490 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 491 | MTK_PHY_CR_TX_AMP_OFFSET_C_MASK, buf[2] << 8); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 492 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 493 | MTK_PHY_CR_TX_AMP_OFFSET_D_MASK, buf[3]); |
| 494 | |
| 495 | return 0; |
| 496 | } |
| 497 | |
| 498 | static int tx_offset_cal_efuse(struct phy_device *phydev, u32 *buf) |
| 499 | { |
| 500 | u16 tx_offset_cal_val[4]; |
| 501 | |
| 502 | tx_offset_cal_val[0] = EFS_DA_TX_AMP_OFFSET_A(buf[0]); |
| 503 | tx_offset_cal_val[1] = EFS_DA_TX_AMP_OFFSET_B(buf[1]); |
| 504 | tx_offset_cal_val[2] = EFS_DA_TX_AMP_OFFSET_C(buf[1]); |
| 505 | tx_offset_cal_val[3] = EFS_DA_TX_AMP_OFFSET_D(buf[1]); |
| 506 | |
| 507 | tx_offset_fill_result(phydev, tx_offset_cal_val); |
| 508 | |
| 509 | return 0; |
| 510 | } |
| 511 | |
| 512 | static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf) |
| 513 | { |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 514 | int i; |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 515 | int bias[16] = {0}; |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 516 | const int vals_9461[16] = { 7, 1, 4, 7, |
| 517 | 7, 1, 4, 7, |
| 518 | 7, 1, 4, 7, |
| 519 | 7, 1, 4, 7 }; |
| 520 | const int vals_9481[16] = { 10, 6, 6, 10, |
| 521 | 10, 6, 6, 10, |
| 522 | 10, 6, 6, 10, |
| 523 | 10, 6, 6, 10 }; |
| 524 | |
| 525 | switch (phydev->drv->phy_id) { |
| 526 | case 0x03a29461: |
| 527 | /* We add some calibration to efuse values |
| 528 | * due to board level influence. |
| 529 | * GBE: +7, TBT: +1, HBT: +4, TST: +7 |
| 530 | */ |
| 531 | memcpy(bias, (const void *)vals_9461, sizeof(bias)); |
| 532 | for (i = 0; i <= 12; i += 4) { |
| 533 | if (likely(buf[i >> 2] + bias[i] >= 32)) { |
| 534 | bias[i] -= 13; |
| 535 | } else { |
| 536 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, |
| 537 | 0x5c, 0x7 << i, bias[i] << i); |
| 538 | bias[i + 1] += 13; |
| 539 | bias[i + 2] += 13; |
| 540 | bias[i + 3] += 13; |
| 541 | } |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 542 | } |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 543 | break; |
| 544 | case 0x03a29481: |
| 545 | memcpy(bias, (const void *)vals_9481, sizeof(bias)); |
| 546 | break; |
| 547 | default: |
| 548 | break; |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 549 | } |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 550 | |
developer | dc3e950 | 2022-12-02 18:10:42 +0800 | [diff] [blame] | 551 | /* Prevent overflow */ |
| 552 | for (i = 0; i < 12; i++) { |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 553 | if (buf[i >> 2] + bias[i] > 63) { |
| 554 | buf[i >> 2] = 63; |
developer | dc3e950 | 2022-12-02 18:10:42 +0800 | [diff] [blame] | 555 | bias[i] = 0; |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 556 | } else if (buf[i >> 2] + bias[i] < 0) { |
developer | dc3e950 | 2022-12-02 18:10:42 +0800 | [diff] [blame] | 557 | /* Bias caused by board design may change in the future. |
| 558 | * So check negative cases, too. |
| 559 | */ |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 560 | buf[i >> 2] = 0; |
developer | dc3e950 | 2022-12-02 18:10:42 +0800 | [diff] [blame] | 561 | bias[i] = 0; |
| 562 | } |
| 563 | } |
| 564 | |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 565 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 566 | MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, (buf[0] + bias[0]) << 10); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 567 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 568 | MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, buf[0] + bias[1]); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 569 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 570 | MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, (buf[0] + bias[2]) << 10); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 571 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 572 | MTK_PHY_DA_TX_I2MPB_A_TST_MASK, buf[0] + bias[3]); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 573 | |
| 574 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 575 | MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, (buf[1] + bias[4]) << 8); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 576 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 577 | MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, buf[1] + bias[5]); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 578 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 579 | MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, (buf[1] + bias[6]) << 8); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 580 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 581 | MTK_PHY_DA_TX_I2MPB_B_TST_MASK, buf[1] + bias[7]); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 582 | |
| 583 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 584 | MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, (buf[2] + bias[8]) << 8); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 585 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 586 | MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, buf[2] + bias[9]); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 587 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 588 | MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, (buf[2] + bias[10]) << 8); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 589 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 590 | MTK_PHY_DA_TX_I2MPB_C_TST_MASK, buf[2] + bias[11]); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 591 | |
| 592 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 593 | MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, (buf[3] + bias[12]) << 8); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 594 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 595 | MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, buf[3] + bias[13]); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 596 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 597 | MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, (buf[3] + bias[14]) << 8); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 598 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 599 | MTK_PHY_DA_TX_I2MPB_D_TST_MASK, buf[3] + bias[15]); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 600 | |
| 601 | return 0; |
| 602 | } |
| 603 | |
| 604 | static int tx_amp_cal_efuse(struct phy_device *phydev, u32 *buf) |
| 605 | { |
| 606 | u16 tx_amp_cal_val[4]; |
| 607 | |
| 608 | tx_amp_cal_val[0] = EFS_DA_TX_I2MPB_A(buf[0]); |
| 609 | tx_amp_cal_val[1] = EFS_DA_TX_I2MPB_B(buf[0]); |
| 610 | tx_amp_cal_val[2] = EFS_DA_TX_I2MPB_C(buf[0]); |
| 611 | tx_amp_cal_val[3] = EFS_DA_TX_I2MPB_D(buf[0]); |
| 612 | tx_amp_fill_result(phydev, tx_amp_cal_val); |
| 613 | |
| 614 | return 0; |
| 615 | } |
| 616 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 617 | static int tx_r50_fill_result(struct phy_device *phydev, u16 tx_r50_cal_val, |
| 618 | u8 txg_calen_x) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 619 | { |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 620 | int bias = 0; |
| 621 | u16 reg, val; |
developer | 87c89d1 | 2022-08-19 17:46:34 +0800 | [diff] [blame] | 622 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 623 | switch (phydev->drv->phy_id) { |
| 624 | case 0x03a29481: |
| 625 | { |
| 626 | bias = -2; |
| 627 | break; |
developer | dc3e950 | 2022-12-02 18:10:42 +0800 | [diff] [blame] | 628 | } |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 629 | /* 0x03a29461 enters default case */ |
| 630 | default: |
| 631 | break; |
| 632 | } |
| 633 | |
| 634 | val = clamp_val(bias + tx_r50_cal_val, 0, 63); |
| 635 | |
| 636 | switch (txg_calen_x) { |
| 637 | case PAIR_A: |
| 638 | reg = MTK_PHY_DA_TX_R50_PAIR_A; |
| 639 | break; |
| 640 | case PAIR_B: |
| 641 | reg = MTK_PHY_DA_TX_R50_PAIR_B; |
| 642 | break; |
| 643 | case PAIR_C: |
| 644 | reg = MTK_PHY_DA_TX_R50_PAIR_C; |
| 645 | break; |
| 646 | case PAIR_D: |
| 647 | reg = MTK_PHY_DA_TX_R50_PAIR_D; |
| 648 | break; |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 649 | } |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 650 | |
| 651 | phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, val | val << 8); |
| 652 | |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 653 | return 0; |
| 654 | } |
| 655 | |
| 656 | static int tx_r50_cal_efuse(struct phy_device *phydev, u32 *buf, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 657 | u8 txg_calen_x) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 658 | { |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 659 | u16 tx_r50_cal_val; |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 660 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 661 | switch (txg_calen_x) { |
| 662 | case PAIR_A: |
| 663 | tx_r50_cal_val = EFS_DA_TX_R50_A(buf[1]); |
| 664 | break; |
| 665 | case PAIR_B: |
| 666 | tx_r50_cal_val = EFS_DA_TX_R50_B(buf[1]); |
| 667 | break; |
| 668 | case PAIR_C: |
| 669 | tx_r50_cal_val = EFS_DA_TX_R50_C(buf[2]); |
| 670 | break; |
| 671 | case PAIR_D: |
| 672 | tx_r50_cal_val = EFS_DA_TX_R50_D(buf[2]); |
| 673 | break; |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 674 | } |
| 675 | tx_r50_fill_result(phydev, tx_r50_cal_val, txg_calen_x); |
| 676 | |
| 677 | return 0; |
| 678 | } |
| 679 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 680 | static int tx_r50_cal_sw(struct phy_device *phydev, u8 txg_calen_x) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 681 | { |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 682 | u8 zcal_lower, zcal_upper, rg_zcal_ctrl; |
| 683 | u8 lower_ret, upper_ret; |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 684 | u8 rg_zcal_ctrl_def; |
| 685 | u16 tx_r50_cal_val; |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 686 | int ret; |
| 687 | |
| 688 | phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_ANA_TEST_BUS_CTRL_RG, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 689 | MTK_PHY_ANA_TEST_MODE_MASK, MTK_PHY_TANA_CAL_MODE << 8); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 690 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 691 | MTK_PHY_RG_TXVOS_CALEN); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 692 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 693 | MTK_PHY_RG_CAL_CKINV | MTK_PHY_RG_ANA_CALEN); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 694 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG2, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 695 | BIT(txg_calen_x * 4)); |
| 696 | phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_DASN_TXT_DMY2, |
| 697 | MTK_PHY_TST_DMY2_MASK, 0x1); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 698 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 699 | rg_zcal_ctrl_def = phy_read_mmd(phydev, MDIO_MMD_VEND1, |
| 700 | MTK_PHY_RG_ANA_CAL_RG5) & |
| 701 | MTK_PHY_RG_ZCAL_CTRL_MASK; |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 702 | zcal_lower = ZCAL_CTRL_MIN; |
| 703 | zcal_upper = ZCAL_CTRL_MAX; |
| 704 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 705 | dev_dbg(&phydev->mdio.dev, "Start TX-R50 Pair%c SW cal.\n", |
| 706 | pair[txg_calen_x]); |
| 707 | while ((zcal_upper - zcal_lower) > 1) { |
| 708 | rg_zcal_ctrl = DIV_ROUND_CLOSEST(zcal_lower + zcal_upper, 2); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 709 | ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5, |
| 710 | MTK_PHY_RG_ZCAL_CTRL_MASK, rg_zcal_ctrl); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 711 | if (ret == 1) { |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 712 | zcal_upper = rg_zcal_ctrl; |
developer | 78aa7b9 | 2021-12-29 15:22:10 +0800 | [diff] [blame] | 713 | upper_ret = ret; |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 714 | } else if (ret == 0) { |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 715 | zcal_lower = rg_zcal_ctrl; |
developer | 78aa7b9 | 2021-12-29 15:22:10 +0800 | [diff] [blame] | 716 | lower_ret = ret; |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 717 | } else { |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 718 | goto restore; |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 719 | } |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 720 | } |
| 721 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 722 | if (zcal_lower == ZCAL_CTRL_MIN) { |
| 723 | lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1, |
| 724 | MTK_PHY_RG_ANA_CAL_RG5, |
| 725 | MTK_PHY_RG_ZCAL_CTRL_MASK, zcal_lower); |
| 726 | ret = lower_ret; |
| 727 | } else if (zcal_upper == ZCAL_CTRL_MAX) { |
| 728 | upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1, |
| 729 | MTK_PHY_RG_ANA_CAL_RG5, |
| 730 | MTK_PHY_RG_ZCAL_CTRL_MASK, zcal_upper); |
| 731 | ret = upper_ret; |
developer | 78aa7b9 | 2021-12-29 15:22:10 +0800 | [diff] [blame] | 732 | } |
| 733 | if (ret < 0) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 734 | goto restore; |
| 735 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 736 | ret = upper_ret - lower_ret; |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 737 | if (ret == 1) { |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 738 | tx_r50_cal_val = mt798x_zcal_to_r50[zcal_upper]; |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 739 | tx_r50_fill_result(phydev, tx_r50_cal_val, txg_calen_x); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 740 | dev_info(&phydev->mdio.dev, |
| 741 | "TX-R50 Pair%c SW cal result: 0x%x\n", |
| 742 | pair[txg_calen_x], zcal_lower); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 743 | ret = 0; |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 744 | } else { |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 745 | ret = -EINVAL; |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 746 | } |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 747 | |
| 748 | restore: |
| 749 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_ANA_TEST_BUS_CTRL_RG, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 750 | MTK_PHY_ANA_TEST_MODE_MASK); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 751 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 752 | MTK_PHY_RG_CAL_CKINV | MTK_PHY_RG_ANA_CALEN); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 753 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG2, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 754 | BIT(txg_calen_x * 4)); |
| 755 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_DASN_TXT_DMY2, |
| 756 | MTK_PHY_TST_DMY2_MASK); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 757 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 758 | MTK_PHY_RG_ZCAL_CTRL_MASK, rg_zcal_ctrl_def); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 759 | |
| 760 | return ret; |
| 761 | } |
| 762 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 763 | static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 764 | { |
| 765 | u8 lower_idx, upper_idx, txreserve_val; |
| 766 | u8 lower_ret, upper_ret; |
| 767 | int ret; |
| 768 | |
| 769 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 770 | MTK_PHY_RG_ANA_CALEN); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 771 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 772 | MTK_PHY_RG_CAL_CKINV); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 773 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 774 | MTK_PHY_RG_TXVOS_CALEN); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 775 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 776 | switch (rg_txreserve_x) { |
| 777 | case PAIR_A: |
| 778 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, |
| 779 | MTK_PHY_RG_DASN_DAC_IN0_A, |
| 780 | MTK_PHY_DASN_DAC_IN0_A_MASK); |
| 781 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, |
| 782 | MTK_PHY_RG_DASN_DAC_IN1_A, |
| 783 | MTK_PHY_DASN_DAC_IN1_A_MASK); |
| 784 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, |
| 785 | MTK_PHY_RG_ANA_CAL_RG0, |
| 786 | MTK_PHY_RG_ZCALEN_A); |
| 787 | break; |
| 788 | case PAIR_B: |
| 789 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, |
| 790 | MTK_PHY_RG_DASN_DAC_IN0_B, |
| 791 | MTK_PHY_DASN_DAC_IN0_B_MASK); |
| 792 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, |
| 793 | MTK_PHY_RG_DASN_DAC_IN1_B, |
| 794 | MTK_PHY_DASN_DAC_IN1_B_MASK); |
| 795 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, |
| 796 | MTK_PHY_RG_ANA_CAL_RG1, |
| 797 | MTK_PHY_RG_ZCALEN_B); |
| 798 | break; |
| 799 | case PAIR_C: |
| 800 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, |
| 801 | MTK_PHY_RG_DASN_DAC_IN0_C, |
| 802 | MTK_PHY_DASN_DAC_IN0_C_MASK); |
| 803 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, |
| 804 | MTK_PHY_RG_DASN_DAC_IN1_C, |
| 805 | MTK_PHY_DASN_DAC_IN1_C_MASK); |
| 806 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, |
| 807 | MTK_PHY_RG_ANA_CAL_RG1, |
| 808 | MTK_PHY_RG_ZCALEN_C); |
| 809 | break; |
| 810 | case PAIR_D: |
| 811 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, |
| 812 | MTK_PHY_RG_DASN_DAC_IN0_D, |
| 813 | MTK_PHY_DASN_DAC_IN0_D_MASK); |
| 814 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, |
| 815 | MTK_PHY_RG_DASN_DAC_IN1_D, |
| 816 | MTK_PHY_DASN_DAC_IN1_D_MASK); |
| 817 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, |
| 818 | MTK_PHY_RG_ANA_CAL_RG1, |
| 819 | MTK_PHY_RG_ZCALEN_D); |
| 820 | break; |
| 821 | default: |
| 822 | ret = -EINVAL; |
| 823 | goto restore; |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 824 | } |
| 825 | |
| 826 | lower_idx = TXRESERVE_MIN; |
| 827 | upper_idx = TXRESERVE_MAX; |
| 828 | |
| 829 | dev_dbg(&phydev->mdio.dev, "Start TX-VCM SW cal.\n"); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 830 | while ((upper_idx - lower_idx) > 1) { |
| 831 | txreserve_val = DIV_ROUND_CLOSEST(lower_idx + upper_idx, 2); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 832 | ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 833 | MTK_PHY_DA_RX_PSBN_TBT_MASK | |
| 834 | MTK_PHY_DA_RX_PSBN_HBT_MASK | |
| 835 | MTK_PHY_DA_RX_PSBN_GBE_MASK | |
| 836 | MTK_PHY_DA_RX_PSBN_LP_MASK, |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 837 | txreserve_val << 12 | txreserve_val << 8 | |
| 838 | txreserve_val << 4 | txreserve_val); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 839 | if (ret == 1) { |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 840 | upper_idx = txreserve_val; |
developer | 78aa7b9 | 2021-12-29 15:22:10 +0800 | [diff] [blame] | 841 | upper_ret = ret; |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 842 | } else if (ret == 0) { |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 843 | lower_idx = txreserve_val; |
developer | 78aa7b9 | 2021-12-29 15:22:10 +0800 | [diff] [blame] | 844 | lower_ret = ret; |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 845 | } else { |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 846 | goto restore; |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 847 | } |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 848 | } |
| 849 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 850 | if (lower_idx == TXRESERVE_MIN) { |
| 851 | lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1, |
| 852 | MTK_PHY_RXADC_CTRL_RG9, |
| 853 | MTK_PHY_DA_RX_PSBN_TBT_MASK | |
| 854 | MTK_PHY_DA_RX_PSBN_HBT_MASK | |
| 855 | MTK_PHY_DA_RX_PSBN_GBE_MASK | |
| 856 | MTK_PHY_DA_RX_PSBN_LP_MASK, |
| 857 | lower_idx << 12 | lower_idx << 8 | |
| 858 | lower_idx << 4 | lower_idx); |
| 859 | ret = lower_ret; |
| 860 | } else if (upper_idx == TXRESERVE_MAX) { |
| 861 | upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1, |
| 862 | MTK_PHY_RXADC_CTRL_RG9, |
| 863 | MTK_PHY_DA_RX_PSBN_TBT_MASK | |
| 864 | MTK_PHY_DA_RX_PSBN_HBT_MASK | |
| 865 | MTK_PHY_DA_RX_PSBN_GBE_MASK | |
| 866 | MTK_PHY_DA_RX_PSBN_LP_MASK, |
| 867 | upper_idx << 12 | upper_idx << 8 | |
| 868 | upper_idx << 4 | upper_idx); |
| 869 | ret = upper_ret; |
developer | 78aa7b9 | 2021-12-29 15:22:10 +0800 | [diff] [blame] | 870 | } |
| 871 | if (ret < 0) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 872 | goto restore; |
| 873 | |
developer | 78aa7b9 | 2021-12-29 15:22:10 +0800 | [diff] [blame] | 874 | /* We calibrate TX-VCM in different logic. Check upper index and then |
| 875 | * lower index. If this calibration is valid, apply lower index's result. |
| 876 | */ |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 877 | ret = upper_ret - lower_ret; |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 878 | if (ret == 1) { |
| 879 | ret = 0; |
developer | b5c76d4 | 2022-08-18 15:45:33 +0800 | [diff] [blame] | 880 | /* Make sure we use upper_idx in our calibration system */ |
| 881 | cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 882 | MTK_PHY_DA_RX_PSBN_TBT_MASK | |
| 883 | MTK_PHY_DA_RX_PSBN_HBT_MASK | |
| 884 | MTK_PHY_DA_RX_PSBN_GBE_MASK | |
| 885 | MTK_PHY_DA_RX_PSBN_LP_MASK, |
| 886 | upper_idx << 12 | upper_idx << 8 | |
| 887 | upper_idx << 4 | upper_idx); |
| 888 | dev_info(&phydev->mdio.dev, "TX-VCM SW cal result: 0x%x\n", |
| 889 | upper_idx); |
| 890 | } else if (lower_idx == TXRESERVE_MIN && upper_ret == 1 && |
| 891 | lower_ret == 1) { |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 892 | ret = 0; |
| 893 | cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 894 | MTK_PHY_DA_RX_PSBN_TBT_MASK | |
| 895 | MTK_PHY_DA_RX_PSBN_HBT_MASK | |
| 896 | MTK_PHY_DA_RX_PSBN_GBE_MASK | |
| 897 | MTK_PHY_DA_RX_PSBN_LP_MASK, |
| 898 | lower_idx << 12 | lower_idx << 8 | |
| 899 | lower_idx << 4 | lower_idx); |
| 900 | dev_warn(&phydev->mdio.dev, |
| 901 | "TX-VCM SW cal result at low margin 0x%x\n", |
| 902 | lower_idx); |
| 903 | } else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 && |
| 904 | lower_ret == 0) { |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 905 | ret = 0; |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 906 | dev_warn(&phydev->mdio.dev, |
| 907 | "TX-VCM SW cal result at high margin 0x%x\n", |
| 908 | upper_idx); |
| 909 | } else { |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 910 | ret = -EINVAL; |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 911 | } |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 912 | |
| 913 | restore: |
| 914 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 915 | MTK_PHY_RG_ANA_CALEN); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 916 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 917 | MTK_PHY_RG_TXVOS_CALEN); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 918 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 919 | MTK_PHY_RG_ZCALEN_A); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 920 | phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 921 | MTK_PHY_RG_ZCALEN_B | MTK_PHY_RG_ZCALEN_C | |
| 922 | MTK_PHY_RG_ZCALEN_D); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 923 | |
| 924 | return ret; |
| 925 | } |
| 926 | |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 927 | static inline void mt7981_phy_finetune(struct phy_device *phydev) |
developer | 02d8442 | 2021-12-24 11:48:07 +0800 | [diff] [blame] | 928 | { |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 929 | u32 i; |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 930 | |
developer | 02d8442 | 2021-12-24 11:48:07 +0800 | [diff] [blame] | 931 | /* 100M eye finetune: |
| 932 | * Keep middle level of TX MLT3 shapper as default. |
| 933 | * Only change TX MLT3 overshoot level here. |
| 934 | */ |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 935 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_1st_OVERSHOOT_LEVEL_0TO1, |
| 936 | 0x1ce); |
| 937 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_2nd_OVERSHOOT_LEVEL_0TO1, |
| 938 | 0x1c1); |
| 939 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_1st_OVERSHOOT_LEVEL_1TO0, |
| 940 | 0x20f); |
| 941 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_2nd_OVERSHOOT_LEVEL_1TO0, |
| 942 | 0x202); |
| 943 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_1st_OVERSHOOT_LEVEL_0TON1, |
| 944 | 0x3d0); |
| 945 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_2nd_OVERSHOOT_LEVEL_0TON1, |
| 946 | 0x3c0); |
| 947 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_1st_OVERSHOOT_LEVEL_N1TO0, |
| 948 | 0x13); |
| 949 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_2nd_OVERSHOOT_LEVEL_N1TO0, |
| 950 | 0x5); |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 951 | |
developer | 02d8442 | 2021-12-24 11:48:07 +0800 | [diff] [blame] | 952 | /* TX-AMP finetune: |
| 953 | * 100M +4, 1000M +6 to default value. |
| 954 | * If efuse values aren't valid, TX-AMP uses the below values. |
| 955 | */ |
| 956 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, 0x9824); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 957 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, |
| 958 | 0x9026); |
| 959 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, |
| 960 | 0x2624); |
| 961 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, |
| 962 | 0x2426); |
| 963 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, |
| 964 | 0x2624); |
| 965 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, |
| 966 | 0x2426); |
| 967 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, |
| 968 | 0x2624); |
| 969 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, |
| 970 | 0x2426); |
developer | 68f6e10 | 2022-11-22 17:35:00 +0800 | [diff] [blame] | 971 | |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 972 | phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); |
| 973 | /* EnabRandUpdTrig = 1 */ |
| 974 | __phy_write(phydev, 0x11, 0x2f00); |
| 975 | __phy_write(phydev, 0x12, 0xe); |
| 976 | __phy_write(phydev, 0x10, 0x8fb0); |
| 977 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 978 | /* SlvDSPreadyTime = 0xc */ |
| 979 | __phy_write(phydev, 0x11, 0x671); |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 980 | __phy_write(phydev, 0x12, 0xc); |
| 981 | __phy_write(phydev, 0x10, 0x8fae); |
| 982 | |
| 983 | /* NormMseLoThresh = 85 */ |
| 984 | __phy_write(phydev, 0x11, 0x55a0); |
| 985 | __phy_write(phydev, 0x12, 0x0); |
| 986 | __phy_write(phydev, 0x10, 0x83aa); |
| 987 | |
| 988 | /* InhibitDisableDfeTail1000 = 1 */ |
| 989 | __phy_write(phydev, 0x11, 0x2b); |
| 990 | __phy_write(phydev, 0x12, 0x0); |
| 991 | __phy_write(phydev, 0x10, 0x8f80); |
| 992 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 993 | /* SSTr related */ |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 994 | __phy_write(phydev, 0x11, 0xbaef); |
| 995 | __phy_write(phydev, 0x12, 0x2e); |
| 996 | __phy_write(phydev, 0x10, 0x968c); |
| 997 | |
| 998 | /* VcoSlicerThreshBitsHigh */ |
| 999 | __phy_write(phydev, 0x11, 0x5555); |
| 1000 | __phy_write(phydev, 0x12, 0x55); |
| 1001 | __phy_write(phydev, 0x10, 0x8ec0); |
| 1002 | |
| 1003 | /* ResetSyncOffset = 6 */ |
| 1004 | __phy_write(phydev, 0x11, 0x600); |
| 1005 | __phy_write(phydev, 0x12, 0x0); |
| 1006 | __phy_write(phydev, 0x10, 0x8fc0); |
| 1007 | |
| 1008 | /* VgaDecRate = 1 */ |
| 1009 | __phy_write(phydev, 0x11, 0x4c2a); |
| 1010 | __phy_write(phydev, 0x12, 0x3e); |
| 1011 | __phy_write(phydev, 0x10, 0x8fa4); |
| 1012 | |
| 1013 | phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 1014 | /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9*/ |
developer | 68f6e10 | 2022-11-22 17:35:00 +0800 | [diff] [blame] | 1015 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 1016 | MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK, |
| 1017 | BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9)); |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 1018 | |
| 1019 | /* rg_tr_lpf_cnt_val = 512 */ |
| 1020 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200); |
| 1021 | |
| 1022 | /* IIR2 related */ |
| 1023 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82); |
| 1024 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0); |
| 1025 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103); |
| 1026 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0); |
| 1027 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82); |
| 1028 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0); |
| 1029 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177); |
| 1030 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3); |
| 1031 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82); |
| 1032 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe); |
| 1033 | |
| 1034 | /* FFE peaking */ |
| 1035 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 1036 | MTK_PHY_VGASTATE_FFE_THR_ST1_MASK, 0x1b << 8); |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 1037 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 1038 | MTK_PHY_VGASTATE_FFE_THR_ST2_MASK, 0x1e); |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 1039 | |
| 1040 | /* TX shape */ |
| 1041 | /* 10/100/1000 TX shaper is enabled by default */ |
| 1042 | for (i = 0x202; i < 0x230; i += 2) { |
| 1043 | if (i == 0x20c || i == 0x218 || i == 0x224) |
| 1044 | continue; |
| 1045 | phy_write_mmd(phydev, MDIO_MMD_VEND2, i, 0x2219); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 1046 | phy_write_mmd(phydev, MDIO_MMD_VEND2, i + 1, 0x23); |
developer | d2ec38e | 2022-11-27 01:15:29 +0800 | [diff] [blame] | 1047 | } |
developer | 02d8442 | 2021-12-24 11:48:07 +0800 | [diff] [blame] | 1048 | } |
| 1049 | |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 1050 | static inline void mt7988_phy_finetune(struct phy_device *phydev) |
| 1051 | { |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 1052 | u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182, |
| 1053 | 0x020d, 0x0206, 0x0384, 0x03d0, |
| 1054 | 0x03c6, 0x030a, 0x0011, 0x0005 }; |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 1055 | int i; |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 1056 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 1057 | for (i = 0; i < MTK_PHY_TX_MLT3_END; i++) |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 1058 | phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[i]); |
developer | 6de96aa | 2022-09-29 16:46:18 +0800 | [diff] [blame] | 1059 | |
developer | 5737403 | 2022-10-11 16:43:24 +0800 | [diff] [blame] | 1060 | /* TCT finetune */ |
developer | 6de96aa | 2022-09-29 16:46:18 +0800 | [diff] [blame] | 1061 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5); |
developer | 5737403 | 2022-10-11 16:43:24 +0800 | [diff] [blame] | 1062 | |
| 1063 | /* Disable TX power saving */ |
| 1064 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 1065 | MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8); |
developer | ec2b855 | 2022-10-17 15:30:59 +0800 | [diff] [blame] | 1066 | |
developer | ec2b855 | 2022-10-17 15:30:59 +0800 | [diff] [blame] | 1067 | phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); |
developer | ce73ad6 | 2022-12-07 22:43:45 +0800 | [diff] [blame] | 1068 | /* EnabRandUpdTrig = 1 */ |
| 1069 | __phy_write(phydev, 0x11, 0x2f00); |
| 1070 | __phy_write(phydev, 0x12, 0xe); |
| 1071 | __phy_write(phydev, 0x10, 0x8fb0); |
| 1072 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 1073 | /* SlvDSPreadyTime = 0xc */ |
developer | ce73ad6 | 2022-12-07 22:43:45 +0800 | [diff] [blame] | 1074 | __phy_write(phydev, 0x11, 0x671); |
| 1075 | __phy_write(phydev, 0x12, 0xc); |
| 1076 | __phy_write(phydev, 0x10, 0x8fae); |
| 1077 | |
| 1078 | /* NormMseLoThresh = 85 */ |
| 1079 | __phy_write(phydev, 0x11, 0x55a0); |
developer | ec2b855 | 2022-10-17 15:30:59 +0800 | [diff] [blame] | 1080 | __phy_write(phydev, 0x12, 0x0); |
developer | ce73ad6 | 2022-12-07 22:43:45 +0800 | [diff] [blame] | 1081 | __phy_write(phydev, 0x10, 0x83aa); |
| 1082 | |
| 1083 | /* InhibitDisableDfeTail1000 = 1 */ |
| 1084 | __phy_write(phydev, 0x11, 0x2b); |
| 1085 | __phy_write(phydev, 0x12, 0x0); |
| 1086 | __phy_write(phydev, 0x10, 0x8f80); |
| 1087 | |
| 1088 | /* SSTr related */ |
| 1089 | __phy_write(phydev, 0x11, 0xbaef); |
| 1090 | __phy_write(phydev, 0x12, 0x2e); |
| 1091 | __phy_write(phydev, 0x10, 0x968c); |
| 1092 | |
| 1093 | /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2, |
| 1094 | * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2 |
| 1095 | */ |
| 1096 | __phy_write(phydev, 0x11, 0xd10a); |
| 1097 | __phy_write(phydev, 0x12, 0x34); |
| 1098 | __phy_write(phydev, 0x10, 0x8f82); |
| 1099 | |
| 1100 | /* VcoSlicerThreshBitsHigh */ |
| 1101 | __phy_write(phydev, 0x11, 0x5555); |
| 1102 | __phy_write(phydev, 0x12, 0x55); |
| 1103 | __phy_write(phydev, 0x10, 0x8ec0); |
| 1104 | |
developer | ce26831 | 2022-12-20 16:26:11 +0800 | [diff] [blame] | 1105 | /* ResetSyncOffset = 5 */ |
| 1106 | __phy_write(phydev, 0x11, 0x500); |
developer | ce73ad6 | 2022-12-07 22:43:45 +0800 | [diff] [blame] | 1107 | __phy_write(phydev, 0x12, 0x0); |
| 1108 | __phy_write(phydev, 0x10, 0x8fc0); |
developer | b5c72b0 | 2022-12-21 15:51:07 +0800 | [diff] [blame] | 1109 | phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); |
developer | ce73ad6 | 2022-12-07 22:43:45 +0800 | [diff] [blame] | 1110 | |
developer | ce26831 | 2022-12-20 16:26:11 +0800 | [diff] [blame] | 1111 | phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_2A30); |
| 1112 | /* TxClkOffset = 2 */ |
developer | b5c72b0 | 2022-12-21 15:51:07 +0800 | [diff] [blame] | 1113 | __phy_modify(phydev, MTK_PHY_ANARG_RG, MTK_PHY_TCLKOFFSET_MASK, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 1114 | FIELD_PREP(MTK_PHY_TCLKOFFSET_MASK, 0x2)); |
developer | ec2b855 | 2022-10-17 15:30:59 +0800 | [diff] [blame] | 1115 | phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); |
developer | ce73ad6 | 2022-12-07 22:43:45 +0800 | [diff] [blame] | 1116 | |
| 1117 | /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9*/ |
| 1118 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 1119 | MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK, |
| 1120 | BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9)); |
developer | ce73ad6 | 2022-12-07 22:43:45 +0800 | [diff] [blame] | 1121 | |
| 1122 | /* rg_tr_lpf_cnt_val = 512 */ |
| 1123 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200); |
| 1124 | |
| 1125 | /* IIR2 related */ |
| 1126 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82); |
| 1127 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0); |
| 1128 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103); |
| 1129 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0); |
| 1130 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82); |
| 1131 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0); |
| 1132 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177); |
| 1133 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3); |
| 1134 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82); |
| 1135 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe); |
| 1136 | |
| 1137 | /* FFE peaking */ |
| 1138 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 1139 | MTK_PHY_VGASTATE_FFE_THR_ST1_MASK, 0x1b << 8); |
developer | ce73ad6 | 2022-12-07 22:43:45 +0800 | [diff] [blame] | 1140 | phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 1141 | MTK_PHY_VGASTATE_FFE_THR_ST2_MASK, 0x1e); |
developer | ce73ad6 | 2022-12-07 22:43:45 +0800 | [diff] [blame] | 1142 | |
| 1143 | /* TX shape */ |
| 1144 | /* 10/100/1000 TX shaper is enabled by default */ |
| 1145 | for (i = 0x202; i < 0x230; i += 2) { |
| 1146 | if (i == 0x20c || i == 0x218 || i == 0x224) |
| 1147 | continue; |
| 1148 | phy_write_mmd(phydev, MDIO_MMD_VEND2, i, 0x2219); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 1149 | phy_write_mmd(phydev, MDIO_MMD_VEND2, i + 1, 0x23); |
developer | ce73ad6 | 2022-12-07 22:43:45 +0800 | [diff] [blame] | 1150 | } |
developer | ce26831 | 2022-12-20 16:26:11 +0800 | [diff] [blame] | 1151 | |
| 1152 | /* Disable LDO pump */ |
| 1153 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, 0x0); |
| 1154 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, 0x0); |
| 1155 | |
| 1156 | /* Adjust LDO output voltage */ |
developer | b5c72b0 | 2022-12-21 15:51:07 +0800 | [diff] [blame] | 1157 | phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 1158 | } |
developer | 7581999 | 2023-03-08 20:49:03 +0800 | [diff] [blame] | 1159 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 1160 | static inline int cal_sw(struct phy_device *phydev, enum CAL_ITEM cal_item, |
| 1161 | u8 start_pair, u8 end_pair) |
| 1162 | { |
| 1163 | u8 pair_n; |
| 1164 | int ret; |
| 1165 | |
| 1166 | for (pair_n = start_pair; pair_n <= end_pair; pair_n++) { |
| 1167 | /* TX_OFFSET & TX_AMP have no SW calibration. */ |
| 1168 | switch (cal_item) { |
| 1169 | case REXT: |
| 1170 | ret = rext_cal_sw(phydev); |
| 1171 | break; |
| 1172 | case TX_R50: |
| 1173 | ret = tx_r50_cal_sw(phydev, pair_n); |
| 1174 | break; |
| 1175 | case TX_VCM: |
| 1176 | ret = tx_vcm_cal_sw(phydev, pair_n); |
| 1177 | break; |
| 1178 | default: |
| 1179 | return -EINVAL; |
| 1180 | } |
| 1181 | if (ret) |
| 1182 | return ret; |
| 1183 | } |
| 1184 | return 0; |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 1185 | } |
| 1186 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 1187 | static inline int cal_efuse(struct phy_device *phydev, enum CAL_ITEM cal_item, |
| 1188 | u8 start_pair, u8 end_pair, u32 *buf) |
| 1189 | { |
| 1190 | u8 pair_n; |
| 1191 | int ret; |
| 1192 | |
| 1193 | for (pair_n = start_pair; pair_n <= end_pair; pair_n++) { |
| 1194 | /* TX_VCM has no efuse calibration. */ |
| 1195 | switch (cal_item) { |
| 1196 | case REXT: |
| 1197 | ret = rext_cal_efuse(phydev, buf); |
| 1198 | break; |
| 1199 | case TX_OFFSET: |
| 1200 | ret = tx_offset_cal_efuse(phydev, buf); |
| 1201 | break; |
| 1202 | case TX_AMP: |
| 1203 | ret = tx_amp_cal_efuse(phydev, buf); |
| 1204 | break; |
| 1205 | case TX_R50: |
| 1206 | ret = tx_r50_cal_efuse(phydev, buf, pair_n); |
| 1207 | break; |
| 1208 | default: |
| 1209 | return -EINVAL; |
| 1210 | } |
| 1211 | if (ret) |
| 1212 | return ret; |
| 1213 | } |
| 1214 | |
| 1215 | return 0; |
| 1216 | } |
| 1217 | |
| 1218 | static int start_cal(struct phy_device *phydev, enum CAL_ITEM cal_item, |
| 1219 | bool efs_valid, enum CAL_MODE cal_mode, u8 start_pair, |
| 1220 | u8 end_pair, u32 *buf) |
| 1221 | { |
| 1222 | char cal_prop[5][20] = { "mediatek,rext", "mediatek,tx_offset", |
| 1223 | "mediatek,tx_amp", "mediatek,tx_r50", |
| 1224 | "mediatek,tx_vcm" }; |
| 1225 | const char *dts_cal_mode; |
| 1226 | u8 final_cal_mode = 0; |
| 1227 | bool is_cal = true; |
| 1228 | int ret, cal_ret; |
| 1229 | |
| 1230 | ret = of_property_read_string(phydev->mdio.dev.of_node, |
| 1231 | cal_prop[cal_item], &dts_cal_mode); |
| 1232 | |
| 1233 | switch (cal_mode) { |
| 1234 | case SW_EFUSE_M: |
| 1235 | if ((efs_valid && ret) || |
| 1236 | (efs_valid && !ret && strcmp("efuse", dts_cal_mode) == 0)) { |
| 1237 | cal_ret = cal_efuse(phydev, cal_item, start_pair, |
| 1238 | end_pair, buf); |
| 1239 | final_cal_mode = EFUSE_K; |
| 1240 | } else if ((!efs_valid && ret) || |
| 1241 | (!ret && strcmp("sw", dts_cal_mode) == 0)) { |
| 1242 | cal_ret = cal_sw(phydev, cal_item, start_pair, end_pair); |
| 1243 | final_cal_mode = SW_K; |
| 1244 | } else { |
| 1245 | is_cal = false; |
| 1246 | } |
| 1247 | break; |
| 1248 | case EFUSE_M: |
| 1249 | if ((efs_valid && ret) || |
| 1250 | (efs_valid && !ret && strcmp("efuse", dts_cal_mode) == 0)) { |
| 1251 | cal_ret = cal_efuse(phydev, cal_item, start_pair, |
| 1252 | end_pair, buf); |
| 1253 | final_cal_mode = EFUSE_K; |
| 1254 | } else { |
| 1255 | is_cal = false; |
| 1256 | } |
| 1257 | break; |
| 1258 | case SW_M: |
| 1259 | if (ret || (!ret && strcmp("sw", dts_cal_mode) == 0)) { |
| 1260 | cal_ret = cal_sw(phydev, cal_item, start_pair, end_pair); |
| 1261 | final_cal_mode = SW_K; |
| 1262 | } else { |
| 1263 | is_cal = false; |
| 1264 | } |
| 1265 | break; |
| 1266 | default: |
| 1267 | return -EINVAL; |
| 1268 | } |
| 1269 | |
| 1270 | if (cal_ret) { |
| 1271 | dev_err(&phydev->mdio.dev, "[%s]cal failed\n", cal_prop[cal_item]); |
| 1272 | return -EIO; |
| 1273 | } |
| 1274 | |
| 1275 | if (!is_cal) { |
| 1276 | dev_dbg(&phydev->mdio.dev, "[%s]K mode: %s(not supported)\n", |
| 1277 | cal_prop[cal_item], dts_cal_mode); |
| 1278 | return -EIO; |
| 1279 | } |
| 1280 | |
| 1281 | dev_dbg(&phydev->mdio.dev, "[%s]K mode: %s(dts: %s), efs-valid: %s\n", |
| 1282 | cal_prop[cal_item], |
| 1283 | final_cal_mode ? "SW" : "EFUSE", |
| 1284 | ret ? "not set" : dts_cal_mode, |
| 1285 | efs_valid ? "yes" : "no"); |
| 1286 | return 0; |
| 1287 | } |
| 1288 | |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 1289 | static int mt798x_phy_calibration(struct phy_device *phydev) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 1290 | { |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 1291 | int ret = 0; |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 1292 | u32 *buf; |
| 1293 | bool efs_valid = true; |
| 1294 | size_t len; |
| 1295 | struct nvmem_cell *cell; |
| 1296 | |
| 1297 | if (phydev->interface != PHY_INTERFACE_MODE_GMII) |
| 1298 | return -EINVAL; |
| 1299 | |
| 1300 | cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data"); |
| 1301 | if (IS_ERR(cell)) { |
| 1302 | if (PTR_ERR(cell) == -EPROBE_DEFER) |
| 1303 | return PTR_ERR(cell); |
| 1304 | return 0; |
| 1305 | } |
| 1306 | |
| 1307 | buf = (u32 *)nvmem_cell_read(cell, &len); |
| 1308 | if (IS_ERR(buf)) |
| 1309 | return PTR_ERR(buf); |
| 1310 | nvmem_cell_put(cell); |
| 1311 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 1312 | if (!buf[0] || !buf[1] || !buf[2] || !buf[3]) |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 1313 | efs_valid = false; |
| 1314 | |
| 1315 | if (len < 4 * sizeof(u32)) { |
| 1316 | dev_err(&phydev->mdio.dev, "invalid calibration data\n"); |
| 1317 | ret = -EINVAL; |
| 1318 | goto out; |
| 1319 | } |
| 1320 | |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 1321 | ret = start_cal(phydev, REXT, efs_valid, SW_EFUSE_M, |
| 1322 | NO_PAIR, NO_PAIR, buf); |
| 1323 | if (ret) |
| 1324 | goto out; |
| 1325 | ret = start_cal(phydev, TX_OFFSET, efs_valid, EFUSE_M, |
| 1326 | NO_PAIR, NO_PAIR, buf); |
| 1327 | if (ret) |
| 1328 | goto out; |
| 1329 | ret = start_cal(phydev, TX_AMP, efs_valid, EFUSE_M, |
| 1330 | NO_PAIR, NO_PAIR, buf); |
| 1331 | if (ret) |
| 1332 | goto out; |
| 1333 | ret = start_cal(phydev, TX_R50, efs_valid, EFUSE_M, |
| 1334 | PAIR_A, PAIR_D, buf); |
| 1335 | if (ret) |
| 1336 | goto out; |
| 1337 | ret = start_cal(phydev, TX_VCM, efs_valid, SW_M, |
| 1338 | PAIR_A, PAIR_A, buf); |
| 1339 | if (ret) |
| 1340 | goto out; |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 1341 | |
| 1342 | out: |
| 1343 | kfree(buf); |
| 1344 | return ret; |
| 1345 | } |
| 1346 | |
developer | 68f6e10 | 2022-11-22 17:35:00 +0800 | [diff] [blame] | 1347 | static int mt7981_phy_probe(struct phy_device *phydev) |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 1348 | { |
| 1349 | mt7981_phy_finetune(phydev); |
| 1350 | |
| 1351 | return mt798x_phy_calibration(phydev); |
| 1352 | } |
| 1353 | |
developer | 68f6e10 | 2022-11-22 17:35:00 +0800 | [diff] [blame] | 1354 | static int mt7988_phy_probe(struct phy_device *phydev) |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 1355 | { |
developer | 2302129 | 2022-10-21 19:10:10 +0800 | [diff] [blame] | 1356 | struct device_node *np; |
| 1357 | void __iomem *boottrap; |
| 1358 | u32 reg; |
| 1359 | int port; |
| 1360 | |
| 1361 | /* Setup LED polarity according to boottrap's polarity */ |
| 1362 | np = of_find_compatible_node(NULL, NULL, "mediatek,boottrap"); |
| 1363 | if (!np) |
| 1364 | return -ENOENT; |
| 1365 | boottrap = of_iomap(np, 0); |
| 1366 | if (!boottrap) |
| 1367 | return -ENOMEM; |
| 1368 | reg = readl(boottrap); |
| 1369 | port = phydev->mdio.addr; |
| 1370 | if ((port == GPHY_PORT0 && reg & BIT(8)) || |
| 1371 | (port == GPHY_PORT1 && reg & BIT(9)) || |
| 1372 | (port == GPHY_PORT2 && reg & BIT(10)) || |
| 1373 | (port == GPHY_PORT3 && reg & BIT(11))) { |
| 1374 | phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 1375 | MTK_PHY_LED0_ENABLE | MTK_PHY_LED0_ON_LINK10 | |
| 1376 | MTK_PHY_LED0_ON_LINK100 | |
| 1377 | MTK_PHY_LED0_ON_LINK1000); |
developer | 2302129 | 2022-10-21 19:10:10 +0800 | [diff] [blame] | 1378 | } else { |
| 1379 | phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 1380 | MTK_PHY_LED0_ENABLE | MTK_PHY_LED0_POLARITY | |
| 1381 | MTK_PHY_LED0_ON_LINK10 | |
| 1382 | MTK_PHY_LED0_ON_LINK100 | |
| 1383 | MTK_PHY_LED0_ON_LINK1000); |
developer | 2302129 | 2022-10-21 19:10:10 +0800 | [diff] [blame] | 1384 | } |
developer | 8bc5dca | 2022-10-24 17:15:12 +0800 | [diff] [blame] | 1385 | phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_BLINK_CTRL, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 1386 | MTK_PHY_LED0_1000TX | MTK_PHY_LED0_1000RX | |
| 1387 | MTK_PHY_LED0_100TX | MTK_PHY_LED0_100RX | |
| 1388 | MTK_PHY_LED0_10TX | MTK_PHY_LED0_10RX); |
developer | 2302129 | 2022-10-21 19:10:10 +0800 | [diff] [blame] | 1389 | |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 1390 | mt7988_phy_finetune(phydev); |
| 1391 | |
| 1392 | return mt798x_phy_calibration(phydev); |
| 1393 | } |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 1394 | #endif |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 1395 | |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 1396 | static struct phy_driver mtk_gephy_driver[] = { |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 1397 | { |
| 1398 | PHY_ID_MATCH_EXACT(0x03a29412), |
| 1399 | .name = "MediaTek MT7530 PHY", |
| 1400 | .config_init = mt7530_phy_config_init, |
| 1401 | /* Interrupts are handled by the switch, not the PHY |
| 1402 | * itself. |
| 1403 | */ |
| 1404 | .config_intr = genphy_no_config_intr, |
| 1405 | .handle_interrupt = genphy_no_ack_interrupt, |
| 1406 | .suspend = genphy_suspend, |
| 1407 | .resume = genphy_resume, |
| 1408 | .read_page = mtk_gephy_read_page, |
| 1409 | .write_page = mtk_gephy_write_page, |
| 1410 | }, |
| 1411 | { |
| 1412 | PHY_ID_MATCH_EXACT(0x03a29441), |
| 1413 | .name = "MediaTek MT7531 PHY", |
| 1414 | .config_init = mt7531_phy_config_init, |
| 1415 | /* Interrupts are handled by the switch, not the PHY |
| 1416 | * itself. |
| 1417 | */ |
| 1418 | .config_intr = genphy_no_config_intr, |
| 1419 | .handle_interrupt = genphy_no_ack_interrupt, |
| 1420 | .suspend = genphy_suspend, |
| 1421 | .resume = genphy_resume, |
| 1422 | .read_page = mtk_gephy_read_page, |
| 1423 | .write_page = mtk_gephy_write_page, |
| 1424 | }, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 1425 | #ifdef CONFIG_MEDIATEK_GE_PHY_SOC |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 1426 | { |
| 1427 | PHY_ID_MATCH_EXACT(0x03a29461), |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 1428 | .name = "MediaTek MT7981 PHY", |
developer | 68f6e10 | 2022-11-22 17:35:00 +0800 | [diff] [blame] | 1429 | .probe = mt7981_phy_probe, |
developer | f35532c | 2022-08-05 18:37:26 +0800 | [diff] [blame] | 1430 | .config_intr = genphy_no_config_intr, |
| 1431 | .handle_interrupt = genphy_no_ack_interrupt, |
| 1432 | .suspend = genphy_suspend, |
| 1433 | .resume = genphy_resume, |
| 1434 | .read_page = mtk_gephy_read_page, |
| 1435 | .write_page = mtk_gephy_write_page, |
| 1436 | }, |
| 1437 | { |
| 1438 | PHY_ID_MATCH_EXACT(0x03a29481), |
| 1439 | .name = "MediaTek MT7988 PHY", |
| 1440 | .probe = mt7988_phy_probe, |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 1441 | .config_intr = genphy_no_config_intr, |
| 1442 | .handle_interrupt = genphy_no_ack_interrupt, |
| 1443 | .suspend = genphy_suspend, |
| 1444 | .resume = genphy_resume, |
| 1445 | .read_page = mtk_gephy_read_page, |
| 1446 | .write_page = mtk_gephy_write_page, |
| 1447 | }, |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 1448 | #endif |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 1449 | }; |
| 1450 | |
| 1451 | module_phy_driver(mtk_gephy_driver); |
| 1452 | |
| 1453 | static struct mdio_device_id __maybe_unused mtk_gephy_tbl[] = { |
| 1454 | { PHY_ID_MATCH_VENDOR(0x03a29400) }, |
| 1455 | { } |
| 1456 | }; |
| 1457 | |
| 1458 | MODULE_DESCRIPTION("MediaTek Gigabit Ethernet PHY driver"); |
developer | 2149cd9 | 2023-03-10 19:01:41 +0800 | [diff] [blame^] | 1459 | MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>"); |
| 1460 | MODULE_AUTHOR("SkyLake Huang <SkyLake.Huang@mediatek.com>"); |
developer | c50c235 | 2021-12-01 10:45:35 +0800 | [diff] [blame] | 1461 | MODULE_AUTHOR("DENG, Qingfang <dqfext@gmail.com>"); |
| 1462 | MODULE_LICENSE("GPL"); |
| 1463 | |
| 1464 | MODULE_DEVICE_TABLE(mdio, mtk_gephy_tbl); |