[][kernel][mt7988][eth][phy: mediatek-ge: Add hardware v3 enhancement]
[Description]
Add hardware v3 enhancement:
* Disable LDO pump (one of LDO functions)
* Adjust RXADC LDO level.
* TxClkOffset=2
* R50-2
* ResetSyncOffset=5
* Restore VgaDecRate settings. (default=9)
[Release-log]
N/A
Change-Id: Idb95bd51777f0a01b20a2e58e07f3ae11409fe3f
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/6947356
diff --git a/target/linux/mediatek/files-5.4/drivers/net/phy/mediatek-ge.c b/target/linux/mediatek/files-5.4/drivers/net/phy/mediatek-ge.c
index 796f1cb..effb78a 100644
--- a/target/linux/mediatek/files-5.4/drivers/net/phy/mediatek-ge.c
+++ b/target/linux/mediatek/files-5.4/drivers/net/phy/mediatek-ge.c
@@ -18,7 +18,11 @@
#define MTK_PHY_PAGE_EXTENDED 0x0001
#define MTK_PHY_PAGE_EXTENDED_2 0x0002
#define MTK_PHY_PAGE_EXTENDED_3 0x0003
+
#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
+#define MTK_PHY_ANARG_RG (0x10)
+#define MTK_PHY_TCLKOFFSET_MASK GENMASK(12, 8)
+
#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
/* Registers on MDIO_MMD_VEND1 */
@@ -87,6 +91,8 @@
#define MTK_PHY_DA_RX_PSBN_GBE_MASK GENMASK(6, 4)
#define MTK_PHY_DA_RX_PSBN_LP_MASK GENMASK(2, 0)
+#define MTK_PHY_LDO_CTRL (0xd6)
+
#define MTK_PHY_RG_ANA_CAL_RG0 (0xdb)
#define MTK_PHY_RG_CAL_CKINV BIT(12)
#define MTK_PHY_RG_ANA_CALEN BIT(8)
@@ -182,6 +188,9 @@
#define MTK_PHY_RG_DEV1E_REG27D (0x27d)
#define MTK_PHY_VGASTATE_FFE_THR_ST2_MASK GENMASK(4, 0)
+#define MTK_PHY_LDO_PUMP_EN_PAIRAB (0x502)
+#define MTK_PHY_LDO_PUMP_EN_PAIRCD (0x503)
+
#define MTK_PHY_RG_DEV1E_REG53D (0x53d)
#define MTK_PHY_DA_TX_R50_A_NORMAL_MASK GENMASK(13, 8)
#define MTK_PHY_DA_TX_R50_A_TBT_MASK GENMASK(5, 0)
@@ -622,7 +631,7 @@
switch(phydev->drv->phy_id) {
case 0x03a29481:
{
- int tmp[16] = { -1, -1, -1, -1 };
+ int tmp[16] = { -2, -2, -2, -2 };
memcpy(bias, (const void *)tmp, sizeof(bias));
break;
}
@@ -1105,16 +1114,17 @@
__phy_write(phydev, 0x12, 0x55);
__phy_write(phydev, 0x10, 0x8ec0);
- /* ResetSyncOffset = 6 */
- __phy_write(phydev, 0x11, 0x600);
+ /* ResetSyncOffset = 5 */
+ __phy_write(phydev, 0x11, 0x500);
__phy_write(phydev, 0x12, 0x0);
__phy_write(phydev, 0x10, 0x8fc0);
- /* VgaDecRate = 1 */
- __phy_write(phydev, 0x11, 0x4c2a);
- __phy_write(phydev, 0x12, 0x3e);
- __phy_write(phydev, 0x10, 0x8fa4);
+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_2A30);
+ /* TxClkOffset = 2 */
+ phy_modify(phydev, MTK_PHY_ANARG_RG, MTK_PHY_TCLKOFFSET_MASK,
+ FIELD_PREP(MTK_PHY_TCLKOFFSET_MASK, 0x2));
+ /* Always restore to page0 if page select is called */
phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
/* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9*/
@@ -1151,6 +1161,13 @@
phy_write_mmd(phydev, MDIO_MMD_VEND2, i, 0x2219);
phy_write_mmd(phydev, MDIO_MMD_VEND2, i+1, 0x23);
}
+
+ /* Disable LDO pump */
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, 0x0);
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, 0x0);
+
+ /* Adjust LDO output voltage */
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_CTRL, 0x2222);
}
static int mt798x_phy_calibration(struct phy_device *phydev)