developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 |
| 2 | * |
| 3 | * Copyright (c) 2022 MediaTek Inc. |
| 4 | * Author: Henry Yen <henry.yen@mediatek.com> |
| 5 | */ |
| 6 | |
| 7 | #include <linux/mfd/syscon.h> |
| 8 | #include <linux/of.h> |
| 9 | #include <linux/regmap.h> |
| 10 | #include "mtk_eth_soc.h" |
| 11 | |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 12 | static struct mtk_usxgmii_pcs *pcs_to_mtk_usxgmii_pcs(struct phylink_pcs *pcs) |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 13 | { |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 14 | return container_of(pcs, struct mtk_usxgmii_pcs, pcs); |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 15 | } |
| 16 | |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 17 | int mtk_usxgmii_xfi_pextp_init(struct mtk_usxgmii *ss, struct device_node *r) |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 18 | { |
| 19 | struct device_node *np; |
| 20 | int i; |
| 21 | |
| 22 | for (i = 0; i < MTK_MAX_DEVS; i++) { |
| 23 | np = of_parse_phandle(r, "mediatek,xfi_pextp", i); |
| 24 | if (!np) |
| 25 | break; |
| 26 | |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 27 | ss->pcs[i].regmap_pextp = syscon_node_to_regmap(np); |
| 28 | if (IS_ERR(ss->pcs[i].regmap_pextp)) |
| 29 | return PTR_ERR(ss->pcs[i].regmap_pextp); |
| 30 | |
| 31 | of_node_put(np); |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 32 | } |
| 33 | |
| 34 | return 0; |
| 35 | } |
| 36 | |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 37 | int mtk_usxgmii_xfi_pll_init(struct mtk_usxgmii *ss, struct device_node *r) |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 38 | { |
| 39 | struct device_node *np; |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 40 | int i; |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 41 | |
| 42 | np = of_parse_phandle(r, "mediatek,xfi_pll", 0); |
| 43 | if (!np) |
| 44 | return -1; |
| 45 | |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 46 | for (i = 0; i < MTK_MAX_DEVS; i++) { |
| 47 | ss->pll = syscon_node_to_regmap(np); |
| 48 | if (IS_ERR(ss->pll)) |
| 49 | return PTR_ERR(ss->pll); |
| 50 | } |
| 51 | |
| 52 | of_node_put(np); |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 53 | |
| 54 | return 0; |
| 55 | } |
| 56 | |
| 57 | int mtk_toprgu_init(struct mtk_eth *eth, struct device_node *r) |
| 58 | { |
| 59 | struct device_node *np; |
| 60 | |
| 61 | np = of_parse_phandle(r, "mediatek,toprgu", 0); |
| 62 | if (!np) |
| 63 | return -1; |
| 64 | |
| 65 | eth->toprgu = syscon_node_to_regmap(np); |
| 66 | if (IS_ERR(eth->toprgu)) |
| 67 | return PTR_ERR(eth->toprgu); |
| 68 | |
| 69 | return 0; |
| 70 | } |
| 71 | |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 72 | static int mtk_usxgmii_xfi_pll_enable(struct mtk_usxgmii *ss) |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 73 | { |
| 74 | u32 val = 0; |
| 75 | |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 76 | if (!ss->pll) |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 77 | return -EINVAL; |
| 78 | |
| 79 | /* Add software workaround for USXGMII PLL TCL issue */ |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 80 | regmap_write(ss->pll, XFI_PLL_ANA_GLB8, RG_XFI_PLL_ANA_SWWA); |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 81 | |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 82 | regmap_read(ss->pll, XFI_PLL_DIG_GLB8, &val); |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 83 | val |= RG_XFI_PLL_EN; |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 84 | regmap_write(ss->pll, XFI_PLL_DIG_GLB8, val); |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 85 | |
| 86 | return 0; |
| 87 | } |
| 88 | |
| 89 | int mtk_mac2xgmii_id(struct mtk_eth *eth, int mac_id) |
| 90 | { |
| 91 | u32 xgmii_id = mac_id; |
| 92 | |
| 93 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) { |
| 94 | switch (mac_id) { |
| 95 | case MTK_GMAC1_ID: |
| 96 | case MTK_GMAC2_ID: |
| 97 | xgmii_id = 1; |
| 98 | break; |
| 99 | case MTK_GMAC3_ID: |
| 100 | xgmii_id = 0; |
| 101 | break; |
| 102 | default: |
| 103 | pr_info("[%s] Warning: get illegal mac_id=%d !=!!!\n", |
| 104 | __func__, mac_id); |
| 105 | } |
| 106 | } |
| 107 | |
| 108 | return xgmii_id; |
| 109 | } |
| 110 | |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 111 | int mtk_xgmii2mac_id(struct mtk_eth *eth, int xgmii_id) |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 112 | { |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 113 | u32 mac_id = xgmii_id; |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 114 | |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 115 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) { |
| 116 | switch (xgmii_id) { |
| 117 | case 0: |
| 118 | mac_id = 2; |
| 119 | break; |
| 120 | case 1: |
| 121 | mac_id = 1; |
| 122 | break; |
| 123 | default: |
| 124 | pr_info("[%s] Warning: get illegal xgmii_id=%d !=!!!\n", |
| 125 | __func__, xgmii_id); |
| 126 | } |
| 127 | } |
| 128 | |
| 129 | return mac_id; |
| 130 | } |
| 131 | |
| 132 | int mtk_usxgmii_setup_phya_an_10000(struct mtk_usxgmii_pcs *mpcs) |
| 133 | { |
| 134 | if (!mpcs->regmap || !mpcs->regmap_pextp) |
| 135 | return -EINVAL; |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 136 | |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 137 | regmap_update_bits(mpcs->regmap, 0x810, GENMASK(31, 0), |
| 138 | 0x000FFE6D); |
| 139 | regmap_update_bits(mpcs->regmap, 0x818, GENMASK(31, 0), |
| 140 | 0x07B1EC7B); |
| 141 | regmap_update_bits(mpcs->regmap, 0x80C, GENMASK(31, 0), |
| 142 | 0x30000000); |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 143 | ndelay(1020); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 144 | regmap_update_bits(mpcs->regmap, 0x80C, GENMASK(31, 0), |
| 145 | 0x10000000); |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 146 | ndelay(1020); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 147 | regmap_update_bits(mpcs->regmap, 0x80C, GENMASK(31, 0), |
| 148 | 0x00000000); |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 149 | |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 150 | regmap_update_bits(mpcs->regmap_pextp, 0x9024, GENMASK(31, 0), |
| 151 | 0x00C9071C); |
| 152 | regmap_update_bits(mpcs->regmap_pextp, 0x2020, GENMASK(31, 0), |
| 153 | 0xAA8585AA); |
| 154 | regmap_update_bits(mpcs->regmap_pextp, 0x2030, GENMASK(31, 0), |
| 155 | 0x0C020707); |
| 156 | regmap_update_bits(mpcs->regmap_pextp, 0x2034, GENMASK(31, 0), |
| 157 | 0x0E050F0F); |
| 158 | regmap_update_bits(mpcs->regmap_pextp, 0x2040, GENMASK(31, 0), |
| 159 | 0x00140032); |
| 160 | regmap_update_bits(mpcs->regmap_pextp, 0x50F0, GENMASK(31, 0), |
| 161 | 0x00C014AA); |
| 162 | regmap_update_bits(mpcs->regmap_pextp, 0x50E0, GENMASK(31, 0), |
| 163 | 0x3777C12B); |
| 164 | regmap_update_bits(mpcs->regmap_pextp, 0x506C, GENMASK(31, 0), |
| 165 | 0x005F9CFF); |
| 166 | regmap_update_bits(mpcs->regmap_pextp, 0x5070, GENMASK(31, 0), |
| 167 | 0x9D9DFAFA); |
| 168 | regmap_update_bits(mpcs->regmap_pextp, 0x5074, GENMASK(31, 0), |
| 169 | 0x27273F3F); |
| 170 | regmap_update_bits(mpcs->regmap_pextp, 0x5078, GENMASK(31, 0), |
| 171 | 0xA7883C68); |
| 172 | regmap_update_bits(mpcs->regmap_pextp, 0x507C, GENMASK(31, 0), |
| 173 | 0x11661166); |
| 174 | regmap_update_bits(mpcs->regmap_pextp, 0x5080, GENMASK(31, 0), |
| 175 | 0x0E000AAF); |
| 176 | regmap_update_bits(mpcs->regmap_pextp, 0x5084, GENMASK(31, 0), |
| 177 | 0x08080D0D); |
| 178 | regmap_update_bits(mpcs->regmap_pextp, 0x5088, GENMASK(31, 0), |
| 179 | 0x02030909); |
| 180 | regmap_update_bits(mpcs->regmap_pextp, 0x50E4, GENMASK(31, 0), |
| 181 | 0x0C0C0000); |
| 182 | regmap_update_bits(mpcs->regmap_pextp, 0x50E8, GENMASK(31, 0), |
| 183 | 0x04040000); |
| 184 | regmap_update_bits(mpcs->regmap_pextp, 0x50EC, GENMASK(31, 0), |
| 185 | 0x0F0F0C06); |
| 186 | regmap_update_bits(mpcs->regmap_pextp, 0x50A8, GENMASK(31, 0), |
| 187 | 0x506E8C8C); |
| 188 | regmap_update_bits(mpcs->regmap_pextp, 0x6004, GENMASK(31, 0), |
| 189 | 0x18190000); |
| 190 | regmap_update_bits(mpcs->regmap_pextp, 0x00F8, GENMASK(31, 0), |
| 191 | 0x01423342); |
| 192 | regmap_update_bits(mpcs->regmap_pextp, 0x00F4, GENMASK(31, 0), |
| 193 | 0x80201F20); |
| 194 | regmap_update_bits(mpcs->regmap_pextp, 0x0030, GENMASK(31, 0), |
| 195 | 0x00050C00); |
| 196 | regmap_update_bits(mpcs->regmap_pextp, 0x0070, GENMASK(31, 0), |
| 197 | 0x02002800); |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 198 | ndelay(1020); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 199 | regmap_update_bits(mpcs->regmap_pextp, 0x30B0, GENMASK(31, 0), |
| 200 | 0x00000020); |
| 201 | regmap_update_bits(mpcs->regmap_pextp, 0x3028, GENMASK(31, 0), |
| 202 | 0x00008A01); |
| 203 | regmap_update_bits(mpcs->regmap_pextp, 0x302C, GENMASK(31, 0), |
| 204 | 0x0000A884); |
| 205 | regmap_update_bits(mpcs->regmap_pextp, 0x3024, GENMASK(31, 0), |
| 206 | 0x00083002); |
| 207 | regmap_update_bits(mpcs->regmap_pextp, 0x3010, GENMASK(31, 0), |
| 208 | 0x00022220); |
| 209 | regmap_update_bits(mpcs->regmap_pextp, 0x5064, GENMASK(31, 0), |
| 210 | 0x0F020A01); |
| 211 | regmap_update_bits(mpcs->regmap_pextp, 0x50B4, GENMASK(31, 0), |
| 212 | 0x06100600); |
| 213 | regmap_update_bits(mpcs->regmap_pextp, 0x3048, GENMASK(31, 0), |
| 214 | 0x40704000); |
| 215 | regmap_update_bits(mpcs->regmap_pextp, 0x3050, GENMASK(31, 0), |
| 216 | 0xA8000000); |
| 217 | regmap_update_bits(mpcs->regmap_pextp, 0x3054, GENMASK(31, 0), |
| 218 | 0x000000AA); |
| 219 | regmap_update_bits(mpcs->regmap_pextp, 0x306C, GENMASK(31, 0), |
| 220 | 0x00000F00); |
| 221 | regmap_update_bits(mpcs->regmap_pextp, 0xA060, GENMASK(31, 0), |
| 222 | 0x00040000); |
| 223 | regmap_update_bits(mpcs->regmap_pextp, 0x90D0, GENMASK(31, 0), |
| 224 | 0x00000001); |
| 225 | regmap_update_bits(mpcs->regmap_pextp, 0x0070, GENMASK(31, 0), |
| 226 | 0x0200E800); |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 227 | udelay(150); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 228 | regmap_update_bits(mpcs->regmap_pextp, 0x0070, GENMASK(31, 0), |
| 229 | 0x0200C111); |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 230 | ndelay(1020); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 231 | regmap_update_bits(mpcs->regmap_pextp, 0x0070, GENMASK(31, 0), |
| 232 | 0x0200C101); |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 233 | udelay(15); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 234 | regmap_update_bits(mpcs->regmap_pextp, 0x0070, GENMASK(31, 0), |
| 235 | 0x0202C111); |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 236 | ndelay(1020); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 237 | regmap_update_bits(mpcs->regmap_pextp, 0x0070, GENMASK(31, 0), |
| 238 | 0x0202C101); |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 239 | udelay(100); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 240 | regmap_update_bits(mpcs->regmap_pextp, 0x30B0, GENMASK(31, 0), |
| 241 | 0x00000030); |
| 242 | regmap_update_bits(mpcs->regmap_pextp, 0x00F4, GENMASK(31, 0), |
| 243 | 0x80201F00); |
| 244 | regmap_update_bits(mpcs->regmap_pextp, 0x3040, GENMASK(31, 0), |
| 245 | 0x30000000); |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 246 | udelay(400); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 247 | |
| 248 | return 0; |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 249 | } |
| 250 | |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 251 | int mtk_usxgmii_setup_phya_force_5000(struct mtk_usxgmii_pcs *mpcs) |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 252 | { |
| 253 | unsigned int val; |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 254 | |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 255 | if (!mpcs->regmap || !mpcs->regmap_pextp) |
| 256 | return -EINVAL; |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 257 | |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 258 | /* Setup USXGMII speed */ |
| 259 | val = FIELD_PREP(RG_XFI_RX_MODE, RG_XFI_RX_MODE_5G) | |
| 260 | FIELD_PREP(RG_XFI_TX_MODE, RG_XFI_TX_MODE_5G); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 261 | regmap_write(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1, val); |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 262 | |
| 263 | /* Disable USXGMII AN mode */ |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 264 | regmap_read(mpcs->regmap, RG_PCS_AN_CTRL0, &val); |
| 265 | val &= ~USXGMII_AN_ENABLE; |
| 266 | regmap_write(mpcs->regmap, RG_PCS_AN_CTRL0, val); |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 267 | |
| 268 | /* Gated USXGMII */ |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 269 | regmap_read(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1, &val); |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 270 | val |= RG_MAC_CK_GATED; |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 271 | regmap_write(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1, val); |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 272 | |
| 273 | ndelay(1020); |
| 274 | |
| 275 | /* USXGMII force mode setting */ |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 276 | regmap_read(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1, &val); |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 277 | val |= RG_USXGMII_RATE_UPDATE_MODE; |
| 278 | val |= RG_IF_FORCE_EN; |
| 279 | val |= FIELD_PREP(RG_RATE_ADAPT_MODE, RG_RATE_ADAPT_MODE_X1); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 280 | regmap_write(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1, val); |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 281 | |
| 282 | /* Un-gated USXGMII */ |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 283 | regmap_read(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1, &val); |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 284 | val &= ~RG_MAC_CK_GATED; |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 285 | regmap_write(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1, val); |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 286 | |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 287 | ndelay(1020); |
| 288 | |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 289 | regmap_update_bits(mpcs->regmap_pextp, 0x9024, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 290 | 0x00D9071C); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 291 | regmap_update_bits(mpcs->regmap_pextp, 0x2020, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 292 | 0xAAA5A5AA); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 293 | regmap_update_bits(mpcs->regmap_pextp, 0x2030, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 294 | 0x0C020707); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 295 | regmap_update_bits(mpcs->regmap_pextp, 0x2034, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 296 | 0x0E050F0F); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 297 | regmap_update_bits(mpcs->regmap_pextp, 0x2040, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 298 | 0x00140032); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 299 | regmap_update_bits(mpcs->regmap_pextp, 0x50F0, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 300 | 0x00C018AA); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 301 | regmap_update_bits(mpcs->regmap_pextp, 0x50E0, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 302 | 0x3777812B); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 303 | regmap_update_bits(mpcs->regmap_pextp, 0x506C, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 304 | 0x005C9CFF); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 305 | regmap_update_bits(mpcs->regmap_pextp, 0x5070, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 306 | 0x9DFAFAFA); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 307 | regmap_update_bits(mpcs->regmap_pextp, 0x5074, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 308 | 0x273F3F3F); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 309 | regmap_update_bits(mpcs->regmap_pextp, 0x5078, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 310 | 0xA8883868); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 311 | regmap_update_bits(mpcs->regmap_pextp, 0x507C, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 312 | 0x14661466); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 313 | regmap_update_bits(mpcs->regmap_pextp, 0x5080, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 314 | 0x0E001ABF); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 315 | regmap_update_bits(mpcs->regmap_pextp, 0x5084, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 316 | 0x080B0D0D); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 317 | regmap_update_bits(mpcs->regmap_pextp, 0x5088, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 318 | 0x02050909); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 319 | regmap_update_bits(mpcs->regmap_pextp, 0x50E4, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 320 | 0x0C000000); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 321 | regmap_update_bits(mpcs->regmap_pextp, 0x50E8, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 322 | 0x04000000); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 323 | regmap_update_bits(mpcs->regmap_pextp, 0x50EC, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 324 | 0x0F0F0C06); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 325 | regmap_update_bits(mpcs->regmap_pextp, 0x50A8, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 326 | 0x50808C8C); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 327 | regmap_update_bits(mpcs->regmap_pextp, 0x6004, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 328 | 0x18000000); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 329 | regmap_update_bits(mpcs->regmap_pextp, 0x00F8, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 330 | 0x00A132A1); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 331 | regmap_update_bits(mpcs->regmap_pextp, 0x00F4, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 332 | 0x80201F20); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 333 | regmap_update_bits(mpcs->regmap_pextp, 0x0030, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 334 | 0x00050C00); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 335 | regmap_update_bits(mpcs->regmap_pextp, 0x0070, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 336 | 0x02002800); |
| 337 | ndelay(1020); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 338 | regmap_update_bits(mpcs->regmap_pextp, 0x30B0, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 339 | 0x00000020); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 340 | regmap_update_bits(mpcs->regmap_pextp, 0x3028, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 341 | 0x00008A01); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 342 | regmap_update_bits(mpcs->regmap_pextp, 0x302C, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 343 | 0x0000A884); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 344 | regmap_update_bits(mpcs->regmap_pextp, 0x3024, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 345 | 0x00083002); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 346 | regmap_update_bits(mpcs->regmap_pextp, 0x3010, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 347 | 0x00022220); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 348 | regmap_update_bits(mpcs->regmap_pextp, 0x5064, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 349 | 0x0F020A01); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 350 | regmap_update_bits(mpcs->regmap_pextp, 0x50B4, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 351 | 0x06100600); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 352 | regmap_update_bits(mpcs->regmap_pextp, 0x3048, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 353 | 0x40704000); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 354 | regmap_update_bits(mpcs->regmap_pextp, 0x3050, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 355 | 0xA8000000); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 356 | regmap_update_bits(mpcs->regmap_pextp, 0x3054, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 357 | 0x000000AA); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 358 | regmap_update_bits(mpcs->regmap_pextp, 0x306C, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 359 | 0x00000F00); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 360 | regmap_update_bits(mpcs->regmap_pextp, 0xA060, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 361 | 0x00040000); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 362 | regmap_update_bits(mpcs->regmap_pextp, 0x90D0, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 363 | 0x00000003); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 364 | regmap_update_bits(mpcs->regmap_pextp, 0x0070, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 365 | 0x0200E800); |
| 366 | udelay(150); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 367 | regmap_update_bits(mpcs->regmap_pextp, 0x0070, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 368 | 0x0200C111); |
| 369 | ndelay(1020); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 370 | regmap_update_bits(mpcs->regmap_pextp, 0x0070, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 371 | 0x0200C101); |
| 372 | udelay(15); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 373 | regmap_update_bits(mpcs->regmap_pextp, 0x0070, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 374 | 0x0202C111); |
| 375 | ndelay(1020); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 376 | regmap_update_bits(mpcs->regmap_pextp, 0x0070, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 377 | 0x0202C101); |
| 378 | udelay(100); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 379 | regmap_update_bits(mpcs->regmap_pextp, 0x30B0, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 380 | 0x00000030); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 381 | regmap_update_bits(mpcs->regmap_pextp, 0x00F4, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 382 | 0x80201F00); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 383 | regmap_update_bits(mpcs->regmap_pextp, 0x3040, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 384 | 0x30000000); |
| 385 | udelay(400); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 386 | |
| 387 | return 0; |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 388 | } |
| 389 | |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 390 | int mtk_usxgmii_setup_phya_force_10000(struct mtk_usxgmii_pcs *mpcs) |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 391 | { |
| 392 | unsigned int val; |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 393 | |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 394 | if (!mpcs->regmap || !mpcs->regmap_pextp) |
| 395 | return -EINVAL; |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 396 | |
| 397 | /* Setup USXGMII speed */ |
| 398 | val = FIELD_PREP(RG_XFI_RX_MODE, RG_XFI_RX_MODE_10G) | |
| 399 | FIELD_PREP(RG_XFI_TX_MODE, RG_XFI_TX_MODE_10G); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 400 | regmap_write(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1, val); |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 401 | |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 402 | /* Disable USXGMII AN mode */ |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 403 | regmap_read(mpcs->regmap, RG_PCS_AN_CTRL0, &val); |
| 404 | val &= ~USXGMII_AN_ENABLE; |
| 405 | regmap_write(mpcs->regmap, RG_PCS_AN_CTRL0, val); |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 406 | |
| 407 | /* Gated USXGMII */ |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 408 | regmap_read(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1, &val); |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 409 | val |= RG_MAC_CK_GATED; |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 410 | regmap_write(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1, val); |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 411 | |
| 412 | ndelay(1020); |
| 413 | |
| 414 | /* USXGMII force mode setting */ |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 415 | regmap_read(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1, &val); |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 416 | val |= RG_USXGMII_RATE_UPDATE_MODE; |
| 417 | val |= RG_IF_FORCE_EN; |
| 418 | val |= FIELD_PREP(RG_RATE_ADAPT_MODE, RG_RATE_ADAPT_MODE_X1); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 419 | regmap_write(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1, val); |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 420 | |
| 421 | /* Un-gated USXGMII */ |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 422 | regmap_read(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1, &val); |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 423 | val &= ~RG_MAC_CK_GATED; |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 424 | regmap_write(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1, val); |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 425 | |
| 426 | ndelay(1020); |
| 427 | |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 428 | regmap_update_bits(mpcs->regmap_pextp, 0x9024, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 429 | 0x00C9071C); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 430 | regmap_update_bits(mpcs->regmap_pextp, 0x2020, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 431 | 0xAA8585AA); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 432 | regmap_update_bits(mpcs->regmap_pextp, 0x2030, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 433 | 0x0C020707); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 434 | regmap_update_bits(mpcs->regmap_pextp, 0x2034, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 435 | 0x0E050F0F); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 436 | regmap_update_bits(mpcs->regmap_pextp, 0x2040, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 437 | 0x00140032); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 438 | regmap_update_bits(mpcs->regmap_pextp, 0x50F0, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 439 | 0x00C014AA); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 440 | regmap_update_bits(mpcs->regmap_pextp, 0x50E0, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 441 | 0x3777C12B); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 442 | regmap_update_bits(mpcs->regmap_pextp, 0x506C, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 443 | 0x005F9CFF); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 444 | regmap_update_bits(mpcs->regmap_pextp, 0x5070, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 445 | 0x9D9DFAFA); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 446 | regmap_update_bits(mpcs->regmap_pextp, 0x5074, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 447 | 0x27273F3F); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 448 | regmap_update_bits(mpcs->regmap_pextp, 0x5078, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 449 | 0xA7883C68); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 450 | regmap_update_bits(mpcs->regmap_pextp, 0x507C, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 451 | 0x11661166); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 452 | regmap_update_bits(mpcs->regmap_pextp, 0x5080, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 453 | 0x0E000AAF); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 454 | regmap_update_bits(mpcs->regmap_pextp, 0x5084, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 455 | 0x08080D0D); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 456 | regmap_update_bits(mpcs->regmap_pextp, 0x5088, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 457 | 0x02030909); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 458 | regmap_update_bits(mpcs->regmap_pextp, 0x50E4, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 459 | 0x0C0C0000); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 460 | regmap_update_bits(mpcs->regmap_pextp, 0x50E8, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 461 | 0x04040000); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 462 | regmap_update_bits(mpcs->regmap_pextp, 0x50EC, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 463 | 0x0F0F0C06); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 464 | regmap_update_bits(mpcs->regmap_pextp, 0x50A8, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 465 | 0x506E8C8C); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 466 | regmap_update_bits(mpcs->regmap_pextp, 0x6004, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 467 | 0x18190000); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 468 | regmap_update_bits(mpcs->regmap_pextp, 0x00F8, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 469 | 0x01423342); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 470 | regmap_update_bits(mpcs->regmap_pextp, 0x00F4, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 471 | 0x80201F20); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 472 | regmap_update_bits(mpcs->regmap_pextp, 0x0030, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 473 | 0x00050C00); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 474 | regmap_update_bits(mpcs->regmap_pextp, 0x0070, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 475 | 0x02002800); |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 476 | ndelay(1020); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 477 | regmap_update_bits(mpcs->regmap_pextp, 0x30B0, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 478 | 0x00000020); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 479 | regmap_update_bits(mpcs->regmap_pextp, 0x3028, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 480 | 0x00008A01); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 481 | regmap_update_bits(mpcs->regmap_pextp, 0x302C, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 482 | 0x0000A884); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 483 | regmap_update_bits(mpcs->regmap_pextp, 0x3024, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 484 | 0x00083002); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 485 | regmap_update_bits(mpcs->regmap_pextp, 0x3010, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 486 | 0x00022220); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 487 | regmap_update_bits(mpcs->regmap_pextp, 0x5064, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 488 | 0x0F020A01); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 489 | regmap_update_bits(mpcs->regmap_pextp, 0x50B4, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 490 | 0x06100600); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 491 | regmap_update_bits(mpcs->regmap_pextp, 0x3048, GENMASK(31, 0), |
developer | a500d94 | 2023-05-19 13:47:40 +0800 | [diff] [blame^] | 492 | 0x47684100); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 493 | regmap_update_bits(mpcs->regmap_pextp, 0x3050, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 494 | 0x00000000); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 495 | regmap_update_bits(mpcs->regmap_pextp, 0x3054, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 496 | 0x00000000); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 497 | regmap_update_bits(mpcs->regmap_pextp, 0x306C, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 498 | 0x00000F00); |
developer | a500d94 | 2023-05-19 13:47:40 +0800 | [diff] [blame^] | 499 | if (mpcs->id == 0) |
| 500 | regmap_update_bits(mpcs->regmap_pextp, 0xA008, GENMASK(31, 0), |
| 501 | 0x0007B400); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 502 | regmap_update_bits(mpcs->regmap_pextp, 0xA060, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 503 | 0x00040000); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 504 | regmap_update_bits(mpcs->regmap_pextp, 0x90D0, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 505 | 0x00000001); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 506 | regmap_update_bits(mpcs->regmap_pextp, 0x0070, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 507 | 0x0200E800); |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 508 | udelay(150); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 509 | regmap_update_bits(mpcs->regmap_pextp, 0x0070, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 510 | 0x0200C111); |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 511 | ndelay(1020); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 512 | regmap_update_bits(mpcs->regmap_pextp, 0x0070, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 513 | 0x0200C101); |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 514 | udelay(15); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 515 | regmap_update_bits(mpcs->regmap_pextp, 0x0070, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 516 | 0x0202C111); |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 517 | ndelay(1020); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 518 | regmap_update_bits(mpcs->regmap_pextp, 0x0070, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 519 | 0x0202C101); |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 520 | udelay(100); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 521 | regmap_update_bits(mpcs->regmap_pextp, 0x30B0, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 522 | 0x00000030); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 523 | regmap_update_bits(mpcs->regmap_pextp, 0x00F4, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 524 | 0x80201F00); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 525 | regmap_update_bits(mpcs->regmap_pextp, 0x3040, GENMASK(31, 0), |
developer | cfa104b | 2023-01-11 17:40:41 +0800 | [diff] [blame] | 526 | 0x30000000); |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 527 | udelay(400); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 528 | |
| 529 | return 0; |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 530 | } |
| 531 | |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 532 | void mtk_usxgmii_reset(struct mtk_eth *eth, int id) |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 533 | { |
developer | 6aa0016 | 2023-03-20 11:56:51 +0800 | [diff] [blame] | 534 | u32 val = 0; |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 535 | |
developer | 8b6f240 | 2022-11-28 13:42:34 +0800 | [diff] [blame] | 536 | if (id >= MTK_MAX_DEVS || !eth->toprgu) |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 537 | return; |
| 538 | |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 539 | switch (id) { |
| 540 | case 0: |
developer | 6aa0016 | 2023-03-20 11:56:51 +0800 | [diff] [blame] | 541 | /* Enable software reset */ |
| 542 | regmap_read(eth->toprgu, TOPRGU_SWSYSRST_EN, &val); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 543 | val |= SWSYSRST_XFI_PEXPT0_GRST | |
| 544 | SWSYSRST_XFI0_GRST; |
developer | 6aa0016 | 2023-03-20 11:56:51 +0800 | [diff] [blame] | 545 | regmap_write(eth->toprgu, TOPRGU_SWSYSRST_EN, val); |
| 546 | |
| 547 | /* Assert USXGMII reset */ |
| 548 | regmap_read(eth->toprgu, TOPRGU_SWSYSRST, &val); |
| 549 | val |= FIELD_PREP(SWSYSRST_UNLOCK_KEY, 0x88) | |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 550 | SWSYSRST_XFI_PEXPT0_GRST | |
| 551 | SWSYSRST_XFI0_GRST; |
developer | 6aa0016 | 2023-03-20 11:56:51 +0800 | [diff] [blame] | 552 | regmap_write(eth->toprgu, TOPRGU_SWSYSRST, val); |
| 553 | |
| 554 | udelay(100); |
| 555 | |
| 556 | /* De-assert USXGMII reset */ |
| 557 | regmap_read(eth->toprgu, TOPRGU_SWSYSRST, &val); |
| 558 | val |= FIELD_PREP(SWSYSRST_UNLOCK_KEY, 0x88); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 559 | val &= ~(SWSYSRST_XFI_PEXPT0_GRST | |
| 560 | SWSYSRST_XFI0_GRST); |
developer | 6aa0016 | 2023-03-20 11:56:51 +0800 | [diff] [blame] | 561 | regmap_write(eth->toprgu, TOPRGU_SWSYSRST, val); |
| 562 | |
| 563 | /* Disable software reset */ |
| 564 | regmap_read(eth->toprgu, TOPRGU_SWSYSRST_EN, &val); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 565 | val &= ~(SWSYSRST_XFI_PEXPT0_GRST | |
| 566 | SWSYSRST_XFI0_GRST); |
developer | 6aa0016 | 2023-03-20 11:56:51 +0800 | [diff] [blame] | 567 | regmap_write(eth->toprgu, TOPRGU_SWSYSRST_EN, val); |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 568 | break; |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 569 | case 1: |
developer | 6aa0016 | 2023-03-20 11:56:51 +0800 | [diff] [blame] | 570 | /* Enable software reset */ |
| 571 | regmap_read(eth->toprgu, TOPRGU_SWSYSRST_EN, &val); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 572 | val |= SWSYSRST_XFI_PEXPT1_GRST | |
| 573 | SWSYSRST_XFI1_GRST; |
developer | 6aa0016 | 2023-03-20 11:56:51 +0800 | [diff] [blame] | 574 | regmap_write(eth->toprgu, TOPRGU_SWSYSRST_EN, val); |
| 575 | |
| 576 | /* Assert USXGMII reset */ |
| 577 | regmap_read(eth->toprgu, TOPRGU_SWSYSRST, &val); |
| 578 | val |= FIELD_PREP(SWSYSRST_UNLOCK_KEY, 0x88) | |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 579 | SWSYSRST_XFI_PEXPT1_GRST | |
| 580 | SWSYSRST_XFI1_GRST; |
developer | 6aa0016 | 2023-03-20 11:56:51 +0800 | [diff] [blame] | 581 | regmap_write(eth->toprgu, TOPRGU_SWSYSRST, val); |
| 582 | |
| 583 | udelay(100); |
| 584 | |
| 585 | /* De-assert USXGMII reset */ |
| 586 | regmap_read(eth->toprgu, TOPRGU_SWSYSRST, &val); |
| 587 | val |= FIELD_PREP(SWSYSRST_UNLOCK_KEY, 0x88); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 588 | val &= ~(SWSYSRST_XFI_PEXPT1_GRST | |
| 589 | SWSYSRST_XFI1_GRST); |
developer | 6aa0016 | 2023-03-20 11:56:51 +0800 | [diff] [blame] | 590 | regmap_write(eth->toprgu, TOPRGU_SWSYSRST, val); |
| 591 | |
| 592 | /* Disable software reset */ |
| 593 | regmap_read(eth->toprgu, TOPRGU_SWSYSRST_EN, &val); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 594 | val &= ~(SWSYSRST_XFI_PEXPT1_GRST | |
| 595 | SWSYSRST_XFI1_GRST); |
developer | 6aa0016 | 2023-03-20 11:56:51 +0800 | [diff] [blame] | 596 | regmap_write(eth->toprgu, TOPRGU_SWSYSRST_EN, val); |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 597 | break; |
| 598 | } |
| 599 | |
developer | 993b385 | 2022-12-08 15:58:20 +0800 | [diff] [blame] | 600 | mdelay(10); |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 601 | } |
| 602 | |
developer | 8900c0a | 2023-05-09 10:37:33 +0800 | [diff] [blame] | 603 | static int mtk_usxgmii_pcs_config(struct phylink_pcs *pcs, unsigned int mode, |
| 604 | phy_interface_t interface, |
| 605 | const unsigned long *advertising, |
| 606 | bool permit_pause_to_mac) |
| 607 | { |
| 608 | struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs); |
| 609 | struct mtk_eth *eth = mpcs->eth; |
| 610 | int err = 0; |
| 611 | |
| 612 | mpcs->interface = interface; |
| 613 | |
| 614 | mtk_usxgmii_xfi_pll_enable(eth->usxgmii); |
| 615 | mtk_usxgmii_reset(eth, mpcs->id); |
| 616 | |
| 617 | /* Setup USXGMIISYS with the determined property */ |
| 618 | if (interface == PHY_INTERFACE_MODE_USXGMII) |
| 619 | err = mtk_usxgmii_setup_phya_an_10000(mpcs); |
| 620 | else if (interface == PHY_INTERFACE_MODE_10GKR) |
| 621 | err = mtk_usxgmii_setup_phya_force_10000(mpcs); |
| 622 | else if (interface == PHY_INTERFACE_MODE_5GBASER) |
| 623 | err = mtk_usxgmii_setup_phya_force_5000(mpcs); |
| 624 | |
| 625 | return err; |
| 626 | } |
| 627 | |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 628 | static void mtk_usxgmii_pcs_get_state(struct phylink_pcs *pcs, |
| 629 | struct phylink_link_state *state) |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 630 | { |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 631 | struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs); |
| 632 | struct mtk_eth *eth = mpcs->eth; |
| 633 | struct mtk_mac *mac = eth->mac[mtk_xgmii2mac_id(eth, mpcs->id)]; |
| 634 | u32 val = 0; |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 635 | |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 636 | regmap_read(mpcs->regmap, RG_PCS_AN_CTRL0, &val); |
| 637 | if (FIELD_GET(USXGMII_AN_ENABLE, val)) { |
| 638 | /* Refresh LPA by inverting LPA_LATCH */ |
| 639 | regmap_read(mpcs->regmap, RG_PCS_AN_STS0, &val); |
| 640 | regmap_update_bits(mpcs->regmap, RG_PCS_AN_STS0, |
| 641 | USXGMII_LPA_LATCH, |
| 642 | !(val & USXGMII_LPA_LATCH)); |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 643 | |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 644 | regmap_read(mpcs->regmap, RG_PCS_AN_STS0, &val); |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 645 | |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 646 | state->interface = mpcs->interface; |
| 647 | state->link = FIELD_GET(USXGMII_LPA_LINK, val); |
| 648 | state->duplex = FIELD_GET(USXGMII_LPA_DUPLEX, val); |
| 649 | |
| 650 | switch (FIELD_GET(USXGMII_LPA_SPEED_MASK, val)) { |
| 651 | case USXGMII_LPA_SPEED_10: |
| 652 | state->speed = SPEED_10; |
| 653 | break; |
| 654 | case USXGMII_LPA_SPEED_100: |
| 655 | state->speed = SPEED_100; |
| 656 | break; |
| 657 | case USXGMII_LPA_SPEED_1000: |
| 658 | state->speed = SPEED_1000; |
| 659 | break; |
| 660 | case USXGMII_LPA_SPEED_2500: |
| 661 | state->speed = SPEED_2500; |
| 662 | break; |
| 663 | case USXGMII_LPA_SPEED_5000: |
| 664 | state->speed = SPEED_5000; |
| 665 | break; |
| 666 | case USXGMII_LPA_SPEED_10000: |
| 667 | state->speed = SPEED_10000; |
| 668 | break; |
| 669 | } |
| 670 | } else { |
| 671 | val = mtk_r32(mac->hw, MTK_XGMAC_STS(mac->id)); |
| 672 | |
| 673 | if (mac->id == MTK_GMAC2_ID) |
| 674 | val = val >> 16; |
| 675 | |
| 676 | switch (FIELD_GET(MTK_USXGMII_PCS_MODE, val)) { |
| 677 | case 0: |
| 678 | state->speed = SPEED_10000; |
| 679 | break; |
| 680 | case 1: |
| 681 | state->speed = SPEED_5000; |
| 682 | break; |
| 683 | case 2: |
| 684 | state->speed = SPEED_2500; |
| 685 | break; |
| 686 | case 3: |
| 687 | state->speed = SPEED_1000; |
| 688 | break; |
| 689 | } |
| 690 | |
| 691 | state->interface = mpcs->interface; |
| 692 | state->link = FIELD_GET(MTK_USXGMII_PCS_LINK, val); |
| 693 | state->duplex = DUPLEX_FULL; |
| 694 | } |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 695 | |
developer | 8900c0a | 2023-05-09 10:37:33 +0800 | [diff] [blame] | 696 | if (state->link == 0) |
| 697 | mtk_usxgmii_pcs_config(pcs, MLO_AN_INBAND, |
| 698 | state->interface, NULL, false); |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 699 | } |
| 700 | |
| 701 | void mtk_usxgmii_pcs_restart_an(struct phylink_pcs *pcs) |
| 702 | { |
| 703 | struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs); |
| 704 | unsigned int val = 0; |
| 705 | |
| 706 | if (!mpcs->regmap) |
| 707 | return; |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 708 | |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 709 | regmap_read(mpcs->regmap, RG_PCS_AN_CTRL0, &val); |
| 710 | val |= USXGMII_AN_RESTART; |
| 711 | regmap_write(mpcs->regmap, RG_PCS_AN_CTRL0, val); |
| 712 | } |
| 713 | |
developer | aeaea7b | 2023-05-18 18:20:10 +0800 | [diff] [blame] | 714 | static void mtk_usxgmii_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode, |
| 715 | phy_interface_t interface, |
| 716 | int speed, int duplex) |
| 717 | { |
| 718 | /* Reconfiguring USXGMII to ensure the quality of the RX signal |
| 719 | * after the line side link up. |
| 720 | */ |
| 721 | mtk_usxgmii_pcs_config(pcs, mode, |
| 722 | interface, NULL, false); |
| 723 | } |
| 724 | |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 725 | static const struct phylink_pcs_ops mtk_usxgmii_pcs_ops = { |
| 726 | .pcs_config = mtk_usxgmii_pcs_config, |
| 727 | .pcs_get_state = mtk_usxgmii_pcs_get_state, |
| 728 | .pcs_an_restart = mtk_usxgmii_pcs_restart_an, |
developer | aeaea7b | 2023-05-18 18:20:10 +0800 | [diff] [blame] | 729 | .pcs_link_up = mtk_usxgmii_pcs_link_up, |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 730 | }; |
| 731 | |
| 732 | int mtk_usxgmii_init(struct mtk_eth *eth, struct device_node *r) |
| 733 | { |
| 734 | struct mtk_usxgmii *ss = eth->usxgmii; |
| 735 | struct device_node *np; |
| 736 | int ret, i; |
| 737 | |
| 738 | for (i = 0; i < MTK_MAX_DEVS; i++) { |
| 739 | np = of_parse_phandle(r, "mediatek,usxgmiisys", i); |
| 740 | if (!np) |
| 741 | break; |
| 742 | |
| 743 | ss->pcs[i].id = i; |
| 744 | ss->pcs[i].eth = eth; |
| 745 | |
| 746 | ss->pcs[i].regmap = syscon_node_to_regmap(np); |
| 747 | if (IS_ERR(ss->pcs[i].regmap)) |
| 748 | return PTR_ERR(ss->pcs[i].regmap); |
| 749 | |
| 750 | ss->pcs[i].pcs.ops = &mtk_usxgmii_pcs_ops; |
| 751 | ss->pcs[i].pcs.poll = true; |
| 752 | ss->pcs[i].interface = PHY_INTERFACE_MODE_NA; |
| 753 | |
| 754 | of_node_put(np); |
| 755 | } |
| 756 | |
| 757 | ret = mtk_usxgmii_xfi_pextp_init(ss, r); |
| 758 | if (ret) |
| 759 | return ret; |
| 760 | |
| 761 | ret = mtk_usxgmii_xfi_pll_init(ss, r); |
| 762 | if (ret) |
| 763 | return ret; |
developer | 089e885 | 2022-09-28 14:43:46 +0800 | [diff] [blame] | 764 | |
| 765 | return 0; |
| 766 | } |
developer | 31d1066 | 2023-02-09 16:56:34 +0800 | [diff] [blame] | 767 | |
developer | 4e8a3fd | 2023-04-10 18:05:44 +0800 | [diff] [blame] | 768 | struct phylink_pcs *mtk_usxgmii_select_pcs(struct mtk_usxgmii *ss, int id) |
| 769 | { |
| 770 | if (!ss->pcs[id].regmap) |
| 771 | return NULL; |
| 772 | |
| 773 | return &ss->pcs[id].pcs; |
| 774 | } |
| 775 | |
developer | 31d1066 | 2023-02-09 16:56:34 +0800 | [diff] [blame] | 776 | int mtk_dump_usxgmii(struct regmap *pmap, char *name, u32 offset, u32 range) |
| 777 | { |
| 778 | unsigned int cur = offset; |
| 779 | unsigned int val1 = 0, val2 = 0, val3 = 0, val4 = 0; |
| 780 | |
| 781 | pr_info("\n============ %s ============ pmap:%x\n", name, pmap); |
| 782 | while (cur < offset + range) { |
| 783 | regmap_read(pmap, cur, &val1); |
| 784 | regmap_read(pmap, cur + 0x4, &val2); |
| 785 | regmap_read(pmap, cur + 0x8, &val3); |
| 786 | regmap_read(pmap, cur + 0xc, &val4); |
| 787 | pr_info("0x%x: %08x %08x %08x %08x\n", cur, |
| 788 | val1, val2, val3, val4); |
| 789 | cur += 0x10; |
| 790 | } |
| 791 | return 0; |
| 792 | } |
| 793 | |