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git01.mediatek.com / openwrt / feeds / mtk-openwrt-feeds / 089e885f257b6c31f5842a2cc4577c1f8afcf771 / . / target / linux / mediatek / files-5.4 / drivers / net / ethernet / mediatek / mtk_usxgmii.c
blob: aaefa806b3d75280f2bc0cacf3c2dd83f218e281 [file] [log] [blame]
developer089e8852022-09-28 14:43:46 +0800[diff] [blame^]1/* SPDX-License-Identifier: GPL-2.0
2 *
3 * Copyright (c) 2022 MediaTek Inc.
4 * Author: Henry Yen <henry.yen@mediatek.com>
5 */
6
7#include <linux/mfd/syscon.h>
8#include <linux/of.h>
9#include <linux/regmap.h>
10#include "mtk_eth_soc.h"
11
12int mtk_usxgmii_init(struct mtk_xgmii *ss, struct device_node *r)
13{
14 struct device_node *np;
15 int i;
16
17 for (i = 0; i < MTK_MAX_DEVS; i++) {
18 np = of_parse_phandle(r, "mediatek,usxgmiisys", i);
19 if (!np)
20 break;
21
22 ss->regmap_usxgmii[i] = syscon_node_to_regmap(np);
23 if (IS_ERR(ss->regmap_usxgmii[i]))
24 return PTR_ERR(ss->regmap_usxgmii[i]);
25
26 ss->flags[i] &= ~(MTK_USXGMII_INT_2500);
27 if (of_property_read_bool(np, "internal_2500"))
28 ss->flags[i] |= MTK_USXGMII_INT_2500;
29 }
30
31 return 0;
32}
33
34int mtk_xfi_pextp_init(struct mtk_xgmii *ss, struct device_node *r)
35{
36 struct device_node *np;
37 int i;
38
39 for (i = 0; i < MTK_MAX_DEVS; i++) {
40 np = of_parse_phandle(r, "mediatek,xfi_pextp", i);
41 if (!np)
42 break;
43
44 ss->regmap_pextp[i] = syscon_node_to_regmap(np);
45 if (IS_ERR(ss->regmap_pextp[i]))
46 return PTR_ERR(ss->regmap_pextp[i]);
47 }
48
49 return 0;
50}
51
52int mtk_xfi_pll_init(struct mtk_xgmii *ss, struct device_node *r)
53{
54 struct device_node *np;
55
56 np = of_parse_phandle(r, "mediatek,xfi_pll", 0);
57 if (!np)
58 return -1;
59
60 ss->regmap_pll = syscon_node_to_regmap(np);
61 if (IS_ERR(ss->regmap_pll))
62 return PTR_ERR(ss->regmap_pll);
63
64 return 0;
65}
66
67int mtk_toprgu_init(struct mtk_eth *eth, struct device_node *r)
68{
69 struct device_node *np;
70
71 np = of_parse_phandle(r, "mediatek,toprgu", 0);
72 if (!np)
73 return -1;
74
75 eth->toprgu = syscon_node_to_regmap(np);
76 if (IS_ERR(eth->toprgu))
77 return PTR_ERR(eth->toprgu);
78
79 return 0;
80}
81
82int mtk_xfi_pll_enable(struct mtk_xgmii *ss)
83{
84 u32 val = 0;
85
86 if (!ss->regmap_pll)
87 return -EINVAL;
88
89 /* Add software workaround for USXGMII PLL TCL issue */
90 regmap_write(ss->regmap_pll, XFI_PLL_ANA_GLB8, RG_XFI_PLL_ANA_SWWA);
91
92 regmap_read(ss->regmap_pll, XFI_PLL_DIG_GLB8, &val);
93 val |= RG_XFI_PLL_EN;
94 regmap_write(ss->regmap_pll, XFI_PLL_DIG_GLB8, val);
95
96 return 0;
97}
98
99int mtk_mac2xgmii_id(struct mtk_eth *eth, int mac_id)
100{
101 u32 xgmii_id = mac_id;
102
103 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) {
104 switch (mac_id) {
105 case MTK_GMAC1_ID:
106 case MTK_GMAC2_ID:
107 xgmii_id = 1;
108 break;
109 case MTK_GMAC3_ID:
110 xgmii_id = 0;
111 break;
112 default:
113 pr_info("[%s] Warning: get illegal mac_id=%d !=!!!\n",
114 __func__, mac_id);
115 }
116 }
117
118 return xgmii_id;
119}
120
121void mtk_usxgmii_setup_phya_an_10000(struct mtk_xgmii *ss, int mac_id)
122{
123 u32 id = mtk_mac2xgmii_id(ss->eth, mac_id);
124
125 if (id < 0 || id >= MTK_MAX_DEVS ||
126 !ss->regmap_usxgmii[id] || !ss->regmap_pextp[id])
127 return;
128
129 regmap_update_bits(ss->regmap_usxgmii[id], 0x810, GENMASK(31, 0), 0x000FFE6D);
130 regmap_update_bits(ss->regmap_usxgmii[id], 0x818, GENMASK(31, 0), 0x07B1EC7B);
131 regmap_update_bits(ss->regmap_usxgmii[id], 0x80C, GENMASK(31, 0), 0x30000000);
132 ndelay(1020);
133 regmap_update_bits(ss->regmap_usxgmii[id], 0x80C, GENMASK(31, 0), 0x10000000);
134 ndelay(1020);
135 regmap_update_bits(ss->regmap_usxgmii[id], 0x80C, GENMASK(31, 0), 0x00000000);
136
137 regmap_update_bits(ss->regmap_pextp[id], 0x9024, GENMASK(31, 0), 0x00C9071C);
138 regmap_update_bits(ss->regmap_pextp[id], 0x2020, GENMASK(31, 0), 0xAA8585AA);
139 regmap_update_bits(ss->regmap_pextp[id], 0x2030, GENMASK(31, 0), 0x0C020707);
140 regmap_update_bits(ss->regmap_pextp[id], 0x2034, GENMASK(31, 0), 0x0E050F0F);
141 regmap_update_bits(ss->regmap_pextp[id], 0x2040, GENMASK(31, 0), 0x00140032);
142 regmap_update_bits(ss->regmap_pextp[id], 0x50F0, GENMASK(31, 0), 0x00C014AA);
143 regmap_update_bits(ss->regmap_pextp[id], 0x50E0, GENMASK(31, 0), 0x3777C12B);
144 regmap_update_bits(ss->regmap_pextp[id], 0x506C, GENMASK(31, 0), 0x005F9CFF);
145 regmap_update_bits(ss->regmap_pextp[id], 0x5070, GENMASK(31, 0), 0x9D9DFAFA);
146 regmap_update_bits(ss->regmap_pextp[id], 0x5074, GENMASK(31, 0), 0x27273F3F);
147 regmap_update_bits(ss->regmap_pextp[id], 0x5078, GENMASK(31, 0), 0xA7883C68);
148 regmap_update_bits(ss->regmap_pextp[id], 0x507C, GENMASK(31, 0), 0x11661166);
149 regmap_update_bits(ss->regmap_pextp[id], 0x5080, GENMASK(31, 0), 0x0E000AAF);
150 regmap_update_bits(ss->regmap_pextp[id], 0x5084, GENMASK(31, 0), 0x08080D0D);
151 regmap_update_bits(ss->regmap_pextp[id], 0x5088, GENMASK(31, 0), 0x02030909);
152 regmap_update_bits(ss->regmap_pextp[id], 0x50E4, GENMASK(31, 0), 0x0C0C0000);
153 regmap_update_bits(ss->regmap_pextp[id], 0x50E8, GENMASK(31, 0), 0x04040000);
154 regmap_update_bits(ss->regmap_pextp[id], 0x50EC, GENMASK(31, 0), 0x0F0F0C06);
155 regmap_update_bits(ss->regmap_pextp[id], 0x50A8, GENMASK(31, 0), 0x506E8C8C);
156 regmap_update_bits(ss->regmap_pextp[id], 0x6004, GENMASK(31, 0), 0x18190000);
157 regmap_update_bits(ss->regmap_pextp[id], 0x00F8, GENMASK(31, 0), 0x01423342);
158 regmap_update_bits(ss->regmap_pextp[id], 0x00F4, GENMASK(31, 0), 0x80201F20);
159 regmap_update_bits(ss->regmap_pextp[id], 0x0030, GENMASK(31, 0), 0x00050C00);
160 regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x02002800);
161 ndelay(1020);
162 regmap_update_bits(ss->regmap_pextp[id], 0x30B0, GENMASK(31, 0), 0x00000020);
163 regmap_update_bits(ss->regmap_pextp[id], 0x3028, GENMASK(31, 0), 0x00008A01);
164 regmap_update_bits(ss->regmap_pextp[id], 0x302C, GENMASK(31, 0), 0x0000A884);
165 regmap_update_bits(ss->regmap_pextp[id], 0x3024, GENMASK(31, 0), 0x00083002);
166 regmap_update_bits(ss->regmap_pextp[id], 0x3010, GENMASK(31, 0), 0x00022220);
167 regmap_update_bits(ss->regmap_pextp[id], 0x5064, GENMASK(31, 0), 0x0F020A01);
168 regmap_update_bits(ss->regmap_pextp[id], 0x50B4, GENMASK(31, 0), 0x06100600);
169 regmap_update_bits(ss->regmap_pextp[id], 0x3048, GENMASK(31, 0), 0x40704000);
170 regmap_update_bits(ss->regmap_pextp[id], 0x3050, GENMASK(31, 0), 0xA8000000);
171 regmap_update_bits(ss->regmap_pextp[id], 0x3054, GENMASK(31, 0), 0x000000AA);
172 regmap_update_bits(ss->regmap_pextp[id], 0x306C, GENMASK(31, 0), 0x00000F00);
173 regmap_update_bits(ss->regmap_pextp[id], 0xA060, GENMASK(31, 0), 0x00040000);
174 regmap_update_bits(ss->regmap_pextp[id], 0x90D0, GENMASK(31, 0), 0x00000001);
175 regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x0200E800);
176 udelay(150);
177 regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x0200C111);
178 ndelay(1020);
179 regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x0200C101);
180 udelay(15);
181 regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x0202C111);
182 ndelay(1020);
183 regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x0202C101);
184 udelay(100);
185 regmap_update_bits(ss->regmap_pextp[id], 0x30B0, GENMASK(31, 0), 0x00000030);
186 regmap_update_bits(ss->regmap_pextp[id], 0x00F4, GENMASK(31, 0), 0x80201F00);
187 regmap_update_bits(ss->regmap_pextp[id], 0x3040, GENMASK(31, 0), 0x30000000);
188 udelay(400);
189}
190
191void mtk_usxgmii_setup_phya_force(struct mtk_xgmii *ss, int mac_id, int max_speed)
192{
193 unsigned int val;
194 u32 id = mtk_mac2xgmii_id(ss->eth, mac_id);
195
196 if (id < 0 || id >= MTK_MAX_DEVS ||
197 !ss->regmap_usxgmii[id] || !ss->regmap_pextp[id])
198 return;
199
200 /* Decide USXGMII speed */
201 switch (max_speed) {
202 case SPEED_5000:
203 val = FIELD_PREP(RG_XFI_RX_MODE, RG_XFI_RX_MODE_5G) |
204 FIELD_PREP(RG_XFI_TX_MODE, RG_XFI_TX_MODE_5G);
205 break;
206 case SPEED_10000:
207 default:
208 val = FIELD_PREP(RG_XFI_RX_MODE, RG_XFI_RX_MODE_10G) |
209 FIELD_PREP(RG_XFI_TX_MODE, RG_XFI_TX_MODE_10G);
210 break;
211 };
212 regmap_write(ss->regmap_usxgmii[id], RG_PHY_TOP_SPEED_CTRL1, val);
213
214 /* Disable USXGMII AN mode */
215 regmap_read(ss->regmap_usxgmii[id], RG_PCS_AN_CTRL0, &val);
216 val &= ~RG_AN_ENABLE;
217 regmap_write(ss->regmap_usxgmii[id], RG_PCS_AN_CTRL0, val);
218
219 /* Gated USXGMII */
220 regmap_read(ss->regmap_usxgmii[id], RG_PHY_TOP_SPEED_CTRL1, &val);
221 val |= RG_MAC_CK_GATED;
222 regmap_write(ss->regmap_usxgmii[id], RG_PHY_TOP_SPEED_CTRL1, val);
223
224 ndelay(1020);
225
226 /* USXGMII force mode setting */
227 regmap_read(ss->regmap_usxgmii[id], RG_PHY_TOP_SPEED_CTRL1, &val);
228 val |= RG_USXGMII_RATE_UPDATE_MODE;
229 val |= RG_IF_FORCE_EN;
230 val |= FIELD_PREP(RG_RATE_ADAPT_MODE, RG_RATE_ADAPT_MODE_X1);
231 regmap_write(ss->regmap_usxgmii[id], RG_PHY_TOP_SPEED_CTRL1, val);
232
233 /* Un-gated USXGMII */
234 regmap_read(ss->regmap_usxgmii[id], RG_PHY_TOP_SPEED_CTRL1, &val);
235 val &= ~RG_MAC_CK_GATED;
236 regmap_write(ss->regmap_usxgmii[id], RG_PHY_TOP_SPEED_CTRL1, val);
237
238 ndelay(1020);
239
240 regmap_update_bits(ss->regmap_pextp[id], 0x9024, GENMASK(31, 0), 0x00C9071C);
241 regmap_update_bits(ss->regmap_pextp[id], 0x2020, GENMASK(31, 0), 0xAA8585AA);
242 regmap_update_bits(ss->regmap_pextp[id], 0x2030, GENMASK(31, 0), 0x0C020707);
243 regmap_update_bits(ss->regmap_pextp[id], 0x2034, GENMASK(31, 0), 0x0E050F0F);
244 regmap_update_bits(ss->regmap_pextp[id], 0x2040, GENMASK(31, 0), 0x00140032);
245 regmap_update_bits(ss->regmap_pextp[id], 0x50F0, GENMASK(31, 0), 0x00C014AA);
246 regmap_update_bits(ss->regmap_pextp[id], 0x50E0, GENMASK(31, 0), 0x3777C12B);
247 regmap_update_bits(ss->regmap_pextp[id], 0x506C, GENMASK(31, 0), 0x005F9CFF);
248 regmap_update_bits(ss->regmap_pextp[id], 0x5070, GENMASK(31, 0), 0x9D9DFAFA);
249 regmap_update_bits(ss->regmap_pextp[id], 0x5074, GENMASK(31, 0), 0x27273F3F);
250 regmap_update_bits(ss->regmap_pextp[id], 0x5078, GENMASK(31, 0), 0xA7883C68);
251 regmap_update_bits(ss->regmap_pextp[id], 0x507C, GENMASK(31, 0), 0x11661166);
252 regmap_update_bits(ss->regmap_pextp[id], 0x5080, GENMASK(31, 0), 0x0E000AAF);
253 regmap_update_bits(ss->regmap_pextp[id], 0x5084, GENMASK(31, 0), 0x08080D0D);
254 regmap_update_bits(ss->regmap_pextp[id], 0x5088, GENMASK(31, 0), 0x02030909);
255 regmap_update_bits(ss->regmap_pextp[id], 0x50E4, GENMASK(31, 0), 0x0C0C0000);
256 regmap_update_bits(ss->regmap_pextp[id], 0x50E8, GENMASK(31, 0), 0x04040000);
257 regmap_update_bits(ss->regmap_pextp[id], 0x50EC, GENMASK(31, 0), 0x0F0F0C06);
258 regmap_update_bits(ss->regmap_pextp[id], 0x50A8, GENMASK(31, 0), 0x506E8C8C);
259 regmap_update_bits(ss->regmap_pextp[id], 0x6004, GENMASK(31, 0), 0x18190000);
260 regmap_update_bits(ss->regmap_pextp[id], 0x00F8, GENMASK(31, 0), 0x01423342);
261 regmap_update_bits(ss->regmap_pextp[id], 0x00F4, GENMASK(31, 0), 0x80201F20);
262 regmap_update_bits(ss->regmap_pextp[id], 0x0030, GENMASK(31, 0), 0x00050C00);
263 regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x02002800);
264 ndelay(1020);
265 regmap_update_bits(ss->regmap_pextp[id], 0x30B0, GENMASK(31, 0), 0x00000020);
266 regmap_update_bits(ss->regmap_pextp[id], 0x3028, GENMASK(31, 0), 0x00008A01);
267 regmap_update_bits(ss->regmap_pextp[id], 0x302C, GENMASK(31, 0), 0x0000A884);
268 regmap_update_bits(ss->regmap_pextp[id], 0x3024, GENMASK(31, 0), 0x00083002);
269 regmap_update_bits(ss->regmap_pextp[id], 0x3010, GENMASK(31, 0), 0x00022220);
270 regmap_update_bits(ss->regmap_pextp[id], 0x5064, GENMASK(31, 0), 0x0F020A01);
271 regmap_update_bits(ss->regmap_pextp[id], 0x50B4, GENMASK(31, 0), 0x06100600);
272 regmap_update_bits(ss->regmap_pextp[id], 0x3048, GENMASK(31, 0), 0x49664100);
273 regmap_update_bits(ss->regmap_pextp[id], 0x3050, GENMASK(31, 0), 0x00000000);
274 regmap_update_bits(ss->regmap_pextp[id], 0x3054, GENMASK(31, 0), 0x00000000);
275 regmap_update_bits(ss->regmap_pextp[id], 0x306C, GENMASK(31, 0), 0x00000F00);
276 regmap_update_bits(ss->regmap_pextp[id], 0xA060, GENMASK(31, 0), 0x00040000);
277 regmap_update_bits(ss->regmap_pextp[id], 0x90D0, GENMASK(31, 0), 0x00000001);
278 regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x0200E800);
279 udelay(150);
280 regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x0200C111);
281 ndelay(1020);
282 regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x0200C101);
283 udelay(15);
284 regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x0202C111);
285 ndelay(1020);
286 regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x0202C101);
287 udelay(100);
288 regmap_update_bits(ss->regmap_pextp[id], 0x30B0, GENMASK(31, 0), 0x00000030);
289 regmap_update_bits(ss->regmap_pextp[id], 0x00F4, GENMASK(31, 0), 0x80201F00);
290 regmap_update_bits(ss->regmap_pextp[id], 0x3040, GENMASK(31, 0), 0x30000000);
291 udelay(400);
292}
293
294void mtk_usxgmii_reset(struct mtk_xgmii *ss, int mac_id)
295{
296 struct mtk_eth *eth = ss->eth;
297 u32 id = mtk_mac2xgmii_id(eth, mac_id);
298
299 if (id < 0 || id >= MTK_MAX_DEVS || !eth->toprgu)
300 return;
301
302 switch (mac_id) {
303 case MTK_GMAC2_ID:
304 regmap_update_bits(eth->toprgu, 0xFC, GENMASK(31, 0), 0x0000A004);
305 regmap_update_bits(eth->toprgu, 0x18, GENMASK(31, 0), 0x88F0A004);
306 regmap_update_bits(eth->toprgu, 0xFC, GENMASK(31, 0), 0x00000000);
307 regmap_update_bits(eth->toprgu, 0x18, GENMASK(31, 0), 0x88F00000);
308 regmap_update_bits(eth->toprgu, 0x18, GENMASK(31, 0), 0x00F00000);
309 break;
310 case MTK_GMAC3_ID:
311 regmap_update_bits(eth->toprgu, 0xFC, GENMASK(31, 0), 0x00005002);
312 regmap_update_bits(eth->toprgu, 0x18, GENMASK(31, 0), 0x88F05002);
313 regmap_update_bits(eth->toprgu, 0xFC, GENMASK(31, 0), 0x00000000);
314 regmap_update_bits(eth->toprgu, 0x18, GENMASK(31, 0), 0x88F00000);
315 regmap_update_bits(eth->toprgu, 0x18, GENMASK(31, 0), 0x00F00000);
316 break;
317 }
318
319 udelay(100);
320}
321
322int mtk_usxgmii_setup_mode_an(struct mtk_xgmii *ss, int mac_id, int max_speed)
323{
324 if (mac_id < 0 || mac_id >= MTK_MAX_DEVS)
325 return -EINVAL;
326
327 if ((max_speed != SPEED_10000) && (max_speed != SPEED_5000))
328 return -EINVAL;
329
330 mtk_xfi_pll_enable(ss);
331 mtk_usxgmii_reset(ss, mac_id);
332 mtk_usxgmii_setup_phya_an_10000(ss, mac_id);
333
334 return 0;
335}
336
337int mtk_usxgmii_setup_mode_force(struct mtk_xgmii *ss, int mac_id, int max_speed)
338{
339 if (mac_id < 0 || mac_id >= MTK_MAX_DEVS)
340 return -EINVAL;
341
342 if ((max_speed != SPEED_10000) && (max_speed != SPEED_5000))
343 return -EINVAL;
344
345 mtk_xfi_pll_enable(ss);
346 mtk_usxgmii_reset(ss, mac_id);
347 mtk_usxgmii_setup_phya_force(ss, mac_id, max_speed);
348
349 return 0;
350}