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git01.mediatek.com / openwrt / feeds / mtk-openwrt-feeds / 6aa00169a7ab2e5bd7a3db1b0bedc21ea2efe77d / . / target / linux / mediatek / files-5.4 / drivers / net / ethernet / mediatek / mtk_usxgmii.c
blob: 8fb28cac284ff647c038e0345ce316e11940131a [file] [log] [blame]
developer089e8852022-09-28 14:43:46 +0800[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0
2 *
3 * Copyright (c) 2022 MediaTek Inc.
4 * Author: Henry Yen <henry.yen@mediatek.com>
5 */
6
7#include <linux/mfd/syscon.h>
8#include <linux/of.h>
9#include <linux/regmap.h>
10#include "mtk_eth_soc.h"
11
12int mtk_usxgmii_init(struct mtk_xgmii *ss, struct device_node *r)
13{
14 struct device_node *np;
15 int i;
16
17 for (i = 0; i < MTK_MAX_DEVS; i++) {
18 np = of_parse_phandle(r, "mediatek,usxgmiisys", i);
19 if (!np)
20 break;
21
22 ss->regmap_usxgmii[i] = syscon_node_to_regmap(np);
23 if (IS_ERR(ss->regmap_usxgmii[i]))
24 return PTR_ERR(ss->regmap_usxgmii[i]);
developer089e8852022-09-28 14:43:46 +0800[diff] [blame]25 }
26
27 return 0;
28}
29
30int mtk_xfi_pextp_init(struct mtk_xgmii *ss, struct device_node *r)
31{
32 struct device_node *np;
33 int i;
34
35 for (i = 0; i < MTK_MAX_DEVS; i++) {
36 np = of_parse_phandle(r, "mediatek,xfi_pextp", i);
37 if (!np)
38 break;
39
40 ss->regmap_pextp[i] = syscon_node_to_regmap(np);
41 if (IS_ERR(ss->regmap_pextp[i]))
42 return PTR_ERR(ss->regmap_pextp[i]);
43 }
44
45 return 0;
46}
47
48int mtk_xfi_pll_init(struct mtk_xgmii *ss, struct device_node *r)
49{
50 struct device_node *np;
51
52 np = of_parse_phandle(r, "mediatek,xfi_pll", 0);
53 if (!np)
54 return -1;
55
56 ss->regmap_pll = syscon_node_to_regmap(np);
57 if (IS_ERR(ss->regmap_pll))
58 return PTR_ERR(ss->regmap_pll);
59
60 return 0;
61}
62
63int mtk_toprgu_init(struct mtk_eth *eth, struct device_node *r)
64{
65 struct device_node *np;
66
67 np = of_parse_phandle(r, "mediatek,toprgu", 0);
68 if (!np)
69 return -1;
70
71 eth->toprgu = syscon_node_to_regmap(np);
72 if (IS_ERR(eth->toprgu))
73 return PTR_ERR(eth->toprgu);
74
75 return 0;
76}
77
78int mtk_xfi_pll_enable(struct mtk_xgmii *ss)
79{
80 u32 val = 0;
81
82 if (!ss->regmap_pll)
83 return -EINVAL;
84
85 /* Add software workaround for USXGMII PLL TCL issue */
86 regmap_write(ss->regmap_pll, XFI_PLL_ANA_GLB8, RG_XFI_PLL_ANA_SWWA);
87
88 regmap_read(ss->regmap_pll, XFI_PLL_DIG_GLB8, &val);
89 val |= RG_XFI_PLL_EN;
90 regmap_write(ss->regmap_pll, XFI_PLL_DIG_GLB8, val);
91
92 return 0;
93}
94
95int mtk_mac2xgmii_id(struct mtk_eth *eth, int mac_id)
96{
97 u32 xgmii_id = mac_id;
98
99 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) {
100 switch (mac_id) {
101 case MTK_GMAC1_ID:
102 case MTK_GMAC2_ID:
103 xgmii_id = 1;
104 break;
105 case MTK_GMAC3_ID:
106 xgmii_id = 0;
107 break;
108 default:
109 pr_info("[%s] Warning: get illegal mac_id=%d !=!!!\n",
110 __func__, mac_id);
111 }
112 }
113
114 return xgmii_id;
115}
116
117void mtk_usxgmii_setup_phya_an_10000(struct mtk_xgmii *ss, int mac_id)
118{
119 u32 id = mtk_mac2xgmii_id(ss->eth, mac_id);
120
developer8b6f2402022-11-28 13:42:34 +0800[diff] [blame]121 if (id >= MTK_MAX_DEVS ||
developer089e8852022-09-28 14:43:46 +0800[diff] [blame]122 !ss->regmap_usxgmii[id] || !ss->regmap_pextp[id])
123 return;
124
125 regmap_update_bits(ss->regmap_usxgmii[id], 0x810, GENMASK(31, 0), 0x000FFE6D);
126 regmap_update_bits(ss->regmap_usxgmii[id], 0x818, GENMASK(31, 0), 0x07B1EC7B);
127 regmap_update_bits(ss->regmap_usxgmii[id], 0x80C, GENMASK(31, 0), 0x30000000);
128 ndelay(1020);
129 regmap_update_bits(ss->regmap_usxgmii[id], 0x80C, GENMASK(31, 0), 0x10000000);
130 ndelay(1020);
131 regmap_update_bits(ss->regmap_usxgmii[id], 0x80C, GENMASK(31, 0), 0x00000000);
132
133 regmap_update_bits(ss->regmap_pextp[id], 0x9024, GENMASK(31, 0), 0x00C9071C);
134 regmap_update_bits(ss->regmap_pextp[id], 0x2020, GENMASK(31, 0), 0xAA8585AA);
135 regmap_update_bits(ss->regmap_pextp[id], 0x2030, GENMASK(31, 0), 0x0C020707);
136 regmap_update_bits(ss->regmap_pextp[id], 0x2034, GENMASK(31, 0), 0x0E050F0F);
137 regmap_update_bits(ss->regmap_pextp[id], 0x2040, GENMASK(31, 0), 0x00140032);
138 regmap_update_bits(ss->regmap_pextp[id], 0x50F0, GENMASK(31, 0), 0x00C014AA);
139 regmap_update_bits(ss->regmap_pextp[id], 0x50E0, GENMASK(31, 0), 0x3777C12B);
140 regmap_update_bits(ss->regmap_pextp[id], 0x506C, GENMASK(31, 0), 0x005F9CFF);
141 regmap_update_bits(ss->regmap_pextp[id], 0x5070, GENMASK(31, 0), 0x9D9DFAFA);
142 regmap_update_bits(ss->regmap_pextp[id], 0x5074, GENMASK(31, 0), 0x27273F3F);
143 regmap_update_bits(ss->regmap_pextp[id], 0x5078, GENMASK(31, 0), 0xA7883C68);
144 regmap_update_bits(ss->regmap_pextp[id], 0x507C, GENMASK(31, 0), 0x11661166);
145 regmap_update_bits(ss->regmap_pextp[id], 0x5080, GENMASK(31, 0), 0x0E000AAF);
146 regmap_update_bits(ss->regmap_pextp[id], 0x5084, GENMASK(31, 0), 0x08080D0D);
147 regmap_update_bits(ss->regmap_pextp[id], 0x5088, GENMASK(31, 0), 0x02030909);
148 regmap_update_bits(ss->regmap_pextp[id], 0x50E4, GENMASK(31, 0), 0x0C0C0000);
149 regmap_update_bits(ss->regmap_pextp[id], 0x50E8, GENMASK(31, 0), 0x04040000);
150 regmap_update_bits(ss->regmap_pextp[id], 0x50EC, GENMASK(31, 0), 0x0F0F0C06);
151 regmap_update_bits(ss->regmap_pextp[id], 0x50A8, GENMASK(31, 0), 0x506E8C8C);
152 regmap_update_bits(ss->regmap_pextp[id], 0x6004, GENMASK(31, 0), 0x18190000);
153 regmap_update_bits(ss->regmap_pextp[id], 0x00F8, GENMASK(31, 0), 0x01423342);
154 regmap_update_bits(ss->regmap_pextp[id], 0x00F4, GENMASK(31, 0), 0x80201F20);
155 regmap_update_bits(ss->regmap_pextp[id], 0x0030, GENMASK(31, 0), 0x00050C00);
156 regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x02002800);
157 ndelay(1020);
158 regmap_update_bits(ss->regmap_pextp[id], 0x30B0, GENMASK(31, 0), 0x00000020);
159 regmap_update_bits(ss->regmap_pextp[id], 0x3028, GENMASK(31, 0), 0x00008A01);
160 regmap_update_bits(ss->regmap_pextp[id], 0x302C, GENMASK(31, 0), 0x0000A884);
161 regmap_update_bits(ss->regmap_pextp[id], 0x3024, GENMASK(31, 0), 0x00083002);
162 regmap_update_bits(ss->regmap_pextp[id], 0x3010, GENMASK(31, 0), 0x00022220);
163 regmap_update_bits(ss->regmap_pextp[id], 0x5064, GENMASK(31, 0), 0x0F020A01);
164 regmap_update_bits(ss->regmap_pextp[id], 0x50B4, GENMASK(31, 0), 0x06100600);
165 regmap_update_bits(ss->regmap_pextp[id], 0x3048, GENMASK(31, 0), 0x40704000);
166 regmap_update_bits(ss->regmap_pextp[id], 0x3050, GENMASK(31, 0), 0xA8000000);
167 regmap_update_bits(ss->regmap_pextp[id], 0x3054, GENMASK(31, 0), 0x000000AA);
168 regmap_update_bits(ss->regmap_pextp[id], 0x306C, GENMASK(31, 0), 0x00000F00);
169 regmap_update_bits(ss->regmap_pextp[id], 0xA060, GENMASK(31, 0), 0x00040000);
170 regmap_update_bits(ss->regmap_pextp[id], 0x90D0, GENMASK(31, 0), 0x00000001);
171 regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x0200E800);
172 udelay(150);
173 regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x0200C111);
174 ndelay(1020);
175 regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x0200C101);
176 udelay(15);
177 regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x0202C111);
178 ndelay(1020);
179 regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x0202C101);
180 udelay(100);
181 regmap_update_bits(ss->regmap_pextp[id], 0x30B0, GENMASK(31, 0), 0x00000030);
182 regmap_update_bits(ss->regmap_pextp[id], 0x00F4, GENMASK(31, 0), 0x80201F00);
183 regmap_update_bits(ss->regmap_pextp[id], 0x3040, GENMASK(31, 0), 0x30000000);
184 udelay(400);
185}
186
developercfa104b2023-01-11 17:40:41 +0800[diff] [blame]187void mtk_usxgmii_setup_phya_force_5000(struct mtk_xgmii *ss, int mac_id)
developer089e8852022-09-28 14:43:46 +0800[diff] [blame]188{
189 unsigned int val;
190 u32 id = mtk_mac2xgmii_id(ss->eth, mac_id);
191
developer8b6f2402022-11-28 13:42:34 +0800[diff] [blame]192 if (id >= MTK_MAX_DEVS ||
developer089e8852022-09-28 14:43:46 +0800[diff] [blame]193 !ss->regmap_usxgmii[id] || !ss->regmap_pextp[id])
194 return;
195
developercfa104b2023-01-11 17:40:41 +0800[diff] [blame]196 /* Setup USXGMII speed */
197 val = FIELD_PREP(RG_XFI_RX_MODE, RG_XFI_RX_MODE_5G) |
198 FIELD_PREP(RG_XFI_TX_MODE, RG_XFI_TX_MODE_5G);
199 regmap_write(ss->regmap_usxgmii[id], RG_PHY_TOP_SPEED_CTRL1, val);
200
201 /* Disable USXGMII AN mode */
202 regmap_read(ss->regmap_usxgmii[id], RG_PCS_AN_CTRL0, &val);
203 val &= ~RG_AN_ENABLE;
204 regmap_write(ss->regmap_usxgmii[id], RG_PCS_AN_CTRL0, val);
205
206 /* Gated USXGMII */
207 regmap_read(ss->regmap_usxgmii[id], RG_PHY_TOP_SPEED_CTRL1, &val);
208 val |= RG_MAC_CK_GATED;
209 regmap_write(ss->regmap_usxgmii[id], RG_PHY_TOP_SPEED_CTRL1, val);
210
211 ndelay(1020);
212
213 /* USXGMII force mode setting */
214 regmap_read(ss->regmap_usxgmii[id], RG_PHY_TOP_SPEED_CTRL1, &val);
215 val |= RG_USXGMII_RATE_UPDATE_MODE;
216 val |= RG_IF_FORCE_EN;
217 val |= FIELD_PREP(RG_RATE_ADAPT_MODE, RG_RATE_ADAPT_MODE_X1);
218 regmap_write(ss->regmap_usxgmii[id], RG_PHY_TOP_SPEED_CTRL1, val);
219
220 /* Un-gated USXGMII */
221 regmap_read(ss->regmap_usxgmii[id], RG_PHY_TOP_SPEED_CTRL1, &val);
222 val &= ~RG_MAC_CK_GATED;
developer089e8852022-09-28 14:43:46 +0800[diff] [blame]223 regmap_write(ss->regmap_usxgmii[id], RG_PHY_TOP_SPEED_CTRL1, val);
224
developercfa104b2023-01-11 17:40:41 +0800[diff] [blame]225 ndelay(1020);
226
227 regmap_update_bits(ss->regmap_pextp[id], 0x9024, GENMASK(31, 0),
228 0x00D9071C);
229 regmap_update_bits(ss->regmap_pextp[id], 0x2020, GENMASK(31, 0),
230 0xAAA5A5AA);
231 regmap_update_bits(ss->regmap_pextp[id], 0x2030, GENMASK(31, 0),
232 0x0C020707);
233 regmap_update_bits(ss->regmap_pextp[id], 0x2034, GENMASK(31, 0),
234 0x0E050F0F);
235 regmap_update_bits(ss->regmap_pextp[id], 0x2040, GENMASK(31, 0),
236 0x00140032);
237 regmap_update_bits(ss->regmap_pextp[id], 0x50F0, GENMASK(31, 0),
238 0x00C018AA);
239 regmap_update_bits(ss->regmap_pextp[id], 0x50E0, GENMASK(31, 0),
240 0x3777812B);
241 regmap_update_bits(ss->regmap_pextp[id], 0x506C, GENMASK(31, 0),
242 0x005C9CFF);
243 regmap_update_bits(ss->regmap_pextp[id], 0x5070, GENMASK(31, 0),
244 0x9DFAFAFA);
245 regmap_update_bits(ss->regmap_pextp[id], 0x5074, GENMASK(31, 0),
246 0x273F3F3F);
247 regmap_update_bits(ss->regmap_pextp[id], 0x5078, GENMASK(31, 0),
248 0xA8883868);
249 regmap_update_bits(ss->regmap_pextp[id], 0x507C, GENMASK(31, 0),
250 0x14661466);
251 regmap_update_bits(ss->regmap_pextp[id], 0x5080, GENMASK(31, 0),
252 0x0E001ABF);
253 regmap_update_bits(ss->regmap_pextp[id], 0x5084, GENMASK(31, 0),
254 0x080B0D0D);
255 regmap_update_bits(ss->regmap_pextp[id], 0x5088, GENMASK(31, 0),
256 0x02050909);
257 regmap_update_bits(ss->regmap_pextp[id], 0x50E4, GENMASK(31, 0),
258 0x0C000000);
259 regmap_update_bits(ss->regmap_pextp[id], 0x50E8, GENMASK(31, 0),
260 0x04000000);
261 regmap_update_bits(ss->regmap_pextp[id], 0x50EC, GENMASK(31, 0),
262 0x0F0F0C06);
263 regmap_update_bits(ss->regmap_pextp[id], 0x50A8, GENMASK(31, 0),
264 0x50808C8C);
265 regmap_update_bits(ss->regmap_pextp[id], 0x6004, GENMASK(31, 0),
266 0x18000000);
267 regmap_update_bits(ss->regmap_pextp[id], 0x00F8, GENMASK(31, 0),
268 0x00A132A1);
269 regmap_update_bits(ss->regmap_pextp[id], 0x00F4, GENMASK(31, 0),
270 0x80201F20);
271 regmap_update_bits(ss->regmap_pextp[id], 0x0030, GENMASK(31, 0),
272 0x00050C00);
273 regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0),
274 0x02002800);
275 ndelay(1020);
276 regmap_update_bits(ss->regmap_pextp[id], 0x30B0, GENMASK(31, 0),
277 0x00000020);
278 regmap_update_bits(ss->regmap_pextp[id], 0x3028, GENMASK(31, 0),
279 0x00008A01);
280 regmap_update_bits(ss->regmap_pextp[id], 0x302C, GENMASK(31, 0),
281 0x0000A884);
282 regmap_update_bits(ss->regmap_pextp[id], 0x3024, GENMASK(31, 0),
283 0x00083002);
284 regmap_update_bits(ss->regmap_pextp[id], 0x3010, GENMASK(31, 0),
285 0x00022220);
286 regmap_update_bits(ss->regmap_pextp[id], 0x5064, GENMASK(31, 0),
287 0x0F020A01);
288 regmap_update_bits(ss->regmap_pextp[id], 0x50B4, GENMASK(31, 0),
289 0x06100600);
290 regmap_update_bits(ss->regmap_pextp[id], 0x3048, GENMASK(31, 0),
291 0x40704000);
292 regmap_update_bits(ss->regmap_pextp[id], 0x3050, GENMASK(31, 0),
293 0xA8000000);
294 regmap_update_bits(ss->regmap_pextp[id], 0x3054, GENMASK(31, 0),
295 0x000000AA);
296 regmap_update_bits(ss->regmap_pextp[id], 0x306C, GENMASK(31, 0),
297 0x00000F00);
298 regmap_update_bits(ss->regmap_pextp[id], 0xA060, GENMASK(31, 0),
299 0x00040000);
300 regmap_update_bits(ss->regmap_pextp[id], 0x90D0, GENMASK(31, 0),
301 0x00000003);
302 regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0),
303 0x0200E800);
304 udelay(150);
305 regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0),
306 0x0200C111);
307 ndelay(1020);
308 regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0),
309 0x0200C101);
310 udelay(15);
311 regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0),
312 0x0202C111);
313 ndelay(1020);
314 regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0),
315 0x0202C101);
316 udelay(100);
317 regmap_update_bits(ss->regmap_pextp[id], 0x30B0, GENMASK(31, 0),
318 0x00000030);
319 regmap_update_bits(ss->regmap_pextp[id], 0x00F4, GENMASK(31, 0),
320 0x80201F00);
321 regmap_update_bits(ss->regmap_pextp[id], 0x3040, GENMASK(31, 0),
322 0x30000000);
323 udelay(400);
324}
325
326void mtk_usxgmii_setup_phya_force_10000(struct mtk_xgmii *ss, int mac_id)
327{
328 unsigned int val;
329 u32 id = mtk_mac2xgmii_id(ss->eth, mac_id);
330
331 if (id >= MTK_MAX_DEVS ||
332 !ss->regmap_usxgmii[id] || !ss->regmap_pextp[id])
333 return;
334
335 /* Setup USXGMII speed */
336 val = FIELD_PREP(RG_XFI_RX_MODE, RG_XFI_RX_MODE_10G) |
337 FIELD_PREP(RG_XFI_TX_MODE, RG_XFI_TX_MODE_10G);
338 regmap_write(ss->regmap_usxgmii[id], RG_PHY_TOP_SPEED_CTRL1, val);
339
developer089e8852022-09-28 14:43:46 +0800[diff] [blame]340 /* Disable USXGMII AN mode */
341 regmap_read(ss->regmap_usxgmii[id], RG_PCS_AN_CTRL0, &val);
342 val &= ~RG_AN_ENABLE;
343 regmap_write(ss->regmap_usxgmii[id], RG_PCS_AN_CTRL0, val);
344
345 /* Gated USXGMII */
346 regmap_read(ss->regmap_usxgmii[id], RG_PHY_TOP_SPEED_CTRL1, &val);
347 val |= RG_MAC_CK_GATED;
348 regmap_write(ss->regmap_usxgmii[id], RG_PHY_TOP_SPEED_CTRL1, val);
349
350 ndelay(1020);
351
352 /* USXGMII force mode setting */
353 regmap_read(ss->regmap_usxgmii[id], RG_PHY_TOP_SPEED_CTRL1, &val);
354 val |= RG_USXGMII_RATE_UPDATE_MODE;
355 val |= RG_IF_FORCE_EN;
356 val |= FIELD_PREP(RG_RATE_ADAPT_MODE, RG_RATE_ADAPT_MODE_X1);
357 regmap_write(ss->regmap_usxgmii[id], RG_PHY_TOP_SPEED_CTRL1, val);
358
359 /* Un-gated USXGMII */
360 regmap_read(ss->regmap_usxgmii[id], RG_PHY_TOP_SPEED_CTRL1, &val);
361 val &= ~RG_MAC_CK_GATED;
362 regmap_write(ss->regmap_usxgmii[id], RG_PHY_TOP_SPEED_CTRL1, val);
363
364 ndelay(1020);
365
developercfa104b2023-01-11 17:40:41 +0800[diff] [blame]366 regmap_update_bits(ss->regmap_pextp[id], 0x9024, GENMASK(31, 0),
367 0x00C9071C);
368 regmap_update_bits(ss->regmap_pextp[id], 0x2020, GENMASK(31, 0),
369 0xAA8585AA);
370 regmap_update_bits(ss->regmap_pextp[id], 0x2030, GENMASK(31, 0),
371 0x0C020707);
372 regmap_update_bits(ss->regmap_pextp[id], 0x2034, GENMASK(31, 0),
373 0x0E050F0F);
374 regmap_update_bits(ss->regmap_pextp[id], 0x2040, GENMASK(31, 0),
375 0x00140032);
376 regmap_update_bits(ss->regmap_pextp[id], 0x50F0, GENMASK(31, 0),
377 0x00C014AA);
378 regmap_update_bits(ss->regmap_pextp[id], 0x50E0, GENMASK(31, 0),
379 0x3777C12B);
380 regmap_update_bits(ss->regmap_pextp[id], 0x506C, GENMASK(31, 0),
381 0x005F9CFF);
382 regmap_update_bits(ss->regmap_pextp[id], 0x5070, GENMASK(31, 0),
383 0x9D9DFAFA);
384 regmap_update_bits(ss->regmap_pextp[id], 0x5074, GENMASK(31, 0),
385 0x27273F3F);
386 regmap_update_bits(ss->regmap_pextp[id], 0x5078, GENMASK(31, 0),
387 0xA7883C68);
388 regmap_update_bits(ss->regmap_pextp[id], 0x507C, GENMASK(31, 0),
389 0x11661166);
390 regmap_update_bits(ss->regmap_pextp[id], 0x5080, GENMASK(31, 0),
391 0x0E000AAF);
392 regmap_update_bits(ss->regmap_pextp[id], 0x5084, GENMASK(31, 0),
393 0x08080D0D);
394 regmap_update_bits(ss->regmap_pextp[id], 0x5088, GENMASK(31, 0),
395 0x02030909);
396 regmap_update_bits(ss->regmap_pextp[id], 0x50E4, GENMASK(31, 0),
397 0x0C0C0000);
398 regmap_update_bits(ss->regmap_pextp[id], 0x50E8, GENMASK(31, 0),
399 0x04040000);
400 regmap_update_bits(ss->regmap_pextp[id], 0x50EC, GENMASK(31, 0),
401 0x0F0F0C06);
402 regmap_update_bits(ss->regmap_pextp[id], 0x50A8, GENMASK(31, 0),
403 0x506E8C8C);
404 regmap_update_bits(ss->regmap_pextp[id], 0x6004, GENMASK(31, 0),
405 0x18190000);
406 regmap_update_bits(ss->regmap_pextp[id], 0x00F8, GENMASK(31, 0),
407 0x01423342);
408 regmap_update_bits(ss->regmap_pextp[id], 0x00F4, GENMASK(31, 0),
409 0x80201F20);
410 regmap_update_bits(ss->regmap_pextp[id], 0x0030, GENMASK(31, 0),
411 0x00050C00);
412 regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0),
413 0x02002800);
developer089e8852022-09-28 14:43:46 +0800[diff] [blame]414 ndelay(1020);
developercfa104b2023-01-11 17:40:41 +0800[diff] [blame]415 regmap_update_bits(ss->regmap_pextp[id], 0x30B0, GENMASK(31, 0),
416 0x00000020);
417 regmap_update_bits(ss->regmap_pextp[id], 0x3028, GENMASK(31, 0),
418 0x00008A01);
419 regmap_update_bits(ss->regmap_pextp[id], 0x302C, GENMASK(31, 0),
420 0x0000A884);
421 regmap_update_bits(ss->regmap_pextp[id], 0x3024, GENMASK(31, 0),
422 0x00083002);
423 regmap_update_bits(ss->regmap_pextp[id], 0x3010, GENMASK(31, 0),
424 0x00022220);
425 regmap_update_bits(ss->regmap_pextp[id], 0x5064, GENMASK(31, 0),
426 0x0F020A01);
427 regmap_update_bits(ss->regmap_pextp[id], 0x50B4, GENMASK(31, 0),
428 0x06100600);
429 regmap_update_bits(ss->regmap_pextp[id], 0x3048, GENMASK(31, 0),
430 0x49664100);
431 regmap_update_bits(ss->regmap_pextp[id], 0x3050, GENMASK(31, 0),
432 0x00000000);
433 regmap_update_bits(ss->regmap_pextp[id], 0x3054, GENMASK(31, 0),
434 0x00000000);
435 regmap_update_bits(ss->regmap_pextp[id], 0x306C, GENMASK(31, 0),
436 0x00000F00);
437 regmap_update_bits(ss->regmap_pextp[id], 0xA060, GENMASK(31, 0),
438 0x00040000);
439 regmap_update_bits(ss->regmap_pextp[id], 0x90D0, GENMASK(31, 0),
440 0x00000001);
441 regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0),
442 0x0200E800);
developer089e8852022-09-28 14:43:46 +0800[diff] [blame]443 udelay(150);
developercfa104b2023-01-11 17:40:41 +0800[diff] [blame]444 regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0),
445 0x0200C111);
developer089e8852022-09-28 14:43:46 +0800[diff] [blame]446 ndelay(1020);
developercfa104b2023-01-11 17:40:41 +0800[diff] [blame]447 regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0),
448 0x0200C101);
developer089e8852022-09-28 14:43:46 +0800[diff] [blame]449 udelay(15);
developercfa104b2023-01-11 17:40:41 +0800[diff] [blame]450 regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0),
451 0x0202C111);
developer089e8852022-09-28 14:43:46 +0800[diff] [blame]452 ndelay(1020);
developercfa104b2023-01-11 17:40:41 +0800[diff] [blame]453 regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0),
454 0x0202C101);
developer089e8852022-09-28 14:43:46 +0800[diff] [blame]455 udelay(100);
developercfa104b2023-01-11 17:40:41 +0800[diff] [blame]456 regmap_update_bits(ss->regmap_pextp[id], 0x30B0, GENMASK(31, 0),
457 0x00000030);
458 regmap_update_bits(ss->regmap_pextp[id], 0x00F4, GENMASK(31, 0),
459 0x80201F00);
460 regmap_update_bits(ss->regmap_pextp[id], 0x3040, GENMASK(31, 0),
461 0x30000000);
developer089e8852022-09-28 14:43:46 +0800[diff] [blame]462 udelay(400);
463}
464
465void mtk_usxgmii_reset(struct mtk_xgmii *ss, int mac_id)
466{
467 struct mtk_eth *eth = ss->eth;
468 u32 id = mtk_mac2xgmii_id(eth, mac_id);
developer6aa00162023-03-20 11:56:51 +0800[diff] [blame^]469 u32 val = 0;
developer089e8852022-09-28 14:43:46 +0800[diff] [blame]470
developer8b6f2402022-11-28 13:42:34 +0800[diff] [blame]471 if (id >= MTK_MAX_DEVS || !eth->toprgu)
developer089e8852022-09-28 14:43:46 +0800[diff] [blame]472 return;
473
474 switch (mac_id) {
475 case MTK_GMAC2_ID:
developer6aa00162023-03-20 11:56:51 +0800[diff] [blame^]476 /* Enable software reset */
477 regmap_read(eth->toprgu, TOPRGU_SWSYSRST_EN, &val);
478 val |= SWSYSRST_XFI_PEXPT1_GRST |
479 SWSYSRST_XFI1_GRST;
480 regmap_write(eth->toprgu, TOPRGU_SWSYSRST_EN, val);
481
482 /* Assert USXGMII reset */
483 regmap_read(eth->toprgu, TOPRGU_SWSYSRST, &val);
484 val |= FIELD_PREP(SWSYSRST_UNLOCK_KEY, 0x88) |
485 SWSYSRST_XFI_PEXPT1_GRST |
486 SWSYSRST_XFI1_GRST;
487 regmap_write(eth->toprgu, TOPRGU_SWSYSRST, val);
488
489 udelay(100);
490
491 /* De-assert USXGMII reset */
492 regmap_read(eth->toprgu, TOPRGU_SWSYSRST, &val);
493 val |= FIELD_PREP(SWSYSRST_UNLOCK_KEY, 0x88);
494 val &= ~(SWSYSRST_XFI_PEXPT1_GRST |
495 SWSYSRST_XFI1_GRST);
496 regmap_write(eth->toprgu, TOPRGU_SWSYSRST, val);
497
498 /* Disable software reset */
499 regmap_read(eth->toprgu, TOPRGU_SWSYSRST_EN, &val);
500 val &= ~(SWSYSRST_XFI_PEXPT1_GRST |
501 SWSYSRST_XFI1_GRST);
502 regmap_write(eth->toprgu, TOPRGU_SWSYSRST_EN, val);
developer089e8852022-09-28 14:43:46 +0800[diff] [blame]503 break;
504 case MTK_GMAC3_ID:
developer6aa00162023-03-20 11:56:51 +0800[diff] [blame^]505 /* Enable software reset */
506 regmap_read(eth->toprgu, TOPRGU_SWSYSRST_EN, &val);
507 val |= SWSYSRST_XFI_PEXPT0_GRST |
508 SWSYSRST_XFI0_GRST;
509 regmap_write(eth->toprgu, TOPRGU_SWSYSRST_EN, val);
510
511 /* Assert USXGMII reset */
512 regmap_read(eth->toprgu, TOPRGU_SWSYSRST, &val);
513 val |= FIELD_PREP(SWSYSRST_UNLOCK_KEY, 0x88) |
514 SWSYSRST_XFI_PEXPT0_GRST |
515 SWSYSRST_XFI0_GRST;
516 regmap_write(eth->toprgu, TOPRGU_SWSYSRST, val);
517
518 udelay(100);
519
520 /* De-assert USXGMII reset */
521 regmap_read(eth->toprgu, TOPRGU_SWSYSRST, &val);
522 val |= FIELD_PREP(SWSYSRST_UNLOCK_KEY, 0x88);
523 val &= ~(SWSYSRST_XFI_PEXPT0_GRST |
524 SWSYSRST_XFI0_GRST);
525 regmap_write(eth->toprgu, TOPRGU_SWSYSRST, val);
526
527 /* Disable software reset */
528 regmap_read(eth->toprgu, TOPRGU_SWSYSRST_EN, &val);
529 val &= ~(SWSYSRST_XFI_PEXPT0_GRST |
530 SWSYSRST_XFI0_GRST);
531 regmap_write(eth->toprgu, TOPRGU_SWSYSRST_EN, val);
developer089e8852022-09-28 14:43:46 +0800[diff] [blame]532 break;
533 }
534
developer993b3852022-12-08 15:58:20 +0800[diff] [blame]535 mdelay(10);
developer089e8852022-09-28 14:43:46 +0800[diff] [blame]536}
537
538int mtk_usxgmii_setup_mode_an(struct mtk_xgmii *ss, int mac_id, int max_speed)
539{
540 if (mac_id < 0 || mac_id >= MTK_MAX_DEVS)
541 return -EINVAL;
542
543 if ((max_speed != SPEED_10000) && (max_speed != SPEED_5000))
544 return -EINVAL;
545
546 mtk_xfi_pll_enable(ss);
547 mtk_usxgmii_reset(ss, mac_id);
548 mtk_usxgmii_setup_phya_an_10000(ss, mac_id);
549
550 return 0;
551}
552
developercfa104b2023-01-11 17:40:41 +0800[diff] [blame]553int mtk_usxgmii_setup_mode_force(struct mtk_xgmii *ss, int mac_id,
554 const struct phylink_link_state *state)
developer089e8852022-09-28 14:43:46 +0800[diff] [blame]555{
556 if (mac_id < 0 || mac_id >= MTK_MAX_DEVS)
557 return -EINVAL;
558
developer089e8852022-09-28 14:43:46 +0800[diff] [blame]559 mtk_xfi_pll_enable(ss);
560 mtk_usxgmii_reset(ss, mac_id);
developercfa104b2023-01-11 17:40:41 +0800[diff] [blame]561 if (state->interface == PHY_INTERFACE_MODE_5GBASER)
562 mtk_usxgmii_setup_phya_force_5000(ss, mac_id);
563 else
564 mtk_usxgmii_setup_phya_force_10000(ss, mac_id);
developer089e8852022-09-28 14:43:46 +0800[diff] [blame]565
566 return 0;
567}
developer31d10662023-02-09 16:56:34 +0800[diff] [blame]568
569int mtk_dump_usxgmii(struct regmap *pmap, char *name, u32 offset, u32 range)
570{
571 unsigned int cur = offset;
572 unsigned int val1 = 0, val2 = 0, val3 = 0, val4 = 0;
573
574 pr_info("\n============ %s ============ pmap:%x\n", name, pmap);
575 while (cur < offset + range) {
576 regmap_read(pmap, cur, &val1);
577 regmap_read(pmap, cur + 0x4, &val2);
578 regmap_read(pmap, cur + 0x8, &val3);
579 regmap_read(pmap, cur + 0xc, &val4);
580 pr_info("0x%x: %08x %08x %08x %08x\n", cur,
581 val1, val2, val3, val4);
582 cur += 0x10;
583 }
584 return 0;
585}
586