Gitiles
Code Review Sign In
git01.mediatek.com / openwrt / feeds / mtk-openwrt-feeds / 8b6f2409cd5c8daebef9c1d07c3b36f6945dfa6e / . / target / linux / mediatek / files-5.4 / drivers / net / ethernet / mediatek / mtk_usxgmii.c
blob: bdd5231b08ed9bcfe8389797f59e1fe46a79141b [file] [log] [blame]
developer089e8852022-09-28 14:43:46 +0800[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0
2 *
3 * Copyright (c) 2022 MediaTek Inc.
4 * Author: Henry Yen <henry.yen@mediatek.com>
5 */
6
7#include <linux/mfd/syscon.h>
8#include <linux/of.h>
9#include <linux/regmap.h>
10#include "mtk_eth_soc.h"
11
12int mtk_usxgmii_init(struct mtk_xgmii *ss, struct device_node *r)
13{
14 struct device_node *np;
15 int i;
16
17 for (i = 0; i < MTK_MAX_DEVS; i++) {
18 np = of_parse_phandle(r, "mediatek,usxgmiisys", i);
19 if (!np)
20 break;
21
22 ss->regmap_usxgmii[i] = syscon_node_to_regmap(np);
23 if (IS_ERR(ss->regmap_usxgmii[i]))
24 return PTR_ERR(ss->regmap_usxgmii[i]);
developer089e8852022-09-28 14:43:46 +0800[diff] [blame]25 }
26
27 return 0;
28}
29
30int mtk_xfi_pextp_init(struct mtk_xgmii *ss, struct device_node *r)
31{
32 struct device_node *np;
33 int i;
34
35 for (i = 0; i < MTK_MAX_DEVS; i++) {
36 np = of_parse_phandle(r, "mediatek,xfi_pextp", i);
37 if (!np)
38 break;
39
40 ss->regmap_pextp[i] = syscon_node_to_regmap(np);
41 if (IS_ERR(ss->regmap_pextp[i]))
42 return PTR_ERR(ss->regmap_pextp[i]);
43 }
44
45 return 0;
46}
47
48int mtk_xfi_pll_init(struct mtk_xgmii *ss, struct device_node *r)
49{
50 struct device_node *np;
51
52 np = of_parse_phandle(r, "mediatek,xfi_pll", 0);
53 if (!np)
54 return -1;
55
56 ss->regmap_pll = syscon_node_to_regmap(np);
57 if (IS_ERR(ss->regmap_pll))
58 return PTR_ERR(ss->regmap_pll);
59
60 return 0;
61}
62
63int mtk_toprgu_init(struct mtk_eth *eth, struct device_node *r)
64{
65 struct device_node *np;
66
67 np = of_parse_phandle(r, "mediatek,toprgu", 0);
68 if (!np)
69 return -1;
70
71 eth->toprgu = syscon_node_to_regmap(np);
72 if (IS_ERR(eth->toprgu))
73 return PTR_ERR(eth->toprgu);
74
75 return 0;
76}
77
78int mtk_xfi_pll_enable(struct mtk_xgmii *ss)
79{
80 u32 val = 0;
81
82 if (!ss->regmap_pll)
83 return -EINVAL;
84
85 /* Add software workaround for USXGMII PLL TCL issue */
86 regmap_write(ss->regmap_pll, XFI_PLL_ANA_GLB8, RG_XFI_PLL_ANA_SWWA);
87
88 regmap_read(ss->regmap_pll, XFI_PLL_DIG_GLB8, &val);
89 val |= RG_XFI_PLL_EN;
90 regmap_write(ss->regmap_pll, XFI_PLL_DIG_GLB8, val);
91
92 return 0;
93}
94
95int mtk_mac2xgmii_id(struct mtk_eth *eth, int mac_id)
96{
97 u32 xgmii_id = mac_id;
98
99 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) {
100 switch (mac_id) {
101 case MTK_GMAC1_ID:
102 case MTK_GMAC2_ID:
103 xgmii_id = 1;
104 break;
105 case MTK_GMAC3_ID:
106 xgmii_id = 0;
107 break;
108 default:
109 pr_info("[%s] Warning: get illegal mac_id=%d !=!!!\n",
110 __func__, mac_id);
111 }
112 }
113
114 return xgmii_id;
115}
116
117void mtk_usxgmii_setup_phya_an_10000(struct mtk_xgmii *ss, int mac_id)
118{
119 u32 id = mtk_mac2xgmii_id(ss->eth, mac_id);
120
developer8b6f2402022-11-28 13:42:34 +0800[diff] [blame^]121 if (id >= MTK_MAX_DEVS ||
developer089e8852022-09-28 14:43:46 +0800[diff] [blame]122 !ss->regmap_usxgmii[id] || !ss->regmap_pextp[id])
123 return;
124
125 regmap_update_bits(ss->regmap_usxgmii[id], 0x810, GENMASK(31, 0), 0x000FFE6D);
126 regmap_update_bits(ss->regmap_usxgmii[id], 0x818, GENMASK(31, 0), 0x07B1EC7B);
127 regmap_update_bits(ss->regmap_usxgmii[id], 0x80C, GENMASK(31, 0), 0x30000000);
128 ndelay(1020);
129 regmap_update_bits(ss->regmap_usxgmii[id], 0x80C, GENMASK(31, 0), 0x10000000);
130 ndelay(1020);
131 regmap_update_bits(ss->regmap_usxgmii[id], 0x80C, GENMASK(31, 0), 0x00000000);
132
133 regmap_update_bits(ss->regmap_pextp[id], 0x9024, GENMASK(31, 0), 0x00C9071C);
134 regmap_update_bits(ss->regmap_pextp[id], 0x2020, GENMASK(31, 0), 0xAA8585AA);
135 regmap_update_bits(ss->regmap_pextp[id], 0x2030, GENMASK(31, 0), 0x0C020707);
136 regmap_update_bits(ss->regmap_pextp[id], 0x2034, GENMASK(31, 0), 0x0E050F0F);
137 regmap_update_bits(ss->regmap_pextp[id], 0x2040, GENMASK(31, 0), 0x00140032);
138 regmap_update_bits(ss->regmap_pextp[id], 0x50F0, GENMASK(31, 0), 0x00C014AA);
139 regmap_update_bits(ss->regmap_pextp[id], 0x50E0, GENMASK(31, 0), 0x3777C12B);
140 regmap_update_bits(ss->regmap_pextp[id], 0x506C, GENMASK(31, 0), 0x005F9CFF);
141 regmap_update_bits(ss->regmap_pextp[id], 0x5070, GENMASK(31, 0), 0x9D9DFAFA);
142 regmap_update_bits(ss->regmap_pextp[id], 0x5074, GENMASK(31, 0), 0x27273F3F);
143 regmap_update_bits(ss->regmap_pextp[id], 0x5078, GENMASK(31, 0), 0xA7883C68);
144 regmap_update_bits(ss->regmap_pextp[id], 0x507C, GENMASK(31, 0), 0x11661166);
145 regmap_update_bits(ss->regmap_pextp[id], 0x5080, GENMASK(31, 0), 0x0E000AAF);
146 regmap_update_bits(ss->regmap_pextp[id], 0x5084, GENMASK(31, 0), 0x08080D0D);
147 regmap_update_bits(ss->regmap_pextp[id], 0x5088, GENMASK(31, 0), 0x02030909);
148 regmap_update_bits(ss->regmap_pextp[id], 0x50E4, GENMASK(31, 0), 0x0C0C0000);
149 regmap_update_bits(ss->regmap_pextp[id], 0x50E8, GENMASK(31, 0), 0x04040000);
150 regmap_update_bits(ss->regmap_pextp[id], 0x50EC, GENMASK(31, 0), 0x0F0F0C06);
151 regmap_update_bits(ss->regmap_pextp[id], 0x50A8, GENMASK(31, 0), 0x506E8C8C);
152 regmap_update_bits(ss->regmap_pextp[id], 0x6004, GENMASK(31, 0), 0x18190000);
153 regmap_update_bits(ss->regmap_pextp[id], 0x00F8, GENMASK(31, 0), 0x01423342);
154 regmap_update_bits(ss->regmap_pextp[id], 0x00F4, GENMASK(31, 0), 0x80201F20);
155 regmap_update_bits(ss->regmap_pextp[id], 0x0030, GENMASK(31, 0), 0x00050C00);
156 regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x02002800);
157 ndelay(1020);
158 regmap_update_bits(ss->regmap_pextp[id], 0x30B0, GENMASK(31, 0), 0x00000020);
159 regmap_update_bits(ss->regmap_pextp[id], 0x3028, GENMASK(31, 0), 0x00008A01);
160 regmap_update_bits(ss->regmap_pextp[id], 0x302C, GENMASK(31, 0), 0x0000A884);
161 regmap_update_bits(ss->regmap_pextp[id], 0x3024, GENMASK(31, 0), 0x00083002);
162 regmap_update_bits(ss->regmap_pextp[id], 0x3010, GENMASK(31, 0), 0x00022220);
163 regmap_update_bits(ss->regmap_pextp[id], 0x5064, GENMASK(31, 0), 0x0F020A01);
164 regmap_update_bits(ss->regmap_pextp[id], 0x50B4, GENMASK(31, 0), 0x06100600);
165 regmap_update_bits(ss->regmap_pextp[id], 0x3048, GENMASK(31, 0), 0x40704000);
166 regmap_update_bits(ss->regmap_pextp[id], 0x3050, GENMASK(31, 0), 0xA8000000);
167 regmap_update_bits(ss->regmap_pextp[id], 0x3054, GENMASK(31, 0), 0x000000AA);
168 regmap_update_bits(ss->regmap_pextp[id], 0x306C, GENMASK(31, 0), 0x00000F00);
169 regmap_update_bits(ss->regmap_pextp[id], 0xA060, GENMASK(31, 0), 0x00040000);
170 regmap_update_bits(ss->regmap_pextp[id], 0x90D0, GENMASK(31, 0), 0x00000001);
171 regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x0200E800);
172 udelay(150);
173 regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x0200C111);
174 ndelay(1020);
175 regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x0200C101);
176 udelay(15);
177 regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x0202C111);
178 ndelay(1020);
179 regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x0202C101);
180 udelay(100);
181 regmap_update_bits(ss->regmap_pextp[id], 0x30B0, GENMASK(31, 0), 0x00000030);
182 regmap_update_bits(ss->regmap_pextp[id], 0x00F4, GENMASK(31, 0), 0x80201F00);
183 regmap_update_bits(ss->regmap_pextp[id], 0x3040, GENMASK(31, 0), 0x30000000);
184 udelay(400);
185}
186
187void mtk_usxgmii_setup_phya_force(struct mtk_xgmii *ss, int mac_id, int max_speed)
188{
189 unsigned int val;
190 u32 id = mtk_mac2xgmii_id(ss->eth, mac_id);
191
developer8b6f2402022-11-28 13:42:34 +0800[diff] [blame^]192 if (id >= MTK_MAX_DEVS ||
developer089e8852022-09-28 14:43:46 +0800[diff] [blame]193 !ss->regmap_usxgmii[id] || !ss->regmap_pextp[id])
194 return;
195
196 /* Decide USXGMII speed */
197 switch (max_speed) {
198 case SPEED_5000:
199 val = FIELD_PREP(RG_XFI_RX_MODE, RG_XFI_RX_MODE_5G) |
200 FIELD_PREP(RG_XFI_TX_MODE, RG_XFI_TX_MODE_5G);
201 break;
202 case SPEED_10000:
203 default:
204 val = FIELD_PREP(RG_XFI_RX_MODE, RG_XFI_RX_MODE_10G) |
205 FIELD_PREP(RG_XFI_TX_MODE, RG_XFI_TX_MODE_10G);
206 break;
207 };
208 regmap_write(ss->regmap_usxgmii[id], RG_PHY_TOP_SPEED_CTRL1, val);
209
210 /* Disable USXGMII AN mode */
211 regmap_read(ss->regmap_usxgmii[id], RG_PCS_AN_CTRL0, &val);
212 val &= ~RG_AN_ENABLE;
213 regmap_write(ss->regmap_usxgmii[id], RG_PCS_AN_CTRL0, val);
214
215 /* Gated USXGMII */
216 regmap_read(ss->regmap_usxgmii[id], RG_PHY_TOP_SPEED_CTRL1, &val);
217 val |= RG_MAC_CK_GATED;
218 regmap_write(ss->regmap_usxgmii[id], RG_PHY_TOP_SPEED_CTRL1, val);
219
220 ndelay(1020);
221
222 /* USXGMII force mode setting */
223 regmap_read(ss->regmap_usxgmii[id], RG_PHY_TOP_SPEED_CTRL1, &val);
224 val |= RG_USXGMII_RATE_UPDATE_MODE;
225 val |= RG_IF_FORCE_EN;
226 val |= FIELD_PREP(RG_RATE_ADAPT_MODE, RG_RATE_ADAPT_MODE_X1);
227 regmap_write(ss->regmap_usxgmii[id], RG_PHY_TOP_SPEED_CTRL1, val);
228
229 /* Un-gated USXGMII */
230 regmap_read(ss->regmap_usxgmii[id], RG_PHY_TOP_SPEED_CTRL1, &val);
231 val &= ~RG_MAC_CK_GATED;
232 regmap_write(ss->regmap_usxgmii[id], RG_PHY_TOP_SPEED_CTRL1, val);
233
234 ndelay(1020);
235
236 regmap_update_bits(ss->regmap_pextp[id], 0x9024, GENMASK(31, 0), 0x00C9071C);
237 regmap_update_bits(ss->regmap_pextp[id], 0x2020, GENMASK(31, 0), 0xAA8585AA);
238 regmap_update_bits(ss->regmap_pextp[id], 0x2030, GENMASK(31, 0), 0x0C020707);
239 regmap_update_bits(ss->regmap_pextp[id], 0x2034, GENMASK(31, 0), 0x0E050F0F);
240 regmap_update_bits(ss->regmap_pextp[id], 0x2040, GENMASK(31, 0), 0x00140032);
241 regmap_update_bits(ss->regmap_pextp[id], 0x50F0, GENMASK(31, 0), 0x00C014AA);
242 regmap_update_bits(ss->regmap_pextp[id], 0x50E0, GENMASK(31, 0), 0x3777C12B);
243 regmap_update_bits(ss->regmap_pextp[id], 0x506C, GENMASK(31, 0), 0x005F9CFF);
244 regmap_update_bits(ss->regmap_pextp[id], 0x5070, GENMASK(31, 0), 0x9D9DFAFA);
245 regmap_update_bits(ss->regmap_pextp[id], 0x5074, GENMASK(31, 0), 0x27273F3F);
246 regmap_update_bits(ss->regmap_pextp[id], 0x5078, GENMASK(31, 0), 0xA7883C68);
247 regmap_update_bits(ss->regmap_pextp[id], 0x507C, GENMASK(31, 0), 0x11661166);
248 regmap_update_bits(ss->regmap_pextp[id], 0x5080, GENMASK(31, 0), 0x0E000AAF);
249 regmap_update_bits(ss->regmap_pextp[id], 0x5084, GENMASK(31, 0), 0x08080D0D);
250 regmap_update_bits(ss->regmap_pextp[id], 0x5088, GENMASK(31, 0), 0x02030909);
251 regmap_update_bits(ss->regmap_pextp[id], 0x50E4, GENMASK(31, 0), 0x0C0C0000);
252 regmap_update_bits(ss->regmap_pextp[id], 0x50E8, GENMASK(31, 0), 0x04040000);
253 regmap_update_bits(ss->regmap_pextp[id], 0x50EC, GENMASK(31, 0), 0x0F0F0C06);
254 regmap_update_bits(ss->regmap_pextp[id], 0x50A8, GENMASK(31, 0), 0x506E8C8C);
255 regmap_update_bits(ss->regmap_pextp[id], 0x6004, GENMASK(31, 0), 0x18190000);
256 regmap_update_bits(ss->regmap_pextp[id], 0x00F8, GENMASK(31, 0), 0x01423342);
257 regmap_update_bits(ss->regmap_pextp[id], 0x00F4, GENMASK(31, 0), 0x80201F20);
258 regmap_update_bits(ss->regmap_pextp[id], 0x0030, GENMASK(31, 0), 0x00050C00);
259 regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x02002800);
260 ndelay(1020);
261 regmap_update_bits(ss->regmap_pextp[id], 0x30B0, GENMASK(31, 0), 0x00000020);
262 regmap_update_bits(ss->regmap_pextp[id], 0x3028, GENMASK(31, 0), 0x00008A01);
263 regmap_update_bits(ss->regmap_pextp[id], 0x302C, GENMASK(31, 0), 0x0000A884);
264 regmap_update_bits(ss->regmap_pextp[id], 0x3024, GENMASK(31, 0), 0x00083002);
265 regmap_update_bits(ss->regmap_pextp[id], 0x3010, GENMASK(31, 0), 0x00022220);
266 regmap_update_bits(ss->regmap_pextp[id], 0x5064, GENMASK(31, 0), 0x0F020A01);
267 regmap_update_bits(ss->regmap_pextp[id], 0x50B4, GENMASK(31, 0), 0x06100600);
268 regmap_update_bits(ss->regmap_pextp[id], 0x3048, GENMASK(31, 0), 0x49664100);
269 regmap_update_bits(ss->regmap_pextp[id], 0x3050, GENMASK(31, 0), 0x00000000);
270 regmap_update_bits(ss->regmap_pextp[id], 0x3054, GENMASK(31, 0), 0x00000000);
271 regmap_update_bits(ss->regmap_pextp[id], 0x306C, GENMASK(31, 0), 0x00000F00);
272 regmap_update_bits(ss->regmap_pextp[id], 0xA060, GENMASK(31, 0), 0x00040000);
273 regmap_update_bits(ss->regmap_pextp[id], 0x90D0, GENMASK(31, 0), 0x00000001);
274 regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x0200E800);
275 udelay(150);
276 regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x0200C111);
277 ndelay(1020);
278 regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x0200C101);
279 udelay(15);
280 regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x0202C111);
281 ndelay(1020);
282 regmap_update_bits(ss->regmap_pextp[id], 0x0070, GENMASK(31, 0), 0x0202C101);
283 udelay(100);
284 regmap_update_bits(ss->regmap_pextp[id], 0x30B0, GENMASK(31, 0), 0x00000030);
285 regmap_update_bits(ss->regmap_pextp[id], 0x00F4, GENMASK(31, 0), 0x80201F00);
286 regmap_update_bits(ss->regmap_pextp[id], 0x3040, GENMASK(31, 0), 0x30000000);
287 udelay(400);
288}
289
290void mtk_usxgmii_reset(struct mtk_xgmii *ss, int mac_id)
291{
292 struct mtk_eth *eth = ss->eth;
293 u32 id = mtk_mac2xgmii_id(eth, mac_id);
294
developer8b6f2402022-11-28 13:42:34 +0800[diff] [blame^]295 if (id >= MTK_MAX_DEVS || !eth->toprgu)
developer089e8852022-09-28 14:43:46 +0800[diff] [blame]296 return;
297
298 switch (mac_id) {
299 case MTK_GMAC2_ID:
300 regmap_update_bits(eth->toprgu, 0xFC, GENMASK(31, 0), 0x0000A004);
301 regmap_update_bits(eth->toprgu, 0x18, GENMASK(31, 0), 0x88F0A004);
302 regmap_update_bits(eth->toprgu, 0xFC, GENMASK(31, 0), 0x00000000);
303 regmap_update_bits(eth->toprgu, 0x18, GENMASK(31, 0), 0x88F00000);
304 regmap_update_bits(eth->toprgu, 0x18, GENMASK(31, 0), 0x00F00000);
305 break;
306 case MTK_GMAC3_ID:
307 regmap_update_bits(eth->toprgu, 0xFC, GENMASK(31, 0), 0x00005002);
308 regmap_update_bits(eth->toprgu, 0x18, GENMASK(31, 0), 0x88F05002);
309 regmap_update_bits(eth->toprgu, 0xFC, GENMASK(31, 0), 0x00000000);
310 regmap_update_bits(eth->toprgu, 0x18, GENMASK(31, 0), 0x88F00000);
311 regmap_update_bits(eth->toprgu, 0x18, GENMASK(31, 0), 0x00F00000);
312 break;
313 }
314
developera1913172022-10-21 10:05:59 +0800[diff] [blame]315 mdelay(1);
developer089e8852022-09-28 14:43:46 +0800[diff] [blame]316}
317
318int mtk_usxgmii_setup_mode_an(struct mtk_xgmii *ss, int mac_id, int max_speed)
319{
320 if (mac_id < 0 || mac_id >= MTK_MAX_DEVS)
321 return -EINVAL;
322
323 if ((max_speed != SPEED_10000) && (max_speed != SPEED_5000))
324 return -EINVAL;
325
326 mtk_xfi_pll_enable(ss);
327 mtk_usxgmii_reset(ss, mac_id);
328 mtk_usxgmii_setup_phya_an_10000(ss, mac_id);
329
330 return 0;
331}
332
333int mtk_usxgmii_setup_mode_force(struct mtk_xgmii *ss, int mac_id, int max_speed)
334{
335 if (mac_id < 0 || mac_id >= MTK_MAX_DEVS)
336 return -EINVAL;
337
338 if ((max_speed != SPEED_10000) && (max_speed != SPEED_5000))
339 return -EINVAL;
340
341 mtk_xfi_pll_enable(ss);
342 mtk_usxgmii_reset(ss, mac_id);
343 mtk_usxgmii_setup_phya_force(ss, mac_id, max_speed);
344
345 return 0;
346}