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developer24455dd2021-10-28 10:55:41 +08001/dts-v1/;
2#include "mt7981.dtsi"
3/ {
4 model = "MediaTek MT7981 RFB";
developera1c200a2022-03-04 20:10:00 +08005 compatible = "mediatek,mt7981-spim-snand-2500wan-gmac2-rfb";
developer24455dd2021-10-28 10:55:41 +08006 chosen {
7 bootargs = "console=ttyS0,115200n1 loglevel=8 \
8 earlycon=uart8250,mmio32,0x11002000";
9 };
10
11 memory {
12 // fpga ddr2: 128MB*2
13 reg = <0 0x40000000 0 0x10000000>;
14 };
15
developer7e6086a2022-05-18 14:50:36 +080016 gpio-keys {
17 compatible = "gpio-keys";
18 reset {
19 label = "reset";
20 linux,code = <KEY_RESTART>;
21 gpios = <&pio 1 GPIO_ACTIVE_LOW>;
22 };
23
24 wps {
25 label = "wps";
26 linux,code = <KEY_WPS_BUTTON>;
27 gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
28 };
29 };
30
developer63866c92021-11-15 12:05:13 +080031 nmbm_spim_nand {
developer24455dd2021-10-28 10:55:41 +080032 compatible = "generic,nmbm";
33
34 #address-cells = <1>;
35 #size-cells = <1>;
36
developer63866c92021-11-15 12:05:13 +080037 lower-mtd-device = <&spi_nand>;
developer24455dd2021-10-28 10:55:41 +080038 forced-create;
developer24455dd2021-10-28 10:55:41 +080039
40 partitions {
41 compatible = "fixed-partitions";
42 #address-cells = <1>;
43 #size-cells = <1>;
44
45 partition@0 {
46 label = "BL2";
47 reg = <0x00000 0x0100000>;
48 read-only;
49 };
50
51 partition@100000 {
52 label = "u-boot-env";
53 reg = <0x0100000 0x0080000>;
54 };
55
developer63866c92021-11-15 12:05:13 +080056 partition@180000 {
developer24455dd2021-10-28 10:55:41 +080057 label = "Factory";
58 reg = <0x180000 0x0200000>;
59 };
60
61 partition@380000 {
62 label = "FIP";
63 reg = <0x380000 0x0200000>;
64 };
65
66 partition@580000 {
67 label = "ubi";
68 reg = <0x580000 0x4000000>;
69 };
70 };
71 };
72};
73
74&uart0 {
75 status = "okay";
76};
77
78&watchdog {
79 status = "okay";
80};
81
82&eth {
83 status = "okay";
84
85 gmac0: mac@0 {
86 compatible = "mediatek,eth-mac";
87 reg = <0>;
88 phy-mode = "2500base-x";
89
90 fixed-link {
91 speed = <2500>;
92 full-duplex;
93 pause;
94 };
95 };
96
97 gmac1: mac@1 {
98 compatible = "mediatek,eth-mac";
99 reg = <1>;
100 phy-mode = "2500base-x";
developer760093a2023-03-15 10:28:10 +0800101 phy-handle = <&phy5>;
developer24455dd2021-10-28 10:55:41 +0800102 };
103
104 mdio: mdio-bus {
105 #address-cells = <1>;
106 #size-cells = <0>;
107
developer760093a2023-03-15 10:28:10 +0800108 reset-gpios = <&pio 14 1>;
109 reset-delay-us = <600>;
110
developer32805cd2022-01-06 17:08:06 +0800111 phy5: phy@5 {
developer760093a2023-03-15 10:28:10 +0800112 compatible = "ethernet-phy-ieee802.3-c45";
developer32805cd2022-01-06 17:08:06 +0800113 reg = <5>;
developer32805cd2022-01-06 17:08:06 +0800114 };
developer24455dd2021-10-28 10:55:41 +0800115
116 switch@0 {
117 compatible = "mediatek,mt7531";
118 reg = <31>;
119 reset-gpios = <&pio 39 0>;
developer24455dd2021-10-28 10:55:41 +0800120 ports {
121 #address-cells = <1>;
122 #size-cells = <0>;
123
124 port@0 {
125 reg = <0>;
126 label = "lan1";
127 };
128
129 port@1 {
130 reg = <1>;
131 label = "lan2";
132 };
133
134 port@2 {
135 reg = <2>;
136 label = "lan3";
137 };
138
139 port@3 {
140 reg = <3>;
141 label = "lan4";
142 };
143
144 port@6 {
145 reg = <6>;
146 label = "cpu";
147 ethernet = <&gmac0>;
148 phy-mode = "2500base-x";
149
150 fixed-link {
151 speed = <2500>;
152 full-duplex;
153 pause;
154 };
155 };
156 };
157 };
158 };
159};
160
161&hnat {
162 mtketh-wan = "eth1";
163 mtketh-lan = "lan";
164 mtketh-max-gmac = <2>;
165 status = "okay";
166};
167
developer63866c92021-11-15 12:05:13 +0800168&spi0 {
developer24455dd2021-10-28 10:55:41 +0800169 pinctrl-names = "default";
developer63866c92021-11-15 12:05:13 +0800170 pinctrl-0 = <&spi0_flash_pins>;
developer24455dd2021-10-28 10:55:41 +0800171 status = "okay";
developer63866c92021-11-15 12:05:13 +0800172 spi_nand: spi_nand@0 {
developer24455dd2021-10-28 10:55:41 +0800173 #address-cells = <1>;
174 #size-cells = <1>;
developer63866c92021-11-15 12:05:13 +0800175 compatible = "spi-nand";
developerd82d9fc2022-06-23 19:03:51 +0800176 spi-cal-enable;
177 spi-cal-mode = "read-data";
178 spi-cal-datalen = <7>;
179 spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>;
180 spi-cal-addrlen = <5>;
181 spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>;
developer63866c92021-11-15 12:05:13 +0800182 reg = <0>;
183 spi-max-frequency = <52000000>;
developer5fb80602023-05-02 18:54:53 +0800184 spi-tx-bus-width = <4>;
185 spi-rx-bus-width = <4>;
developer24455dd2021-10-28 10:55:41 +0800186 };
187};
188
189&spi1 {
190 pinctrl-names = "default";
191 pinctrl-0 = <&spic_pins>;
192 status = "disabled";
developerd82d9fc2022-06-23 19:03:51 +0800193
194 slb9670: slb9670@0 {
195 compatible = "infineon,slb9670";
196 reg = <0>; /* CE0 */
197 #address-cells = <1>;
198 #size-cells = <0>;
199 spi-cal-enable;
200 spi-cal-mode = "read-data";
201 spi-cal-datalen = <2>;
202 spi-cal-data = /bits/ 8 <0x00 0x1b>;
203 spi-max-frequency = <20000000>;
204 };
developer24455dd2021-10-28 10:55:41 +0800205};
206
207&pio {
208
developer63866c92021-11-15 12:05:13 +0800209 i2c_pins: i2c-pins-g0 {
210 mux {
211 function = "i2c";
212 groups = "i2c0_0";
213 };
214 };
215
216 pcm_pins: pcm-pins-g0 {
217 mux {
218 function = "pcm";
219 groups = "pcm";
220 };
221 };
222
223 pwm0_pin: pwm0-pin-g0 {
224 mux {
225 function = "pwm";
226 groups = "pwm0_0";
227 };
228 };
229
230 pwm1_pin: pwm1-pin-g0 {
231 mux {
232 function = "pwm";
233 groups = "pwm1_0";
234 };
235 };
236
237 pwm2_pin: pwm2-pin {
238 mux {
239 function = "pwm";
240 groups = "pwm2";
241 };
242 };
243
244 spi0_flash_pins: spi0-pins {
developer24455dd2021-10-28 10:55:41 +0800245 mux {
developer63866c92021-11-15 12:05:13 +0800246 function = "spi";
247 groups = "spi0", "spi0_wp_hold";
developer24455dd2021-10-28 10:55:41 +0800248 };
developer66b31fc2021-12-27 17:12:45 +0800249
250 conf-pu {
251 pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
252 drive-strength = <MTK_DRIVE_8mA>;
developerd4790ad2022-03-04 16:57:17 +0800253 bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
developer66b31fc2021-12-27 17:12:45 +0800254 };
255
256 conf-pd {
257 pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
258 drive-strength = <MTK_DRIVE_8mA>;
developerd4790ad2022-03-04 16:57:17 +0800259 bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
developer66b31fc2021-12-27 17:12:45 +0800260 };
developer24455dd2021-10-28 10:55:41 +0800261 };
262
263 spic_pins: spi1-pins {
264 mux {
265 function = "spi";
266 groups = "spi1_1";
267 };
268 };
developer63866c92021-11-15 12:05:13 +0800269
270 uart1_pins: uart1-pins-g1 {
271 mux {
272 function = "uart";
273 groups = "uart1_1";
274 };
275 };
276
277 uart2_pins: uart2-pins-g1 {
278 mux {
279 function = "uart";
280 groups = "uart2_1";
281 };
282 };
developer24455dd2021-10-28 10:55:41 +0800283};
284
285&xhci {
developer24455dd2021-10-28 10:55:41 +0800286 status = "okay";
287};