developer | 24455dd | 2021-10-28 10:55:41 +0800 | [diff] [blame] | 1 | /dts-v1/; |
| 2 | #include "mt7981.dtsi" |
| 3 | / { |
| 4 | model = "MediaTek MT7981 RFB"; |
developer | a1c200a | 2022-03-04 20:10:00 +0800 | [diff] [blame] | 5 | compatible = "mediatek,mt7981-spim-snand-2500wan-gmac2-rfb"; |
developer | 24455dd | 2021-10-28 10:55:41 +0800 | [diff] [blame] | 6 | chosen { |
| 7 | bootargs = "console=ttyS0,115200n1 loglevel=8 \ |
| 8 | earlycon=uart8250,mmio32,0x11002000"; |
| 9 | }; |
| 10 | |
| 11 | memory { |
| 12 | // fpga ddr2: 128MB*2 |
| 13 | reg = <0 0x40000000 0 0x10000000>; |
| 14 | }; |
| 15 | |
developer | 7e6086a | 2022-05-18 14:50:36 +0800 | [diff] [blame] | 16 | gpio-keys { |
| 17 | compatible = "gpio-keys"; |
| 18 | reset { |
| 19 | label = "reset"; |
| 20 | linux,code = <KEY_RESTART>; |
| 21 | gpios = <&pio 1 GPIO_ACTIVE_LOW>; |
| 22 | }; |
| 23 | |
| 24 | wps { |
| 25 | label = "wps"; |
| 26 | linux,code = <KEY_WPS_BUTTON>; |
| 27 | gpios = <&pio 0 GPIO_ACTIVE_HIGH>; |
| 28 | }; |
| 29 | }; |
| 30 | |
developer | 63866c9 | 2021-11-15 12:05:13 +0800 | [diff] [blame] | 31 | nmbm_spim_nand { |
developer | 24455dd | 2021-10-28 10:55:41 +0800 | [diff] [blame] | 32 | compatible = "generic,nmbm"; |
| 33 | |
| 34 | #address-cells = <1>; |
| 35 | #size-cells = <1>; |
| 36 | |
developer | 63866c9 | 2021-11-15 12:05:13 +0800 | [diff] [blame] | 37 | lower-mtd-device = <&spi_nand>; |
developer | 24455dd | 2021-10-28 10:55:41 +0800 | [diff] [blame] | 38 | forced-create; |
developer | 24455dd | 2021-10-28 10:55:41 +0800 | [diff] [blame] | 39 | |
| 40 | partitions { |
| 41 | compatible = "fixed-partitions"; |
| 42 | #address-cells = <1>; |
| 43 | #size-cells = <1>; |
| 44 | |
| 45 | partition@0 { |
| 46 | label = "BL2"; |
| 47 | reg = <0x00000 0x0100000>; |
| 48 | read-only; |
| 49 | }; |
| 50 | |
| 51 | partition@100000 { |
| 52 | label = "u-boot-env"; |
| 53 | reg = <0x0100000 0x0080000>; |
| 54 | }; |
| 55 | |
developer | 63866c9 | 2021-11-15 12:05:13 +0800 | [diff] [blame] | 56 | partition@180000 { |
developer | 24455dd | 2021-10-28 10:55:41 +0800 | [diff] [blame] | 57 | label = "Factory"; |
| 58 | reg = <0x180000 0x0200000>; |
| 59 | }; |
| 60 | |
| 61 | partition@380000 { |
| 62 | label = "FIP"; |
| 63 | reg = <0x380000 0x0200000>; |
| 64 | }; |
| 65 | |
| 66 | partition@580000 { |
| 67 | label = "ubi"; |
| 68 | reg = <0x580000 0x4000000>; |
| 69 | }; |
| 70 | }; |
| 71 | }; |
| 72 | }; |
| 73 | |
| 74 | &uart0 { |
| 75 | status = "okay"; |
| 76 | }; |
| 77 | |
| 78 | &watchdog { |
| 79 | status = "okay"; |
| 80 | }; |
| 81 | |
| 82 | ð { |
| 83 | status = "okay"; |
| 84 | |
| 85 | gmac0: mac@0 { |
| 86 | compatible = "mediatek,eth-mac"; |
| 87 | reg = <0>; |
| 88 | phy-mode = "2500base-x"; |
| 89 | |
| 90 | fixed-link { |
| 91 | speed = <2500>; |
| 92 | full-duplex; |
| 93 | pause; |
| 94 | }; |
| 95 | }; |
| 96 | |
| 97 | gmac1: mac@1 { |
| 98 | compatible = "mediatek,eth-mac"; |
| 99 | reg = <1>; |
| 100 | phy-mode = "2500base-x"; |
| 101 | |
| 102 | fixed-link { |
| 103 | speed = <2500>; |
| 104 | full-duplex; |
| 105 | pause; |
| 106 | }; |
| 107 | }; |
| 108 | |
| 109 | mdio: mdio-bus { |
| 110 | #address-cells = <1>; |
| 111 | #size-cells = <0>; |
| 112 | |
developer | 32805cd | 2022-01-06 17:08:06 +0800 | [diff] [blame] | 113 | phy5: phy@5 { |
| 114 | compatible = "ethernet-phy-id67c9.de0a"; |
| 115 | reg = <5>; |
| 116 | reset-gpios = <&pio 14 1>; |
developer | 8c5a08b | 2022-05-06 09:10:38 +0800 | [diff] [blame] | 117 | reset-assert-us = <600>; |
developer | 32805cd | 2022-01-06 17:08:06 +0800 | [diff] [blame] | 118 | reset-deassert-us = <20000>; |
| 119 | phy-mode = "2500base-x"; |
| 120 | }; |
developer | 24455dd | 2021-10-28 10:55:41 +0800 | [diff] [blame] | 121 | |
| 122 | switch@0 { |
| 123 | compatible = "mediatek,mt7531"; |
| 124 | reg = <31>; |
| 125 | reset-gpios = <&pio 39 0>; |
developer | 24455dd | 2021-10-28 10:55:41 +0800 | [diff] [blame] | 126 | ports { |
| 127 | #address-cells = <1>; |
| 128 | #size-cells = <0>; |
| 129 | |
| 130 | port@0 { |
| 131 | reg = <0>; |
| 132 | label = "lan1"; |
| 133 | }; |
| 134 | |
| 135 | port@1 { |
| 136 | reg = <1>; |
| 137 | label = "lan2"; |
| 138 | }; |
| 139 | |
| 140 | port@2 { |
| 141 | reg = <2>; |
| 142 | label = "lan3"; |
| 143 | }; |
| 144 | |
| 145 | port@3 { |
| 146 | reg = <3>; |
| 147 | label = "lan4"; |
| 148 | }; |
| 149 | |
| 150 | port@6 { |
| 151 | reg = <6>; |
| 152 | label = "cpu"; |
| 153 | ethernet = <&gmac0>; |
| 154 | phy-mode = "2500base-x"; |
| 155 | |
| 156 | fixed-link { |
| 157 | speed = <2500>; |
| 158 | full-duplex; |
| 159 | pause; |
| 160 | }; |
| 161 | }; |
| 162 | }; |
| 163 | }; |
| 164 | }; |
| 165 | }; |
| 166 | |
| 167 | &hnat { |
| 168 | mtketh-wan = "eth1"; |
| 169 | mtketh-lan = "lan"; |
| 170 | mtketh-max-gmac = <2>; |
| 171 | status = "okay"; |
| 172 | }; |
| 173 | |
developer | 63866c9 | 2021-11-15 12:05:13 +0800 | [diff] [blame] | 174 | &spi0 { |
developer | 24455dd | 2021-10-28 10:55:41 +0800 | [diff] [blame] | 175 | pinctrl-names = "default"; |
developer | 63866c9 | 2021-11-15 12:05:13 +0800 | [diff] [blame] | 176 | pinctrl-0 = <&spi0_flash_pins>; |
developer | 24455dd | 2021-10-28 10:55:41 +0800 | [diff] [blame] | 177 | status = "okay"; |
developer | 63866c9 | 2021-11-15 12:05:13 +0800 | [diff] [blame] | 178 | spi_nand: spi_nand@0 { |
developer | 24455dd | 2021-10-28 10:55:41 +0800 | [diff] [blame] | 179 | #address-cells = <1>; |
| 180 | #size-cells = <1>; |
developer | 63866c9 | 2021-11-15 12:05:13 +0800 | [diff] [blame] | 181 | compatible = "spi-nand"; |
developer | d82d9fc | 2022-06-23 19:03:51 +0800 | [diff] [blame^] | 182 | spi-cal-enable; |
| 183 | spi-cal-mode = "read-data"; |
| 184 | spi-cal-datalen = <7>; |
| 185 | spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>; |
| 186 | spi-cal-addrlen = <5>; |
| 187 | spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>; |
developer | 63866c9 | 2021-11-15 12:05:13 +0800 | [diff] [blame] | 188 | reg = <0>; |
| 189 | spi-max-frequency = <52000000>; |
| 190 | spi-tx-buswidth = <4>; |
| 191 | spi-rx-buswidth = <4>; |
developer | 24455dd | 2021-10-28 10:55:41 +0800 | [diff] [blame] | 192 | }; |
| 193 | }; |
| 194 | |
| 195 | &spi1 { |
| 196 | pinctrl-names = "default"; |
| 197 | pinctrl-0 = <&spic_pins>; |
| 198 | status = "disabled"; |
developer | d82d9fc | 2022-06-23 19:03:51 +0800 | [diff] [blame^] | 199 | |
| 200 | slb9670: slb9670@0 { |
| 201 | compatible = "infineon,slb9670"; |
| 202 | reg = <0>; /* CE0 */ |
| 203 | #address-cells = <1>; |
| 204 | #size-cells = <0>; |
| 205 | spi-cal-enable; |
| 206 | spi-cal-mode = "read-data"; |
| 207 | spi-cal-datalen = <2>; |
| 208 | spi-cal-data = /bits/ 8 <0x00 0x1b>; |
| 209 | spi-max-frequency = <20000000>; |
| 210 | }; |
developer | 24455dd | 2021-10-28 10:55:41 +0800 | [diff] [blame] | 211 | }; |
| 212 | |
| 213 | &pio { |
| 214 | |
developer | 63866c9 | 2021-11-15 12:05:13 +0800 | [diff] [blame] | 215 | i2c_pins: i2c-pins-g0 { |
| 216 | mux { |
| 217 | function = "i2c"; |
| 218 | groups = "i2c0_0"; |
| 219 | }; |
| 220 | }; |
| 221 | |
| 222 | pcm_pins: pcm-pins-g0 { |
| 223 | mux { |
| 224 | function = "pcm"; |
| 225 | groups = "pcm"; |
| 226 | }; |
| 227 | }; |
| 228 | |
| 229 | pwm0_pin: pwm0-pin-g0 { |
| 230 | mux { |
| 231 | function = "pwm"; |
| 232 | groups = "pwm0_0"; |
| 233 | }; |
| 234 | }; |
| 235 | |
| 236 | pwm1_pin: pwm1-pin-g0 { |
| 237 | mux { |
| 238 | function = "pwm"; |
| 239 | groups = "pwm1_0"; |
| 240 | }; |
| 241 | }; |
| 242 | |
| 243 | pwm2_pin: pwm2-pin { |
| 244 | mux { |
| 245 | function = "pwm"; |
| 246 | groups = "pwm2"; |
| 247 | }; |
| 248 | }; |
| 249 | |
| 250 | spi0_flash_pins: spi0-pins { |
developer | 24455dd | 2021-10-28 10:55:41 +0800 | [diff] [blame] | 251 | mux { |
developer | 63866c9 | 2021-11-15 12:05:13 +0800 | [diff] [blame] | 252 | function = "spi"; |
| 253 | groups = "spi0", "spi0_wp_hold"; |
developer | 24455dd | 2021-10-28 10:55:41 +0800 | [diff] [blame] | 254 | }; |
developer | 66b31fc | 2021-12-27 17:12:45 +0800 | [diff] [blame] | 255 | |
| 256 | conf-pu { |
| 257 | pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; |
| 258 | drive-strength = <MTK_DRIVE_8mA>; |
developer | d4790ad | 2022-03-04 16:57:17 +0800 | [diff] [blame] | 259 | bias-pull-up = <MTK_PUPD_SET_R1R0_11>; |
developer | 66b31fc | 2021-12-27 17:12:45 +0800 | [diff] [blame] | 260 | }; |
| 261 | |
| 262 | conf-pd { |
| 263 | pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; |
| 264 | drive-strength = <MTK_DRIVE_8mA>; |
developer | d4790ad | 2022-03-04 16:57:17 +0800 | [diff] [blame] | 265 | bias-pull-down = <MTK_PUPD_SET_R1R0_11>; |
developer | 66b31fc | 2021-12-27 17:12:45 +0800 | [diff] [blame] | 266 | }; |
developer | 24455dd | 2021-10-28 10:55:41 +0800 | [diff] [blame] | 267 | }; |
| 268 | |
| 269 | spic_pins: spi1-pins { |
| 270 | mux { |
| 271 | function = "spi"; |
| 272 | groups = "spi1_1"; |
| 273 | }; |
| 274 | }; |
developer | 63866c9 | 2021-11-15 12:05:13 +0800 | [diff] [blame] | 275 | |
| 276 | uart1_pins: uart1-pins-g1 { |
| 277 | mux { |
| 278 | function = "uart"; |
| 279 | groups = "uart1_1"; |
| 280 | }; |
| 281 | }; |
| 282 | |
| 283 | uart2_pins: uart2-pins-g1 { |
| 284 | mux { |
| 285 | function = "uart"; |
| 286 | groups = "uart2_1"; |
| 287 | }; |
| 288 | }; |
developer | 24455dd | 2021-10-28 10:55:41 +0800 | [diff] [blame] | 289 | }; |
| 290 | |
| 291 | &xhci { |
developer | 24455dd | 2021-10-28 10:55:41 +0800 | [diff] [blame] | 292 | status = "okay"; |
| 293 | }; |