blob: 904d52970944ae4036b504b2e34b08ee942b7a3e [file] [log] [blame]
developer24455dd2021-10-28 10:55:41 +08001/dts-v1/;
2#include "mt7981.dtsi"
3/ {
4 model = "MediaTek MT7981 RFB";
developer63866c92021-11-15 12:05:13 +08005 compatible = "mediatek,mt7981-spim-snand-rfb";
developer24455dd2021-10-28 10:55:41 +08006 chosen {
7 bootargs = "console=ttyS0,115200n1 loglevel=8 \
8 earlycon=uart8250,mmio32,0x11002000";
9 };
10
11 memory {
12 // fpga ddr2: 128MB*2
13 reg = <0 0x40000000 0 0x10000000>;
14 };
15
developer63866c92021-11-15 12:05:13 +080016 nmbm_spim_nand {
developer24455dd2021-10-28 10:55:41 +080017 compatible = "generic,nmbm";
18
19 #address-cells = <1>;
20 #size-cells = <1>;
21
developer63866c92021-11-15 12:05:13 +080022 lower-mtd-device = <&spi_nand>;
developer24455dd2021-10-28 10:55:41 +080023 forced-create;
developer24455dd2021-10-28 10:55:41 +080024
25 partitions {
26 compatible = "fixed-partitions";
27 #address-cells = <1>;
28 #size-cells = <1>;
29
30 partition@0 {
31 label = "BL2";
32 reg = <0x00000 0x0100000>;
33 read-only;
34 };
35
36 partition@100000 {
37 label = "u-boot-env";
38 reg = <0x0100000 0x0080000>;
39 };
40
developer63866c92021-11-15 12:05:13 +080041 partition@180000 {
developer24455dd2021-10-28 10:55:41 +080042 label = "Factory";
43 reg = <0x180000 0x0200000>;
44 };
45
46 partition@380000 {
47 label = "FIP";
48 reg = <0x380000 0x0200000>;
49 };
50
51 partition@580000 {
52 label = "ubi";
53 reg = <0x580000 0x4000000>;
54 };
55 };
56 };
57};
58
59&uart0 {
60 status = "okay";
61};
62
63&watchdog {
64 status = "okay";
65};
66
67&eth {
68 status = "okay";
69
70 gmac0: mac@0 {
71 compatible = "mediatek,eth-mac";
72 reg = <0>;
73 phy-mode = "2500base-x";
74
75 fixed-link {
76 speed = <2500>;
77 full-duplex;
78 pause;
79 };
80 };
81
82 gmac1: mac@1 {
83 compatible = "mediatek,eth-mac";
84 reg = <1>;
85 phy-mode = "2500base-x";
86
87 fixed-link {
88 speed = <2500>;
89 full-duplex;
90 pause;
91 };
92 };
93
94 mdio: mdio-bus {
95 #address-cells = <1>;
96 #size-cells = <0>;
97
developer32805cd2022-01-06 17:08:06 +080098 phy5: phy@5 {
99 compatible = "ethernet-phy-id67c9.de0a";
100 reg = <5>;
101 reset-gpios = <&pio 14 1>;
102 reset-deassert-us = <20000>;
103 phy-mode = "2500base-x";
104 };
developer24455dd2021-10-28 10:55:41 +0800105
106 switch@0 {
107 compatible = "mediatek,mt7531";
108 reg = <31>;
109 reset-gpios = <&pio 39 0>;
developer24455dd2021-10-28 10:55:41 +0800110 ports {
111 #address-cells = <1>;
112 #size-cells = <0>;
113
114 port@0 {
115 reg = <0>;
116 label = "lan1";
117 };
118
119 port@1 {
120 reg = <1>;
121 label = "lan2";
122 };
123
124 port@2 {
125 reg = <2>;
126 label = "lan3";
127 };
128
129 port@3 {
130 reg = <3>;
131 label = "lan4";
132 };
133
134 port@6 {
135 reg = <6>;
136 label = "cpu";
137 ethernet = <&gmac0>;
138 phy-mode = "2500base-x";
139
140 fixed-link {
141 speed = <2500>;
142 full-duplex;
143 pause;
144 };
145 };
146 };
147 };
148 };
149};
150
151&hnat {
152 mtketh-wan = "eth1";
153 mtketh-lan = "lan";
154 mtketh-max-gmac = <2>;
155 status = "okay";
156};
157
developer63866c92021-11-15 12:05:13 +0800158&spi0 {
developer24455dd2021-10-28 10:55:41 +0800159 pinctrl-names = "default";
developer63866c92021-11-15 12:05:13 +0800160 pinctrl-0 = <&spi0_flash_pins>;
developer24455dd2021-10-28 10:55:41 +0800161 status = "okay";
developer63866c92021-11-15 12:05:13 +0800162 spi_nand: spi_nand@0 {
developer24455dd2021-10-28 10:55:41 +0800163 #address-cells = <1>;
164 #size-cells = <1>;
developer63866c92021-11-15 12:05:13 +0800165 compatible = "spi-nand";
166 reg = <0>;
167 spi-max-frequency = <52000000>;
168 spi-tx-buswidth = <4>;
169 spi-rx-buswidth = <4>;
developer24455dd2021-10-28 10:55:41 +0800170 };
171};
172
173&spi1 {
174 pinctrl-names = "default";
175 pinctrl-0 = <&spic_pins>;
176 status = "disabled";
177};
178
179&pio {
180
developer63866c92021-11-15 12:05:13 +0800181 i2c_pins: i2c-pins-g0 {
182 mux {
183 function = "i2c";
184 groups = "i2c0_0";
185 };
186 };
187
188 pcm_pins: pcm-pins-g0 {
189 mux {
190 function = "pcm";
191 groups = "pcm";
192 };
193 };
194
195 pwm0_pin: pwm0-pin-g0 {
196 mux {
197 function = "pwm";
198 groups = "pwm0_0";
199 };
200 };
201
202 pwm1_pin: pwm1-pin-g0 {
203 mux {
204 function = "pwm";
205 groups = "pwm1_0";
206 };
207 };
208
209 pwm2_pin: pwm2-pin {
210 mux {
211 function = "pwm";
212 groups = "pwm2";
213 };
214 };
215
216 spi0_flash_pins: spi0-pins {
developer24455dd2021-10-28 10:55:41 +0800217 mux {
developer63866c92021-11-15 12:05:13 +0800218 function = "spi";
219 groups = "spi0", "spi0_wp_hold";
developer24455dd2021-10-28 10:55:41 +0800220 };
developer66b31fc2021-12-27 17:12:45 +0800221
222 conf-pu {
223 pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
224 drive-strength = <MTK_DRIVE_8mA>;
225 bias-pull-down = <MTK_PUPD_SET_R1R0_00>;
226 };
227
228 conf-pd {
229 pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
230 drive-strength = <MTK_DRIVE_8mA>;
231 bias-pull-down = <MTK_PUPD_SET_R1R0_00>;
232 };
developer24455dd2021-10-28 10:55:41 +0800233 };
234
235 spic_pins: spi1-pins {
236 mux {
237 function = "spi";
238 groups = "spi1_1";
239 };
240 };
developer63866c92021-11-15 12:05:13 +0800241
242 uart1_pins: uart1-pins-g1 {
243 mux {
244 function = "uart";
245 groups = "uart1_1";
246 };
247 };
248
249 uart2_pins: uart2-pins-g1 {
250 mux {
251 function = "uart";
252 groups = "uart2_1";
253 };
254 };
developer24455dd2021-10-28 10:55:41 +0800255};
256
257&xhci {
developer24455dd2021-10-28 10:55:41 +0800258 status = "okay";
259};