blob: 920deaa8fd8fbabdc09539767a8bd1c8dd647d4b [file] [log] [blame]
developer24455dd2021-10-28 10:55:41 +08001/dts-v1/;
2#include "mt7981.dtsi"
3/ {
4 model = "MediaTek MT7981 RFB";
developer63866c92021-11-15 12:05:13 +08005 compatible = "mediatek,mt7981-spim-snand-rfb";
developer24455dd2021-10-28 10:55:41 +08006 chosen {
7 bootargs = "console=ttyS0,115200n1 loglevel=8 \
8 earlycon=uart8250,mmio32,0x11002000";
9 };
10
11 memory {
12 // fpga ddr2: 128MB*2
13 reg = <0 0x40000000 0 0x10000000>;
14 };
15
developer63866c92021-11-15 12:05:13 +080016 nmbm_spim_nand {
developer24455dd2021-10-28 10:55:41 +080017 compatible = "generic,nmbm";
18
19 #address-cells = <1>;
20 #size-cells = <1>;
21
developer63866c92021-11-15 12:05:13 +080022 lower-mtd-device = <&spi_nand>;
developer24455dd2021-10-28 10:55:41 +080023 forced-create;
developer24455dd2021-10-28 10:55:41 +080024
25 partitions {
26 compatible = "fixed-partitions";
27 #address-cells = <1>;
28 #size-cells = <1>;
29
30 partition@0 {
31 label = "BL2";
32 reg = <0x00000 0x0100000>;
33 read-only;
34 };
35
36 partition@100000 {
37 label = "u-boot-env";
38 reg = <0x0100000 0x0080000>;
39 };
40
developer63866c92021-11-15 12:05:13 +080041 partition@180000 {
developer24455dd2021-10-28 10:55:41 +080042 label = "Factory";
43 reg = <0x180000 0x0200000>;
44 };
45
46 partition@380000 {
47 label = "FIP";
48 reg = <0x380000 0x0200000>;
49 };
50
51 partition@580000 {
52 label = "ubi";
53 reg = <0x580000 0x4000000>;
54 };
55 };
56 };
57};
58
59&uart0 {
60 status = "okay";
61};
62
63&watchdog {
64 status = "okay";
65};
66
67&eth {
68 status = "okay";
69
70 gmac0: mac@0 {
71 compatible = "mediatek,eth-mac";
72 reg = <0>;
73 phy-mode = "2500base-x";
74
75 fixed-link {
76 speed = <2500>;
77 full-duplex;
78 pause;
79 };
80 };
81
82 gmac1: mac@1 {
83 compatible = "mediatek,eth-mac";
84 reg = <1>;
85 phy-mode = "2500base-x";
86
87 fixed-link {
88 speed = <2500>;
89 full-duplex;
90 pause;
91 };
92 };
93
94 mdio: mdio-bus {
95 #address-cells = <1>;
96 #size-cells = <0>;
97
developer63866c92021-11-15 12:05:13 +080098 phy5: phy@5 {
developer24455dd2021-10-28 10:55:41 +080099 compatible = "ethernet-phy-id67c9.de0a";
developer63866c92021-11-15 12:05:13 +0800100 reg = <5>;
developer24455dd2021-10-28 10:55:41 +0800101 phy-mode = "2500base-x";
102 };
103
104 switch@0 {
105 compatible = "mediatek,mt7531";
106 reg = <31>;
107 reset-gpios = <&pio 39 0>;
developer24455dd2021-10-28 10:55:41 +0800108 ports {
109 #address-cells = <1>;
110 #size-cells = <0>;
111
112 port@0 {
113 reg = <0>;
114 label = "lan1";
115 };
116
117 port@1 {
118 reg = <1>;
119 label = "lan2";
120 };
121
122 port@2 {
123 reg = <2>;
124 label = "lan3";
125 };
126
127 port@3 {
128 reg = <3>;
129 label = "lan4";
130 };
131
132 port@6 {
133 reg = <6>;
134 label = "cpu";
135 ethernet = <&gmac0>;
136 phy-mode = "2500base-x";
137
138 fixed-link {
139 speed = <2500>;
140 full-duplex;
141 pause;
142 };
143 };
144 };
145 };
146 };
147};
148
149&hnat {
150 mtketh-wan = "eth1";
151 mtketh-lan = "lan";
152 mtketh-max-gmac = <2>;
153 status = "okay";
154};
155
developer63866c92021-11-15 12:05:13 +0800156&spi0 {
developer24455dd2021-10-28 10:55:41 +0800157 pinctrl-names = "default";
developer63866c92021-11-15 12:05:13 +0800158 pinctrl-0 = <&spi0_flash_pins>;
developer24455dd2021-10-28 10:55:41 +0800159 status = "okay";
developer63866c92021-11-15 12:05:13 +0800160 spi_nand: spi_nand@0 {
developer24455dd2021-10-28 10:55:41 +0800161 #address-cells = <1>;
162 #size-cells = <1>;
developer63866c92021-11-15 12:05:13 +0800163 compatible = "spi-nand";
164 reg = <0>;
165 spi-max-frequency = <52000000>;
166 spi-tx-buswidth = <4>;
167 spi-rx-buswidth = <4>;
developer24455dd2021-10-28 10:55:41 +0800168 };
169};
170
171&spi1 {
172 pinctrl-names = "default";
173 pinctrl-0 = <&spic_pins>;
174 status = "disabled";
175};
176
177&pio {
178
developer63866c92021-11-15 12:05:13 +0800179 i2c_pins: i2c-pins-g0 {
180 mux {
181 function = "i2c";
182 groups = "i2c0_0";
183 };
184 };
185
186 pcm_pins: pcm-pins-g0 {
187 mux {
188 function = "pcm";
189 groups = "pcm";
190 };
191 };
192
193 pwm0_pin: pwm0-pin-g0 {
194 mux {
195 function = "pwm";
196 groups = "pwm0_0";
197 };
198 };
199
200 pwm1_pin: pwm1-pin-g0 {
201 mux {
202 function = "pwm";
203 groups = "pwm1_0";
204 };
205 };
206
207 pwm2_pin: pwm2-pin {
208 mux {
209 function = "pwm";
210 groups = "pwm2";
211 };
212 };
213
214 spi0_flash_pins: spi0-pins {
developer24455dd2021-10-28 10:55:41 +0800215 mux {
developer63866c92021-11-15 12:05:13 +0800216 function = "spi";
217 groups = "spi0", "spi0_wp_hold";
developer24455dd2021-10-28 10:55:41 +0800218 };
219 };
220
221 spic_pins: spi1-pins {
222 mux {
223 function = "spi";
224 groups = "spi1_1";
225 };
226 };
developer63866c92021-11-15 12:05:13 +0800227
228 uart1_pins: uart1-pins-g1 {
229 mux {
230 function = "uart";
231 groups = "uart1_1";
232 };
233 };
234
235 uart2_pins: uart2-pins-g1 {
236 mux {
237 function = "uart";
238 groups = "uart2_1";
239 };
240 };
developer24455dd2021-10-28 10:55:41 +0800241};
242
243&xhci {
developer63866c92021-11-15 12:05:13 +0800244 mediatek,u3p-dis-msk = <0x0>;
245 phys = <&u2port0 PHY_TYPE_USB2>,
246 <&u3port0 PHY_TYPE_USB3>;
developer24455dd2021-10-28 10:55:41 +0800247 status = "okay";
248};