Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / e4f41ae865323d12a241b2421d61e8f34dec2bac / arch / riscv / dts
  1. 4ac36bb sunxi: dts: arm: add T113s/D1 DT files from Linux-v6.6-rc6 by Andre Przywara · Thu Oct 19 15:45:32 2023 +0100
  2. 9d17cdb riscv: dts: binman: add condition for opensbi os boot by Randolph · Thu Oct 12 14:35:05 2023 +0800
  3. 5a3b018 riscv: binman: Fix compilation error by Mayuresh Chitale · Wed Oct 11 21:00:20 2023 +0530
  4. 6c9c5ba configs: andes: add vender prefix for target name by Randolph · Mon Sep 25 17:24:51 2023 +0800
  5. b29a747 Merge branch 'next' by Tom Rini · Mon Oct 02 10:55:44 2023 -0400
  6. b112ed5 riscv: dts: starfive: generate u-boot-spl.bin.normal.out by Heinrich Schuchardt · Sun Sep 17 13:47:31 2023 +0200
  7. 42fa87e riscv: jh7110: enable riscv,timer in the device tree by Torsten Duwe · Mon Aug 14 18:05:33 2023 +0200
  8. 021faf7 riscv: dts: starfive: Enable pcie0 dts node by Minda Chen · Mon Aug 07 16:53:36 2023 +0800
  9. 23dfd81 riscv: dts: starfive: Enable PCIe host controller by Mason Huo · Tue Jul 25 17:46:50 2023 +0800
  10. 1345c9e riscv: dts: jh7110: Add clock source from PLL by Xingyu Wu · Fri Jul 07 18:50:09 2023 +0800
  11. 7ae81bb riscv: dts: jh7110: Add PLL clock controller node by Xingyu Wu · Fri Jul 07 18:50:08 2023 +0800
  12. e3a02bd riscv: dts: t-head: Add basic device tree for Sipeed Lichee PI 4A board by Yixun Lan · Sat Jul 08 19:24:33 2023 +0800
  13. d426942 riscv: dts: starfive: Add support eeprom device tree node by Yanhong Wang · Thu Jun 15 17:36:49 2023 +0800
  14. 438ab1e riscv: dts: jh7110: Combine the board device tree files of 1.2A and 1.3B by Yanhong Wang · Thu Jun 15 17:36:45 2023 +0800
  15. 7f63bd9 riscv: dts: jh7110: Add ethernet device tree nodes by Yanhong Wang · Thu Jun 15 17:36:44 2023 +0800
  16. 3978599 riscv: dts: sync mpfs-icicle devicetree with linux by Conor Dooley · Thu Jun 15 11:12:43 2023 +0100
  17. 75809d9 riscv: dts: drop microchip from dts filenames by Conor Dooley · Thu Jun 15 11:12:42 2023 +0100
  18. 5efc934 riscv: dts: jh7110: Add initial StarFive VisionFive v2 board device tree by Yanhong Wang · Wed Mar 29 11:42:23 2023 +0800
  19. 94817bf riscv: dts: jh7110: Add initial u-boot device tree by Yanhong Wang · Wed Mar 29 11:42:22 2023 +0800
  20. 96c3eb72 riscv: dts: jh7110: Add initial StarFive JH7110 device tree by Yanhong Wang · Wed Mar 29 11:42:21 2023 +0800
  21. 1c0b887 Merge tag 'v2023.04-rc3' into next by Tom Rini · Mon Feb 27 17:28:21 2023 -0500
  22. ddcdd94 riscv: binman: Add help message for missing blobs by Rick Chen · Fri Feb 17 16:57:01 2023 +0800
  23. 249ce73 riscv: Rename Andes cpu and board names by Leo Yu-Chi Liang · Tue Feb 14 20:42:49 2023 +0800
  24. 5cc6b3f riscv: ae350: dts: Update L2 cache compatible string by Yu Chien Peter Lin · Mon Feb 06 16:10:48 2023 +0800
  25. d3a98cb dm: dts: Convert driver model tags to use new schema by Simon Glass · Mon Feb 13 08:56:33 2023 -0700
  26. e828edd riscv: dts: fix the mpfs's reference clock frequency by Conor Dooley · Tue Oct 25 08:58:49 2022 +0100
  27. da2a6d0 riscv: dts: Add QSPI NAND device node by Padmarao Begari · Thu Oct 27 11:32:00 2022 +0530
  28. c66a3b2 riscv: dts: Update memory configuration by Padmarao Begari · Thu Oct 27 11:31:59 2022 +0530
  29. 739cd6f riscv: Rename Andes PLIC to PLICSW by Yu Chien Peter Lin · Tue Oct 25 23:03:50 2022 +0800
  30. 72cc538 Rename CONFIG_SYS_TEXT_BASE to CONFIG_TEXT_BASE by Simon Glass · Thu Oct 20 18:22:39 2022 -0600
  31. ebe3b23 riscv: dts: sifive: Synchronize FU740 and Unmatched DT by Icenowy Zheng · Thu Aug 25 16:11:19 2022 +0800
  32. 13d7170 dt-bindings: clock: sifive: sync FU740 PRCI clock binding header by Icenowy Zheng · Thu Aug 25 16:11:18 2022 +0800
  33. f781746 riscv: dts: Sync important Unmatched pmic and qspi0 changes from Linux by Jessica Clarke · Fri Aug 12 18:50:03 2022 +0100
  34. 5b845a4 k210: dts: align plic node with Linux by Niklas Cassel · Tue Mar 01 10:35:42 2022 +0000
  35. b2c0bb4 k210: dts: align fpioa node with Linux by Damien Le Moal · Tue Mar 01 10:35:41 2022 +0000
  36. 0a876d7 k210: dts: add missing power bus clocks by Damien Le Moal · Tue Mar 01 10:35:40 2022 +0000
  37. 6e5a8b7 k210: use the board vendor name rather than the marketing name by Damien Le Moal · Tue Mar 01 10:35:39 2022 +0000
  38. c8481ef dts: automatically build necessary .dtb files by Rasmus Villemoes · Mon Jan 10 14:34:41 2022 +0100
  39. bd07fb4 riscv: qemu: Split devicetree files for qemu_riscv32/64 by Simon Glass · Thu Dec 16 20:59:12 2021 -0700
  40. f50fad6 riscv: Support booting SiFive Unmatched from SPI. by Thomas Skibo · Wed Nov 24 14:32:09 2021 -0800
  41. b56e2fd riscv: dts: Split Microchip device tree by Padmarao Begari · Wed Nov 17 18:21:17 2021 +0530
  42. dc35df4 riscv: Remove OF_PRIOR_STAGE from RISC-V boards by Ilias Apalodimas · Tue Oct 12 00:00:13 2021 +0300
  43. 288ad1f board: sifive: drop stuff related to unmatched revision 1 by Zong Li · Tue Jul 20 14:26:08 2021 +0800
  44. babf1cb riscv: dts: add OpenPiton RISC-V board dts support by Tianrui Wei · Wed Jul 07 15:48:22 2021 +0800
  45. bab770a riscv: dts: add dts for unmatched rev1 by Zong Li · Wed Jun 30 23:23:49 2021 +0800
  46. 9627a8e riscv: sifive: fu740: Support i2c in spl by Zong Li · Wed Jun 30 23:23:47 2021 +0800
  47. 2ef594d board: riscv: add openpiton-riscv64 SoC support by Tianrui Wei · Thu Jul 01 12:54:19 2021 +0800
  48. d3e8b73 Merge tag 'v2021.07-rc5' into next by Tom Rini · Mon Jun 28 16:22:13 2021 -0400
  49. e6638b4 k210: dts: Set PLL1 to the same rate as PLL0 by Sean Anderson · Fri Jun 11 00:16:15 2021 -0400
  50. 2114b47 riscv: ae350: dts: Add missing "u-boot, dm-spl" for SPL config by Bin Meng · Fri Jun 04 13:51:13 2021 +0800
  51. 85741a2 riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bit by Bin Meng · Fri Jun 04 13:51:12 2021 +0800
  52. cd00421 riscv: ae350: dts: Remove the unnecessary #address-cells in plic nodes by Bin Meng · Fri Jun 04 13:51:11 2021 +0800
  53. 996068b riscv: ae350: dts: Remove the unnecessary space in bootargs by Bin Meng · Fri Jun 04 13:51:10 2021 +0800
  54. c907594 riscv: ae350: dts: Add SPDX license header by Bin Meng · Fri Jun 04 13:51:09 2021 +0800
  55. e552af3 riscv: dts: add SiFive Unmatched board support by Green Wan · Thu May 27 06:52:12 2021 -0700
  56. 06a3e40 riscv: dts: add fu740 support by Green Wan · Thu May 27 06:52:11 2021 -0700
  57. 6b977a4 riscv: ae350: Switch to use binman to generate u-boot.itb by Bin Meng · Mon May 10 20:23:40 2021 +0800
  58. 1255ab8 riscv: qemu: Switch to use binman to generate u-boot.itb by Bin Meng · Mon May 10 20:23:39 2021 +0800
  59. eada910 riscv: dts: Sort build targets in alphabetical order by Bin Meng · Mon May 10 20:23:38 2021 +0800
  60. ced2097 riscv: sifive: unleashed: Switch to use binman to generate u-boot.itb by Bin Meng · Mon May 10 20:23:35 2021 +0800
  61. 72422b9 riscv: Don't reserve AI ram in k210 dts by Sean Anderson · Thu Apr 08 22:13:13 2021 -0400
  62. b23d757 riscv: k210: Use AI as the parent clock of aisram, not PLL1 by Sean Anderson · Thu Apr 08 22:13:12 2021 -0400
  63. 7be6d2b riscv: k210: Rename airam to aisram by Sean Anderson · Thu Apr 08 22:13:11 2021 -0400
  64. e8d9e3a riscv: Enable some devices pre-relocation by Sean Anderson · Thu Apr 08 22:13:09 2021 -0400
  65. c88bdaa riscv: dts: mpfs-icicle-kit: Drop 'clock-frequency' in the uart nodes by Bin Meng · Wed Mar 31 15:24:50 2021 +0800
  66. e9ead4a riscv: sifive: Rename fu540 board to unleashed by Bin Meng · Wed Mar 17 11:10:58 2021 +0800
  67. 1c30c0e riscv: Add watchdog bindings for the k210 by Sean Anderson · Wed Mar 10 21:02:21 2021 -0500
  68. 0937c19 riscv: k210: Enable QSPI for spi3 by Sean Anderson · Thu Feb 04 23:11:19 2021 -0500
  69. 5854c3d riscv: dts: Add device tree for Microchip Icicle Kit by Padmarao Begari · Fri Jan 15 08:20:39 2021 +0530
  70. 2ddd3e0 riscv: Add device tree bindings for SPI by Sean Anderson · Fri Oct 16 18:57:54 2020 -0400
  71. fd9571a spi: dw: Add SoC-specific compatible strings by Sean Anderson · Fri Oct 16 18:57:50 2020 -0400
  72. 2dc5984 riscv: fu540: dts: Correct reg size of clint node by Pragnesh Patel · Tue Oct 20 11:03:02 2020 +0530
  73. d1b3321 riscv: k210: Reduce DMA block size by Sean Anderson · Mon Oct 12 14:18:15 2020 -0400
  74. 36d38fd riscv: add DT binding for BOOT button on Maix board by Heinrich Schuchardt · Mon Sep 14 11:02:05 2020 -0400
  75. 6870556 riscv: Add pinmux and gpio bindings for Kendryte K210 by Sean Anderson · Mon Sep 14 11:02:04 2020 -0400
  76. 3d999194 riscv: Update SiFive device tree for new CLINT driver by Sean Anderson · Mon Sep 28 10:52:29 2020 -0400
  77. c6d0ef8 riscv: Update Kendryte device tree for new CLINT driver by Sean Anderson · Mon Sep 28 10:52:28 2020 -0400
  78. b0357f4 fu540: dtsi: add reset producer and consumer entries by Sagar Shrikant Kadam · Wed Jul 29 02:36:12 2020 -0700
  79. a9e7ec5 riscv: dts: hifive-unleashed-a00: Make memory node available to SPL by Bin Meng · Sun Jul 19 23:06:34 2020 -0700
  80. 05fb96d sifive: fu540: Add Booting from SPI by Jagan Teki · Wed Jul 15 15:38:59 2020 +0530
  81. 90fa4e9 Merge branch 'next' by Tom Rini · Mon Jul 06 15:46:38 2020 -0400
  82. 8a52128 riscv: sifive: fu540: enable all cache ways from U-Boot proper by Pragnesh Patel · Fri May 29 12:14:51 2020 +0530
  83. 3961e14 riscv: fu540: dts: Correct reg size of otp and dmc nodes by Bin Meng · Mon Jun 08 20:28:26 2020 -0700
  84. e3870c8 riscv: fu540: dts: Remove the unnecessary space in the cpu2_intc node by Bin Meng · Mon Jun 08 20:28:25 2020 -0700
  85. d2b7f84 riscv: dts: hifive-unleashed-a00: add cpu aliases by Sagar Shrikant Kadam · Sun Jun 28 07:45:00 2020 -0700
  86. d11b582 riscv: Add device tree for K210 and Sipeed Maix BitM by Sean Anderson · Wed Jun 24 06:41:23 2020 -0400
  87. e00653c riscv: sifive: fu540: add SPL configuration by Pragnesh Patel · Fri May 29 11:33:35 2020 +0530
  88. 01ec498 riscv: dts: sifive: Sync hifive-unleashed-a00 dts from linux by Pragnesh Patel · Fri May 29 11:33:33 2020 +0530
  89. bb337f9 riscv: sifive: dts: fu540: set ethernet clock rate by Pragnesh Patel · Fri May 29 11:33:32 2020 +0530
  90. 45ffc91 riscv: sifive: dts: fu540: add U-Boot dmc node by Pragnesh Patel · Fri May 29 11:33:28 2020 +0530
  91. 8f4a403 sifive: dts: fu540: Add DDR controller and phy register settings by Pragnesh Patel · Fri May 29 11:33:27 2020 +0530
  92. b65f19f riscv: sifive: dts: fu540: Add board -u-boot.dtsi files by Pragnesh Patel · Fri May 29 11:33:25 2020 +0530
  93. 2a449a3 riscv: sifive: fu540: Use OTP DM driver for serial environment variable by Pragnesh Patel · Fri May 29 11:33:22 2020 +0530
  94. 76c8522 sifive: fu540: Enable spi-nor flash support by Jagan Teki · Wed Apr 29 21:03:53 2020 +0530
  95. 0c2964b riscv: dts: hifive-unleashed-a00: Add -u-boot.dtsi by Jagan Teki · Thu Apr 23 22:30:56 2020 +0530
  96. 314d3ef riscv: dts: Add #address-cells and #size-cells in nor node by Rick Chen · Thu Nov 14 13:52:29 2019 +0800
  97. 3209fb8 riscv: dts: Support four cores SMP by Rick Chen · Thu Nov 14 13:52:28 2019 +0800
  98. a8ed626 riscv: dts: Add hifive-unleashed-a00 dts from Linux by Jagan Teki · Mon Nov 18 16:59:40 2019 +0530
  99. 5ff8f41 riscv: dts: move out AE350 L2 node from cpus node by Rick Chen · Wed Aug 28 18:46:10 2019 +0800
  100. a009fa7 dts: switch spi-flash to jedec, spi-nor compatible by Neil Armstrong · Sun Feb 10 10:16:20 2019 +0000