| commit | 42fa87e9f1cc93fca375c3f60d46dd56a22a9413 | [log] [tgz] |
|---|---|---|
| author | Torsten Duwe <duwe@lst.de> | Mon Aug 14 18:05:33 2023 +0200 |
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | Tue Sep 05 10:53:36 2023 +0800 |
| tree | 6f46d4b8d5e9cad5f969665f707d0b7374ef9130 | |
| parent | 002858cd01f80dc21b277d71cb2df0de01306a69 [diff] |
riscv: jh7110: enable riscv,timer in the device tree The JH7110 has the arhitectural CPU timer on all 5 rv64 cores. Note that in the device tree. Signed-off-by: Torsten Duwe <duwe@suse.de> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>