| commit | 7ae81bb4715594fa334db8c6eb3505f22f7bc0c3 | [log] [tgz] |
|---|---|---|
| author | Xingyu Wu <xingyu.wu@starfivetech.com> | Fri Jul 07 18:50:08 2023 +0800 |
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | Mon Jul 24 13:21:01 2023 +0800 |
| tree | b63fe4485552248aba0081de015f913ddd4c1243 | |
| parent | 751e4400f2e5e01de2adb879fad1e92d6cfd1197 [diff] |
riscv: dts: jh7110: Add PLL clock controller node Add child node about PLL clock controller in sys_syscon node. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Reviewed-by: Torsten Duwe <duwe@suse.de> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>