tree b63fe4485552248aba0081de015f913ddd4c1243
parent 751e4400f2e5e01de2adb879fad1e92d6cfd1197
author Xingyu Wu <xingyu.wu@starfivetech.com> 1688727008 +0800
committer Leo Yu-Chi Liang <ycliang@andestech.com> 1690176061 +0800

riscv: dts: jh7110: Add PLL clock controller node

Add child node about PLL clock controller in sys_syscon node.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Torsten Duwe <duwe@suse.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>