Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / e41a292cd2ffc5fa2d89a632c2c9b7dc1f2f34b1 / arch / powerpc / cpu / mpc8xxx / ddr / ctrl_regs.c
  1. e12ce98 powerpc/mpc83xx: Migrate from spd_sdram to unified DDR driver by York Sun · Fri Aug 26 11:32:44 2011 -0700
  2. 15f874a powerpc/mpc8xxx: Fix DDR code for empty first DIMM slot and enable DQS_en by York Sun · Fri Aug 26 11:32:40 2011 -0700
  3. 7a16d64 powerpc/mpc8xxx: Extend CWL table by York Sun · Wed Aug 24 09:40:25 2011 -0700
  4. f8691fc powerpc/mpc8xxx: Allow override DDR read-to-write turnaround time by York Sun · Fri May 27 13:44:28 2011 +0800
  5. 4513d76 powerpc/8xxx: Fix typo for address hashing message by Kumar Gala · Fri Mar 18 11:53:06 2011 -0500
  6. b78c7bf powerpc/8xxx: Replace fsl_ddr_get_mem_data_rate with get_ddr_freq() by Kumar Gala · Mon Jan 31 20:36:02 2011 -0600
  7. 501b70d powerpc/mpc8xxx: disable rcw_en bit for non-DDR3 by York Sun · Thu Mar 17 11:18:12 2011 -0700
  8. 3673f2c powerpc/mpc8xxx: Fix DDR3 timing_cfg_1 and sdram_mode registers by York Sun · Wed Mar 02 14:24:11 2011 -0800
  9. 27f83be powerpc/8xxx: Add additional cycle to write-to-read turnaound for DDR3 by York Sun · Thu Feb 10 10:13:10 2011 -0800
  10. 65b5be2 powerpc/8xxx: Fix compile warning when build for a DDR1 or DDR2 board by Kumar Gala · Thu Jan 20 01:53:15 2011 -0600
  11. ba0c2eb mpc85xx: Enable unique mode registers and dynamic ODT for DDR3 by York Sun · Mon Jan 10 12:03:00 2011 +0000
  12. 80ad401 8xxx/ddr: add support to only compute the ddr sdram size by Haiying Wang · Wed Dec 01 10:35:31 2010 -0500
  13. 2927c5e Disable unused chip-select for DDR controller interleaving by York Sun · Mon Oct 18 13:46:50 2010 -0700
  14. 5207e77 Fix parameters to support RDIMM for P2020DS by York Sun · Fri Aug 27 16:25:56 2010 -0500
  15. 1714e49 powerpc/8xxx: Improvement to DDR parameters by york · Fri Jul 02 22:25:56 2010 +0000
  16. de87932 powerpc/8xxx: Enable DDR3 RDIMM support by york · Fri Jul 02 22:25:55 2010 +0000
  17. 4260372 powerpc/8xxx: Enabled address hashing for 85xx by york · Fri Jul 02 22:25:54 2010 +0000
  18. f4f93c6 powerpc/8xxx: Enable quad-rank DIMMs. by york · Fri Jul 02 22:25:53 2010 +0000
  19. 93799ca powerpc/8xxx: Fix bug in memctrl interleaving & bank interleaving on cs0~cs4 by york · Fri Jul 02 22:25:52 2010 +0000
  20. 8107926 fsl-ddr: Add extra cycle to turnaround times by Dave Liu · Tue Dec 08 11:56:48 2009 +0800
  21. 88fbf93 Move arch/ppc to arch/powerpc by Stefan Roese · Thu Apr 15 16:07:28 2010 +0200[Renamed from arch/ppc/cpu/mpc8xxx/ddr/ctrl_regs.c]
  22. 29514c7 ppc: Move cpu/$CPU to arch/ppc/cpu/$CPU by Peter Tyser · Mon Apr 12 22:28:09 2010 -0500[Renamed from cpu/mpc8xxx/ddr/ctrl_regs.c]
  23. 3525e1a fsl-ddr: Fix the turnaround timing for TIMING_CFG_4 by Dave Liu · Fri Mar 05 12:22:00 2010 +0800
  24. 625b268 fsl-ddr: setup ODT_RD_CFG & ODT_WR_CFG when we interleave by Dave Liu · Wed Dec 16 10:24:39 2009 -0600
  25. 2d0f125 fsl-ddr: add override for the Rtt_Wr by Dave Liu · Wed Dec 16 10:24:38 2009 -0600
  26. 64ee7df fsl-ddr: add the override for write leveling by Dave Liu · Wed Dec 16 10:24:37 2009 -0600
  27. c7d983a fsl-ddr: Fix power-down timing settings by Dave Liu · Wed Dec 16 10:24:36 2009 -0600
  28. 14f2eb1 ppc/8xxx: Misc DDR related fixes by Kumar Gala · Thu Sep 10 14:54:55 2009 -0500
  29. 24aa71a ppc/8xxx: Remove ddr_pd_cntl register since it doesn't exist by Kumar Gala · Tue Sep 01 22:01:54 2009 -0500
  30. 68ef4bd fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BIT by Kumar Gala · Thu Jun 11 23:42:35 2009 -0500
  31. 4be87b2 fsl-ddr: add the DDR3 SPD infrastructure by Dave Liu · Sat Mar 14 12:48:30 2009 +0800
  32. 82aa953 fsl-ddr: Fix two bugs in the ddr infrastructure by Dave Liu · Sat Mar 14 12:48:19 2009 +0800
  33. 2aad0ae fsl-ddr: make the self refresh idle threshold configurable by Dave Liu · Fri Nov 21 16:31:35 2008 +0800
  34. 4758d53 fsl-ddr: clean up the ddr code for DDR3 controller by Dave Liu · Fri Nov 21 16:31:29 2008 +0800
  35. 5c1bb51 fsl-ddr: update the bit mask for DDR3 controller by Dave Liu · Fri Nov 21 16:31:22 2008 +0800
  36. d90e040 Add debug information for DDR controller registers by Haiying Wang · Fri Oct 03 12:37:26 2008 -0400
  37. 272b596 Make DDR interleaving mode work correctly by Haiying Wang · Fri Oct 03 12:36:39 2008 -0400
  38. 35ad58d Fix compiler warning in mpc8xxx ddr code by Kumar Gala · Fri Sep 05 14:40:29 2008 -0500
  39. 124b082 FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. by Kumar Gala · Tue Aug 26 15:01:29 2008 -0500