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git01.mediatek.com / filogic / uboot / d9fcf9adc927c4028d220d964286611c3a7cde92 / drivers / ddr
  1. d9fcf9a ddr: altera: Internal mem_calibrate() cleanup part 6 by Marek Vasut · Mon Jul 20 04:34:51 2015 +0200
  2. 0568f22 ddr: altera: Internal mem_calibrate() cleanup part 5 by Marek Vasut · Fri Jul 17 02:50:56 2015 +0200
  3. fc38d5c ddr: altera: Internal mem_calibrate() cleanup part 4 by Marek Vasut · Fri Jul 17 02:40:21 2015 +0200
  4. 6db5573 ddr: altera: Internal mem_calibrate() cleanup part 3 by Marek Vasut · Fri Jul 17 02:38:51 2015 +0200
  5. f04045f ddr: altera: Internal mem_calibrate() cleanup part 2 by Marek Vasut · Fri Jul 17 02:31:04 2015 +0200
  6. d6f2879 ddr: altera: Internal mem_calibrate() cleanup part 1 by Marek Vasut · Fri Jul 17 02:21:47 2015 +0200
  7. b984ee8 ddr: altera: Trivial mem_calibrate() indent cleanup by Marek Vasut · Fri Jul 17 02:07:12 2015 +0200
  8. 60daef8 ddr: altera: Minor clean up of mem_skip_calibrate() by Marek Vasut · Sun Jul 26 10:54:15 2015 +0200
  9. 575029d ddr: altera: Clean up set_rank_and_odt_mask() part 3 by Marek Vasut · Mon Jul 20 08:15:57 2015 +0200
  10. 9252308 ddr: altera: Clean up set_rank_and_odt_mask() part 2 by Marek Vasut · Mon Jul 20 08:09:05 2015 +0200
  11. 0b5e257 ddr: altera: Clean up set_rank_and_odt_mask() part 1 by Marek Vasut · Mon Jul 20 08:03:11 2015 +0200
  12. be333bc ddr: altera: Clean up mem_precharge_and_activate() by Marek Vasut · Mon Jul 20 07:33:33 2015 +0200
  13. 0f0840d ddr: altera: Clean up mem_config() by Marek Vasut · Fri Jul 17 01:57:41 2015 +0200
  14. fe5aa45 ddr: altera: Clean up phy_mgr_initialize() by Marek Vasut · Fri Jul 17 01:36:32 2015 +0200
  15. 092a1ef ddr: altera: Clean up run_mem_calibrate() by Marek Vasut · Fri Jul 17 01:20:21 2015 +0200
  16. acaaff7 ddr: altera: Rename initialize() to phy_mgr_initialize() by Marek Vasut · Fri Jul 17 01:12:07 2015 +0200
  17. 5da0f5b ddr: altera: Init my_param and my_gbl by Marek Vasut · Fri Jul 17 01:05:36 2015 +0200
  18. b0563cf ddr: altera: Rework initialize_tracking() by Marek Vasut · Fri Jul 17 00:45:11 2015 +0200
  19. e5f2cf7 ddr: altera: Fix ad-hoc iterative division implementation by Marek Vasut · Fri Jul 17 03:11:06 2015 +0200
  20. 42e7860 ddr: altera: Minor clean up of set_jump_as_return() by Marek Vasut · Sun Jul 26 11:07:19 2015 +0200
  21. c577ab5 ddr: altera: Factor out common code by Marek Vasut · Mon Jul 13 00:51:05 2015 +0200
  22. 8bf9227 ddr: altera: Factor out instruction loading from rw_mgr_mem_initialize() by Marek Vasut · Mon Jul 13 00:44:30 2015 +0200
  23. 788870f ddr: altera: Clean up scc_mgr_apply_group_all_out_delay_add_all_ranks() by Marek Vasut · Sun Jul 19 02:18:21 2015 +0200
  24. 484fb3b ddr: altera: Internal scc_mgr_apply_group_all_out_delay_add() cleanup part 2 by Marek Vasut · Fri Jul 17 05:33:28 2015 +0200
  25. 20bfb9d ddr: altera: Internal scc_mgr_apply_group_all_out_delay_add() cleanup part 1 by Marek Vasut · Fri Jul 17 05:30:14 2015 +0200
  26. 62d3c69 ddr: altera: Clean up scc_mgr_zero_group() by Marek Vasut · Mon Jul 20 08:41:04 2015 +0200
  27. 08bcb98 ddr: altera: Clean up scc_mgr_zero_all() by Marek Vasut · Mon Jul 20 04:41:53 2015 +0200
  28. d4d3de2 ddr: altera: Extract scc_mgr_set_hhp_extras() by Marek Vasut · Sun Jul 19 01:34:43 2015 +0200
  29. 3b8e5b0 ddr: altera: Clean up scc_mgr_set_hhp_extras() by Marek Vasut · Sun Jul 19 01:32:55 2015 +0200
  30. 122e1f3 ddr: altera: Clean up scc_mgr_*_delay() args by Marek Vasut · Fri Jul 17 06:07:13 2015 +0200
  31. cd64950 ddr: altera: Clean up scc_mgr_apply_group_dq_out1_delay() by Marek Vasut · Fri Jul 17 05:42:49 2015 +0200
  32. e62f691 ddr: altera: Clean up scc_mgr_set_oct_out1_delay() by Marek Vasut · Sun Jul 12 23:39:06 2015 +0200
  33. 0341de4 ddr: altera: Clean up scc_set_bypass_mode() by Marek Vasut · Fri Jul 17 02:06:20 2015 +0200
  34. 5a4379e ddr: altera: Clean up scc_mgr_load_dqs_for_write_group() by Marek Vasut · Mon Jul 13 00:30:09 2015 +0200
  35. 1d3cde3 ddr: altera: Implement universal scc_mgr_set_all_ranks() by Marek Vasut · Sun Jul 12 23:25:21 2015 +0200
  36. 4972282 ddr: altera: Shuffle around scc_mgr_set_*all_ranks() by Marek Vasut · Sun Jul 12 23:14:33 2015 +0200
  37. 8957b49 ddr: altera: Clean up scc_mgr_initialize() by Marek Vasut · Mon Jul 20 07:16:42 2015 +0200
  38. 303a3dc ddr: altera: Implement universal scc manager config function by Marek Vasut · Sun Jul 12 22:28:33 2015 +0200
  39. 7481b69 ddr: altera: Reorder scc manager functions by Marek Vasut · Sun Jul 12 22:11:55 2015 +0200
  40. cab8079 ddr: altera: Clean up scc manager function args by Marek Vasut · Sun Jul 12 22:07:33 2015 +0200
  41. 6eeb747 ddr: altera: Clean up reg_file_set*() by Marek Vasut · Sun Jul 12 21:10:24 2015 +0200
  42. 0c9f3cb ddr: altera: Clean up initialize_hps_phy() by Marek Vasut · Sun Jul 19 06:14:04 2015 +0200
  43. a17ae0f ddr: altera: Clean up initialize_reg_file() by Marek Vasut · Sun Jul 19 06:13:37 2015 +0200
  44. ea9771b ddr: altera: Clean up hc_initialize_rom_data() by Marek Vasut · Sun Jul 19 06:12:42 2015 +0200
  45. b545096 ddr: altera: Massage addr into I/O accessors by Marek Vasut · Sun Jul 12 21:05:08 2015 +0200
  46. cd5d38e ddr: altera: Stop using SDR_CTRLGRP_ADDRESS directly by Marek Vasut · Sun Jul 12 20:49:39 2015 +0200
  47. 33acf0f ddr: altera: Wrap SOCFPGA_SDR_ADDRESS into SDR_PHYGRP.*ADDRESS by Marek Vasut · Sun Jul 12 20:05:54 2015 +0200
  48. a334010 ddr: altera: Pluck out remaining sdr_get_addr() calls by Marek Vasut · Sun Jul 12 19:03:33 2015 +0200
  49. c3b9b0f ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_mgr_.*->.*) by Marek Vasut · Sun Jul 12 18:54:37 2015 +0200
  50. 0dcb9e8 ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_rw_load.*->.*) by Marek Vasut · Sun Jul 12 18:46:52 2015 +0200
  51. 81df0a2 ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_scc_mgr->.*) by Marek Vasut · Sun Jul 12 18:42:34 2015 +0200
  52. 341ceec ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_reg_file->.*) by Marek Vasut · Sun Jul 12 18:31:05 2015 +0200
  53. 1fa9589 ddr: altera: Zap invocation of sdr_get_addr((u32 *)BASE_RW_MGR)" by Marek Vasut · Sun Jul 12 17:52:36 2015 +0200
  54. 6283b4c ddr: altera: Clean up ugly casts in sdram_calibration_full() by Marek Vasut · Mon Jul 13 01:05:27 2015 +0200
  55. f84348d ddr: altera: Minor indent fix in set_rank_and_odt_mask() by Marek Vasut · Sat Jul 18 02:23:29 2015 +0200
  56. 0eacf7e ddr: altera: Fix debug message format in sequencer by Marek Vasut · Fri Jun 26 18:56:54 2015 +0200
  57. 452d639 ddr: altera: Fix typo in mp_threshold1 programming by Marek Vasut · Thu Jul 09 01:47:56 2015 +0200
  58. e08c559 ddr: altera: Move struct sdram_prot_rule prototype by Marek Vasut · Sun Jul 26 10:37:54 2015 +0200
  59. 43bb47e arm: socfpga: Move sdram_config.h to board dir by Marek Vasut · Sun Jul 12 15:59:10 2015 +0200
  60. 135cc7f driver/ddr/altera: Add the sdram calibration portion by Dinh Nguyen · Tue Jun 02 22:52:49 2015 -0500
  61. 429642c driver/ddr/altera: Add DDR driver for Altera's SDRAM controller by Dinh Nguyen · Tue Jun 02 22:52:48 2015 -0500
  62. 999273f drivers/ddr/fsl: Adjust bstopre value by York Sun · Thu Jul 23 14:04:48 2015 -0700
  63. 61cee0a arm: mvebu: a38x: Use correct PEX register access macros by Stefan Roese · Mon Jun 08 17:01:26 2015 +0200
  64. 5ffceb8 arm: mvebu: Add Armada 38x DDR3 training code from Marvell bin_hdr by Stefan Roese · Thu Mar 26 15:36:56 2015 +0100
  65. eb753e9 arm: mvebu: drivers/ddr: Move Armada XP DDR init code into new directory by Stefan Roese · Wed Mar 25 12:51:18 2015 +0100
  66. b10d1b7 driver/ddr/fsl: Add a hook to update SPD address by York Sun · Thu May 28 14:54:08 2015 +0530
  67. b1f81f0 arm: mvebu: db-mv784mp-gp: Fix ECC I2C address by Stefan Roese · Wed Apr 22 18:36:39 2015 +0200
  68. 1f8d706 driver/ddr/fsl: Add workaround for DDR erratum A008511 by York Sun · Thu Mar 19 09:30:29 2015 -0700
  69. b6a35f8 driver/ddr/fsl: Add built-in memory test for DDR4 driver by York Sun · Thu Mar 19 09:30:28 2015 -0700
  70. fc63b28 driver/ddr/fsl: Fix driver to support empty first slot by York Sun · Thu Mar 19 09:30:27 2015 -0700
  71. 55eb5fa drivers/ddr/fsl: Update DDR driver for DDR4 by York Sun · Thu Mar 19 09:30:26 2015 -0700
  72. 6aff153 MPC8541/MPC8555: Enable SS_EN in DDR_SDRAM_CLK_CNLT register by Curt Brune · Fri Feb 13 10:57:11 2015 -0800
  73. 8ced050 driver/ddr/fsl: Add sync of refresh by York Sun · Tue Jan 06 13:18:55 2015 -0800
  74. 5e52647 driver/ddr/fsl: Fix a typo in timing_cfg_8 calculation by York Sun · Tue Jan 06 13:18:52 2015 -0800
  75. 2c0b62d driver/ddr/fsl: Add support for multiple DDR clocks by York Sun · Tue Jan 06 13:18:50 2015 -0800
  76. d429c5f driver/ddr/fsl: Add workround for erratumn A008514 by York Sun · Tue Jan 06 13:18:48 2015 -0800
  77. 8675fac driver/ddr/fsl: Add workaround for A008336 by York Sun · Tue Jan 06 13:18:47 2015 -0800
  78. 63f5771 driver/ddr/fsl: Adjust CAS to preamble override for emulator by York Sun · Tue Jan 06 13:18:45 2015 -0800
  79. ae6223d arm: mvebu: drivers/ddr: Add DDR3 driver with training code from Marvell bin_hdr by Stefan Roese · Mon Jan 19 11:33:40 2015 +0100
  80. 70acb34 arm/ls1021a: Add workaround for DDR erratum A008378 by York Sun · Mon Dec 08 15:30:55 2014 -0800
  81. 1b07ef1 driver/ddr/fsl: Fix MRC_CYC calculation for DDR3 by York Sun · Tue Dec 02 11:18:09 2014 -0800
  82. 064f126 fsl/sleep: updated the deep sleep framework for QorIQ platforms by Tang Yuantian · Fri Nov 21 11:17:15 2014 +0800
  83. b5d606a driver/ddr/fsl: Add workaround for faulty SPD by York Sun · Fri Nov 14 17:17:50 2014 -0800
  84. fbce88c driver/ddr/fsl: Adjust timing_cfg_0 to better support two DDR slots by York Sun · Fri Nov 07 12:14:36 2014 -0800
  85. db20464 linux/kernel.h: sync min, max, min3, max3 macros with Linux by Masahiro Yamada · Fri Nov 07 03:03:31 2014 +0900
  86. a8b3d52 driver/ddr/fsl: Fix DDR4 driver by York Sun · Thu Sep 11 13:32:06 2014 -0700
  87. c1bf24f driver/ddr/fsl: Fix tXP and tCKE by York Sun · Thu Aug 21 16:13:22 2014 -0700
  88. 79a779b driver/ddr: Restruct driver to allow standalone memory space by York Sun · Fri Aug 01 15:51:00 2014 -0700
  89. e0f6046 driver/ddr/fsl: Add support of overriding chip select write leveling by York Sun · Fri Sep 05 13:52:43 2014 +0800
  90. 132b5d9 driver/ddr/freescale: Fix DDR3 driver for ARM by York Sun · Fri Sep 05 13:52:42 2014 +0800
  91. 5d6c626 driver/ddr/freescale: Add support of accumulate ECC by York Sun · Fri Sep 05 13:52:41 2014 +0800
  92. f0e4f6d driver/ddr: Fix DDR register timing_cfg_8 by York Sun · Thu Jun 26 11:14:44 2014 -0700
  93. 157e72d driver/ddr: Fix DDR4 driver for ARM by York Sun · Mon Jun 23 15:36:44 2014 -0700
  94. ff5ca8d driver/ddr/fsl: Fix printing unspecified module info for DDR4 by York Sun · Thu Jun 05 12:32:15 2014 -0700
  95. 9982579 powerpc/mpc85xx: Add workaround for DDR erratum A004508 by York Sun · Fri May 23 13:15:00 2014 -0700
  96. be6aafc Add cli_ prefix to readline functions by Simon Glass · Thu Apr 10 20:01:27 2014 -0600
  97. dec3c01 move CLI prototypes to cli.h and add comments by Simon Glass · Thu Apr 10 20:01:25 2014 -0600
  98. a7364af mpc85xx/t104x: Add deep sleep framework support by Tang Yuantian · Thu Apr 17 15:33:46 2014 +0800
  99. edbeee1 drivers/ddr: Fix possible out of bounds error by York Sun · Tue Apr 01 14:20:49 2014 -0700
  100. 2896cb7 driver/ddr/fsl: Add DDR4 support to Freescale DDR driver by York Sun · Thu Mar 27 17:54:47 2014 -0700