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git01.mediatek.com / filogic / uboot / bebd282446306e3adfea2144af472e87856955d8 / drivers / clk / clk_stm32f.c
  1. a1b654b treewide: invaild -> invalid by Sean Anderson · Wed Dec 01 14:26:53 2021 -0500
  2. a57b8cd clk: clk_stm32f: migrate trace to dev and log macro by Patrick Delaunay · Fri Nov 06 19:01:46 2020 +0100
  3. 8a2b47f dm: treewide: Rename auto_alloc_size members to be shorter by Simon Glass · Thu Dec 03 16:55:17 2020 -0700
  4. 4dcacfc common: Drop linux/bitops.h from common header by Simon Glass · Sun May 10 11:40:13 2020 -0600
  5. 0f2af88 common: Drop log.h from common header by Simon Glass · Sun May 10 11:40:05 2020 -0600
  6. 7264aae clk: clk_stm32f: Use PLLSAIP as USB 48MHz clock by Patrice Chotard · Wed Apr 11 17:07:45 2018 +0200
  7. 10e4779 SPDX: Convert all of our single license tags to Linux Kernel style by Tom Rini · Sun May 06 17:58:06 2018 -0400
  8. e199c3a clk: clk_stm32f: Add DSI clock support by Patrice Chotard · Thu Feb 08 17:20:51 2018 +0100
  9. 2cd1ed1 clk: clk_stm32f: Add set_rate for LTDC clock by Patrice Chotard · Thu Feb 08 17:20:50 2018 +0100
  10. ff7b11e clk: clk_stm32f: Configure SAI PLL to generate LTDC pixel clock by Patrice Chotard · Thu Feb 08 17:20:49 2018 +0100
  11. 8aca2d1 clk: clk_stm32f: Rework SDMMC stm32_clk_get_rate() part by Patrice Chotard · Thu Feb 08 17:20:48 2018 +0100
  12. cb15d28 clk: clk_stm32f: No more need of 48Mhz from PLL_SAI by Patrice Chotard · Thu Feb 08 17:20:47 2018 +0100
  13. 9490aca clk: clk_stm32f: Fix RCC_PLLSAICFGR mask defines by Patrice Chotard · Thu Feb 08 17:20:46 2018 +0100
  14. 81d7765 clk: clk_stm32f: Fix stm32_clk_get_rate() by Patrice Chotard · Thu Feb 08 17:20:45 2018 +0100
  15. 0c15676 board: stm32: switch to DM STM32 timer by Patrice Chotard · Wed Feb 07 10:44:50 2018 +0100
  16. ef77287 clk: clk_stm32f: Fix stm32_clk_get_rate() for timer by Patrice Chotard · Wed Feb 07 10:44:46 2018 +0100
  17. 24e8578 clk: clk_stm32: Add .set_rate callback by Patrice Chotard · Mon Jan 29 18:14:14 2018 +0100
  18. d5d3655 clk: clk_stm32f: Fix PLLSAICFGR_PLLSAIP_4 divider value by Patrice Chotard · Fri Jan 19 18:02:40 2018 +0100
  19. e2d564e clk: clk_stm32f: Move SYSCFG clock setup into configure_clocks() by Patrice Chotard · Thu Jan 18 14:10:05 2018 +0100
  20. b710b7f clk: clk_stm32f: Remove STMMAC clock setup by Patrice Chotard · Thu Jan 18 14:10:04 2018 +0100
  21. acd97ca clk: stm32: retrieve external oscillator frequency from DT by Patrice Chotard · Thu Jan 18 13:39:30 2018 +0100
  22. f3a701a board: stm32f429-disco: switch to DM STM32 clock driver by Patrice Chotard · Tue Dec 12 09:49:39 2017 +0100
  23. 369d483 clk: clk_stm32fx: add clock configuration for mmc usage by Patrice Chotard · Wed Nov 15 13:14:52 2017 +0100
  24. 03f10a1 dm: misc: bind STM32F4/F7 clock from rcc MFD driver by Patrice Chotard · Wed Nov 15 13:14:51 2017 +0100
  25. 06fc648 clk: stm32fx: migrate define from rcc.h to driver by Patrice Chotard · Wed Nov 15 13:14:49 2017 +0100
  26. d4f2d20 clk: stm32f7: rename clk_stm32f7.c to clk_stm32f.c by Patrice Chotard · Wed Nov 15 13:14:48 2017 +0100[Renamed (97%) from drivers/clk/clk_stm32f7.c]
  27. 1509d66 clk: stm32f7: add STM32F4 support by Patrice Chotard · Wed Nov 15 13:14:47 2017 +0100
  28. 9230487 clk: stm32f7: add dedicated STM32F7 compatible string by Patrice Chotard · Wed Nov 15 13:14:45 2017 +0100
  29. 22768d5 clk: stm32f7: retrieve PWR base address from DT by Patrice Chotard · Wed Nov 15 13:14:44 2017 +0100
  30. b6653f6 clk: clk_stm32f7: fix PLL clock division factor by Patrice Chotard · Thu Oct 26 13:23:19 2017 +0200
  31. 789ee0e stm32: fix STMicroelectronics copyright by Patrice Chotard · Mon Oct 23 09:53:58 2017 +0200
  32. 81e1042 treewide: replace with error() with pr_err() by Masahiro Yamada · Sat Sep 16 14:10:41 2017 +0900
  33. b323de5 dm: clk: add missing .priv_auto_alloc_size() for stm32f7 by Patrice Chotard · Thu Sep 21 10:08:09 2017 +0200
  34. e2e28d2 clk: stm32f7: remove clock_get() by Patrice Chotard · Tue Jul 18 09:29:10 2017 +0200
  35. fee92ee clk: stm32f7: cleanup clocks unused definitions by Patrice Chotard · Tue Jul 18 09:29:06 2017 +0200
  36. 7bdf971 clk: stm32f7: add clock .get_rate() callback by Patrice Chotard · Tue Jul 18 09:29:05 2017 +0200
  37. d93fc2c clk: stm32f7: get RCC base address from DT by Patrice Chotard · Tue Jul 18 09:29:04 2017 +0200
  38. a8f951a clk: stm32f7: add static for configure_clocks() by Patrice Chotard · Tue Jul 18 09:29:03 2017 +0200
  39. b7ae277 clk: Modify xlate() method for livetree by Simon Glass · Thu May 18 20:09:40 2017 -0600
  40. 1a8fde7 stm32f7: use stm32f7 gpio driver supporting driver model by Vikas Manocha · Mon Apr 10 15:02:59 2017 -0700
  41. 2183cbf stm32f7: clk: remove usart1 clock enable from board init by Vikas Manocha · Sun Feb 12 10:25:48 2017 -0800
  42. daaeaab clk: stm32f7: add clock driver for stm32f7 family by Vikas Manocha · Sun Feb 12 10:25:45 2017 -0800[Renamed (85%) from arch/arm/mach-stm32/stm32f7/clock.c]
  43. 337ff2a ARM: SPI: stm32: add stm32f746 qspi driver by Michael Kurz · Sun Jan 22 16:04:30 2017 +0100
  44. 812962b net: stm32: add designware mac glue code for stm32 by Michael Kurz · Sun Jan 22 16:04:27 2017 +0100
  45. 04bb8db ARM: stm32: use clock setup function defined in clock.c by Michael Kurz · Sun Jan 22 16:04:26 2017 +0100
  46. c204fb7 ARM: stm32: cleanup stm32f7 files by Michael Kurz · Sun Jan 22 16:04:24 2017 +0100
  47. 22866944 Revert "stm32: Change USART port to USART6 for stm32f746 discovery board" by Tom Rini · Thu Jul 21 15:38:13 2016 -0400
  48. 8a214c9 stm32: Change USART port to USART6 for stm32f746 discovery board by Toshifumi NISHINAGA · Fri Jul 08 01:02:26 2016 +0900
  49. 65bfb9c stm32: clk: Add 200MHz clock configuration for stm32f746 discovery board by Toshifumi NISHINAGA · Fri Jul 08 01:02:24 2016 +0900
  50. 1b51c93 stm32: add support for stm32f7 & stm32f746 discovery board by Vikas Manocha · Thu Feb 11 15:47:20 2016 -0800