Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / b121cb85cf21244d672f417865c53fb9daf20359 / arch / riscv
  1. 5d0bbea andes: Unify naming policy for Andes related source by Leo Yu-Chi Liang · Tue May 14 17:50:11 2024 +0800
  2. b68fc1d riscv: simplify backtrace report by Heinrich Schuchardt · Tue May 14 07:51:42 2024 +0200
  3. 89ef034 board: starfive: function to read eMMC size by Heinrich Schuchardt · Sun May 12 06:25:22 2024 +0200
  4. dee15a9 global: Make <asm/global_data.h> include <asm/u-boot.h> by Tom Rini · Tue Apr 30 20:40:48 2024 -0600
  5. 2b62dd6 board: starfive: Rename spl_soc_init() to spl_dram_init() by Lukas Funke · Wed Apr 24 09:43:39 2024 +0200
  6. 2e71a9e board: sifive: Rename spl_soc_init() to spl_dram_init() by Lukas Funke · Wed Apr 24 09:43:38 2024 +0200
  7. 60455d6f riscv: dts: sophgo: Add spi nor flash controller node by Kongyang Liu · Sat Apr 20 15:08:24 2024 +0800
  8. af32b89 riscv: dts: sophgo: Add ethernet node by Kongyang Liu · Sat Apr 20 15:00:28 2024 +0800
  9. 85efa4e cmd: sbi: add Supervisor Software Events extension by Heinrich Schuchardt · Wed Apr 17 16:01:27 2024 +0200
  10. 9ae964b riscv: andesv5: Set default cache line size to 64-bytes by Yu Chien Peter Lin · Thu Apr 11 17:29:45 2024 +0800
  11. 793921e Revert "Merge patch series "pxe: Allow extlinux booting without CMDLINE enabled"" by Tom Rini · Thu Apr 18 08:29:35 2024 -0600
  12. 5725dde Merge patch series "pxe: Allow extlinux booting without CMDLINE enabled" by Tom Rini · Wed Apr 10 17:06:27 2024 -0600
  13. 586138f treewide: Make arch-specific bootm code depend on BOOTM by Simon Glass · Thu Dec 14 21:19:02 2023 -0700
  14. 0d96abb Merge tag 'xilinx-for-v2024.07-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze by Tom Rini · Wed Apr 10 11:51:58 2024 -0600
  15. f560f0f eeprom: starfive: function get_product_id_from_eeprom() by Heinrich Schuchardt · Tue Apr 02 10:49:08 2024 +0200
  16. 298fe6c riscv: starfive: MMC card detect by Heinrich Schuchardt · Thu Mar 28 22:46:15 2024 +0100
  17. 1b100e5 riscv: Move virtio scan to board_late_init() by Łukasz Stelmach · Thu Mar 28 10:58:24 2024 +0100
  18. 801bbf9 riscv: support extension probing using riscv, isa-extensions by Conor Dooley · Mon Mar 18 15:16:03 2024 +0000
  19. 4198155 riscv: don't read riscv, isa in the riscv cpu's get_desc() by Conor Dooley · Mon Mar 18 15:16:02 2024 +0000
  20. 8681442 riscv: dts: sophgo: Add clk node and sdhci node by Kongyang Liu · Sun Mar 10 01:51:56 2024 +0800
  21. 749d467 riscv: cache: Implement dcache for cv1800b by Kongyang Liu · Sun Mar 10 00:54:57 2024 +0800
  22. f752674 riscv: cpu: cv1800b: Add support for cv1800b SoC by Kongyang Liu · Sun Mar 10 00:54:56 2024 +0800
  23. 8a813c1 riscv: add backtrace support by Ben Dooks · Tue Sep 05 13:12:53 2023 +0100
  24. d960e20 Merge tag 'u-boot-socfpga-next-20240319' of https://source.denx.de/u-boot/custodians/u-boot-socfpga into next by Tom Rini · Tue Mar 19 09:10:30 2024 -0400
  25. 13ec9f8 Kconfig: move CONFIG_32/64BIT to arch/Kconfig by Dan Carpenter · Mon Mar 04 10:04:15 2024 +0300
  26. 9d82440 riscv: dts: jh7110: Enable PLL node in SPL by Bo Gan · Tue Mar 05 19:00:11 2024 -0800
  27. 01a8587 riscv: cpu: improve multi-letter extension detection in supports_extension() by Conor Dooley · Mon Mar 04 23:28:35 2024 +0000
  28. aff571a riscv: dts: jh7110: fix indentation by Leon M. Busch-George · Mon Mar 04 21:51:47 2024 +0100
  29. fb7800b riscv: sifive: fu740: reduce DDR speed from 1866MT/s to 1600MT/s by Thomas Perrot · Thu Feb 22 15:52:03 2024 +0100
  30. 54a898c riscv: mbv: Enable SPL and binman by Michal Simek · Wed Feb 14 12:52:33 2024 +0100
  31. 299425d efi_loader: set IMAGE_DLLCHARACTERISTICS_NX_COMPAT by Heinrich Schuchardt · Wed Feb 14 21:43:21 2024 +0100
  32. cf44e5c riscv: dts: starfive: add regulator device by Nam Cao · Mon Jan 29 09:43:09 2024 +0100
  33. ecfd53c riscv: dts: jh7110: add power management unit controller node by Nam Cao · Mon Jan 29 09:43:08 2024 +0100
  34. b64fc0e riscv: sophgo: milkv_duo: initial support added by Kongyang Liu · Sun Jan 28 15:05:25 2024 +0800
  35. 8b2b5fd riscv: dts: sophgo: add basic device tree for Milk-V Duo board by Kongyang Liu · Sun Jan 28 15:05:24 2024 +0800
  36. 23b0fd6 riscv: Support building with Clang by kleines Filmröllchen · Thu Jan 25 15:06:59 2024 +0100
  37. 35b0d18 cmd: sbi: add support for Debug Trigger Extension by Heinrich Schuchardt · Wed Jan 17 17:46:52 2024 +0100
  38. 6a84277 board: sifive: spl: Initialized the PWM setting in the SPL stage by Vincent Chen · Tue Jan 16 14:35:57 2024 +0800
  39. 9bcbe84 riscv: separate .data and .text sections of EFI binaries by Heinrich Schuchardt · Thu Jan 25 09:38:15 2024 +0100
  40. 9ceda68 riscv: page align EFI binary section by Heinrich Schuchardt · Thu Jan 25 09:38:14 2024 +0100
  41. 558abfe riscv: conflicting SPDX license linker scripts by Heinrich Schuchardt · Thu Jan 25 09:38:13 2024 +0100
  42. 565ac63 riscv: add ACPI fields to global data by Heinrich Schuchardt · Tue Dec 19 16:04:03 2023 +0100
  43. 7862a2a andes: cpu: Enable cache and TLB ECC support by Leo Yu-Chi Liang · Tue Dec 26 14:17:35 2023 +0800
  44. 96e75a8 andes: cpu: Enable memboost feature by Leo Yu-Chi Liang · Tue Dec 26 14:17:34 2023 +0800
  45. 1eb9f91 andes: ae350: Implement cache switch via Kconfig by Leo Yu-Chi Liang · Tue Dec 26 14:17:33 2023 +0800
  46. a5dda2b andes: csr.h: Clean up CSR definition by Leo Yu-Chi Liang · Tue Dec 26 14:17:32 2023 +0800
  47. d0f9f3a riscv: Extend board compatible string with "qemu,mbv" by Michal Simek · Wed Dec 20 15:53:28 2023 +0100
  48. 44876f3 riscv: cache: support cache enable in SPL stage by Zong Li · Thu Dec 14 14:09:37 2023 +0000
  49. 13692b3 Merge patch series "Complete decoupling of bootm logic from commands" by Tom Rini · Thu Dec 21 16:10:00 2023 -0500
  50. 0726d9d bootm: Adjust arguments of boot_os_fn by Simon Glass · Fri Dec 15 20:14:13 2023 -0700
  51. 34ee3ed riscv: Add a reset_cpu() function by Simon Glass · Fri Dec 15 20:14:09 2023 -0700
  52. 10e6a37 global: Rework architecture global_data.h to include <linux/types.h> by Tom Rini · Thu Dec 14 13:16:52 2023 -0500
  53. 0dd0659 Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-riscv into next by Tom Rini · Mon Dec 18 09:56:58 2023 -0500
  54. 08ccd54 Merge tag 'v2024.01-rc5' into next by Tom Rini · Mon Dec 18 08:31:50 2023 -0500
  55. 962c10a riscv: Add support for AMD/Xilinx MicroBlaze V by Michal Simek · Mon Nov 06 12:56:47 2023 +0100
  56. 9adf696 riscv: dts: jh7110: Add a gpio-restart node by Jaehoon Chung · Tue Oct 31 17:24:38 2023 +0900
  57. 1a5a8fc riscv: binman: fix the load field format by Randolph · Fri Nov 17 18:39:50 2023 +0800
  58. 922eec0 riscv: andes: Fix enable register settings of PLICSW by Yu Chien Peter Lin · Thu Nov 16 20:46:12 2023 +0800
  59. 0fe44f6 riscv: dts: jh7110: Add watchdog device tree node by Chanho Park · Mon Nov 06 08:13:17 2023 +0900
  60. 929c820 riscv: io.h: Fix signatures of reads/writes functions by Igor Prusov · Tue Nov 14 14:02:50 2023 +0300
  61. cde3882 riscv: io.h: Add defines for reads/writes functions by Igor Prusov · Tue Nov 14 14:02:49 2023 +0300
  62. 601941c riscv: dts: jh7110: Add rng device tree node by Chanho Park · Wed Nov 01 21:16:51 2023 +0900
  63. d1898ce riscv: import read/write_relaxed functions by Chanho Park · Wed Nov 01 21:16:48 2023 +0900
  64. 8bf50cd riscv: allow resume after exception by Heinrich Schuchardt · Tue Oct 31 14:55:51 2023 +0200
  65. a23ab3d riscv: cpu: jh7110: Add gpio helper macros by Chanho Park · Tue Oct 31 17:55:59 2023 +0900
  66. ac1c3d0 riscv: Weakly define invalidate_icache_range() by Samuel Holland · Tue Oct 31 00:37:20 2023 -0500
  67. 6c6315e riscv: Align the trap handler to 64 bytes by Samuel Holland · Tue Oct 31 00:35:41 2023 -0500
  68. bd6a54c riscv: Sort target configs alphabetically by Samuel Holland · Tue Oct 31 00:32:12 2023 -0500
  69. 9fcbdd4 Kconfig: Remove all default n/no options by Michal Simek · Wed Oct 25 09:25:37 2023 +0200
  70. b6b9900 riscv: Remove common.h usage by Tom Rini · Thu Oct 12 19:03:59 2023 -0400
  71. 4ac36bb sunxi: dts: arm: add T113s/D1 DT files from Linux-v6.6-rc6 by Andre Przywara · Thu Oct 19 15:45:32 2023 +0100
  72. 60814cb riscv: Add Zbb support for building U-Boot by Yu Chien Peter Lin · Wed Aug 09 18:49:30 2023 +0800
  73. 9d17cdb riscv: dts: binman: add condition for opensbi os boot by Randolph · Thu Oct 12 14:35:05 2023 +0800
  74. b1bc7a7 riscv: kconfig: introduce SPL_LOAD_FIT_OPENSBI_OS_BOOT symbol by Randolph · Thu Oct 12 14:35:04 2023 +0800
  75. 1a9a7a9 riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy by Randolph · Thu Oct 12 13:35:34 2023 +0800
  76. 5a3b018 riscv: binman: Fix compilation error by Mayuresh Chitale · Wed Oct 11 21:00:20 2023 +0530
  77. 3b1bcfb riscv: remove dram_init_banksize() by Heinrich Schuchardt · Tue Sep 26 09:16:34 2023 +0200
  78. ac5e68f riscv: andesv5: Prefer using the generic RISC-V timer driver in S-mode by Yu Chien Peter Lin · Fri Sep 29 12:03:07 2023 +0800
  79. 6c9c5ba configs: andes: add vender prefix for target name by Randolph · Mon Sep 25 17:24:51 2023 +0800
  80. 20964b6 riscv: enable CONFIG_DEBUG_UART by default by Heinrich Schuchardt · Sat Sep 23 01:35:26 2023 +0200
  81. 19f6361 riscv: bootstage: correct bootstage_report guard by Chanho Park · Wed Sep 06 14:18:12 2023 +0900
  82. b29a747 Merge branch 'next' by Tom Rini · Mon Oct 02 10:55:44 2023 -0400
  83. 03a885b riscv: set fdtfile on VisionFive 2 by Heinrich Schuchardt · Thu Sep 07 13:21:28 2023 +0200
  84. bdd5f81 common: Drop linux/printk.h from common header by Simon Glass · Thu Sep 14 18:21:46 2023 -0600
  85. 9b38810 Record the position of the SMBIOS tables by Simon Glass · Tue Sep 19 21:00:15 2023 -0600
  86. b112ed5 riscv: dts: starfive: generate u-boot-spl.bin.normal.out by Heinrich Schuchardt · Sun Sep 17 13:47:31 2023 +0200
  87. 329cd57 riscv: set fdtfile on VisionFive 2 by Heinrich Schuchardt · Thu Sep 07 13:21:28 2023 +0200
  88. c32177d riscv: Correct event usage for riscv_cpu_probe/setup by Tom Rini · Mon Sep 04 15:06:35 2023 -0400
  89. f4d52f6 riscv: Rework riscv_cpu_probe for current event macros by Tom Rini · Mon Sep 04 15:06:34 2023 -0400
  90. a7289b6 risc-v: implement DBCN write byte by Heinrich Schuchardt · Mon Sep 04 13:24:03 2023 +0200
  91. 85621526 riscv: cpu: jh7110: Imply SPL_SYS_MALLOC_CLEAR_ON_INIT by Shengyu Qu · Fri Aug 25 00:25:20 2023 +0800
  92. 42fa87e riscv: jh7110: enable riscv,timer in the device tree by Torsten Duwe · Mon Aug 14 18:05:33 2023 +0200
  93. 69dea21 Merge tag 'v2023.10-rc4' into next by Tom Rini · Mon Sep 04 10:51:58 2023 -0400
  94. b8357c1 event: Convert existing spy records to simple by Simon Glass · Mon Aug 21 21:16:56 2023 -0600
  95. 7ca0dc0 riscv: cpu: make riscv_cpu_probe to EVT_DM_POST_INIT_R callback by Chanho Park · Fri Aug 18 14:11:03 2023 +0900
  96. 51a9aac common: return type board_get_usable_ram_top by Heinrich Schuchardt · Sat Aug 12 20:16:58 2023 +0200
  97. ac4bf43 riscv: cpu: jh7110: Select SPL_ZERO_MEM_BEFORE_USE by Shengyu Qu · Wed Aug 09 21:11:33 2023 +0800
  98. 62b89a1 riscv: Add SPL_ZERO_MEM_BEFORE_USE implementation by Shengyu Qu · Wed Aug 09 21:11:32 2023 +0800
  99. d1a3254 riscv: Kconfig: Add SPL_ZERO_MEM_BEFORE_USE by Shengyu Qu · Wed Aug 09 21:11:31 2023 +0800
  100. 8fe34ac riscv: starfive: Add SYS_CACHE_SHIFT_6 to enable SYS_CACHELINE_SIZE by Minda Chen · Mon Aug 07 16:53:37 2023 +0800