| commit | 749d467c57d1761cef162382a02eacf97a00ad55 | [log] [tgz] |
|---|---|---|
| author | Kongyang Liu <seashell11234455@gmail.com> | Sun Mar 10 00:54:57 2024 +0800 |
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | Tue Apr 09 11:30:02 2024 +0800 |
| tree | 2ce0fe708842901444b0cf468ca1eb6f810a7731 | |
| parent | f7526743ab04f249adf7b10c9fc8adb3cf877fc1 [diff] |
riscv: cache: Implement dcache for cv1800b Add dcache operations invalidate_dcache_range and flush_dcache_range for cv1800b. Signed-off-by: Kongyang Liu <seashell11234455@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>