| commit | 9d82440da33f507abf0892b8e5e5297a942b1c66 | [log] [tgz] |
|---|---|---|
| author | Bo Gan <ganboing@gmail.com> | Tue Mar 05 19:00:11 2024 -0800 |
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | Tue Mar 12 14:36:13 2024 +0800 |
| tree | 64208fb838045f841c787f24d5cb867c273d2310 | |
| parent | 01a8587f0dc8124f5d5f21f265fa1cbd61a16b09 [diff] |
riscv: dts: jh7110: Enable PLL node in SPL Previously PLL node was missing from SPL dts. This caused BUS_ROOT to stay on OSC clock (24Mhz). As a result, all peripherals have to run at a much lower frequency, and loading from sdcard/emmc is slow. Thus, enabling PLL node in dts to fix this. Signed-off-by: Bo Gan <ganboing@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>