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git01.mediatek.com / filogic / uboot / a1b1fd1730d3208da2e7bf5485e47296d8f311b3 / arch / riscv / cpu
  1. 7862a2a andes: cpu: Enable cache and TLB ECC support by Leo Yu-Chi Liang · Tue Dec 26 14:17:35 2023 +0800
  2. 96e75a8 andes: cpu: Enable memboost feature by Leo Yu-Chi Liang · Tue Dec 26 14:17:34 2023 +0800
  3. 1eb9f91 andes: ae350: Implement cache switch via Kconfig by Leo Yu-Chi Liang · Tue Dec 26 14:17:33 2023 +0800
  4. 34ee3ed riscv: Add a reset_cpu() function by Simon Glass · Fri Dec 15 20:14:09 2023 -0700
  5. 6c6315e riscv: Align the trap handler to 64 bytes by Samuel Holland · Tue Oct 31 00:35:41 2023 -0500
  6. b6b9900 riscv: Remove common.h usage by Tom Rini · Thu Oct 12 19:03:59 2023 -0400
  7. 3b1bcfb riscv: remove dram_init_banksize() by Heinrich Schuchardt · Tue Sep 26 09:16:34 2023 +0200
  8. ac5e68f riscv: andesv5: Prefer using the generic RISC-V timer driver in S-mode by Yu Chien Peter Lin · Fri Sep 29 12:03:07 2023 +0800
  9. b29a747 Merge branch 'next' by Tom Rini · Mon Oct 02 10:55:44 2023 -0400
  10. c32177d riscv: Correct event usage for riscv_cpu_probe/setup by Tom Rini · Mon Sep 04 15:06:35 2023 -0400
  11. f4d52f6 riscv: Rework riscv_cpu_probe for current event macros by Tom Rini · Mon Sep 04 15:06:34 2023 -0400
  12. 85621526 riscv: cpu: jh7110: Imply SPL_SYS_MALLOC_CLEAR_ON_INIT by Shengyu Qu · Fri Aug 25 00:25:20 2023 +0800
  13. 69dea21 Merge tag 'v2023.10-rc4' into next by Tom Rini · Mon Sep 04 10:51:58 2023 -0400
  14. b8357c1 event: Convert existing spy records to simple by Simon Glass · Mon Aug 21 21:16:56 2023 -0600
  15. 7ca0dc0 riscv: cpu: make riscv_cpu_probe to EVT_DM_POST_INIT_R callback by Chanho Park · Fri Aug 18 14:11:03 2023 +0900
  16. 51a9aac common: return type board_get_usable_ram_top by Heinrich Schuchardt · Sat Aug 12 20:16:58 2023 +0200
  17. ac4bf43 riscv: cpu: jh7110: Select SPL_ZERO_MEM_BEFORE_USE by Shengyu Qu · Wed Aug 09 21:11:33 2023 +0800
  18. 62b89a1 riscv: Add SPL_ZERO_MEM_BEFORE_USE implementation by Shengyu Qu · Wed Aug 09 21:11:32 2023 +0800
  19. 8fe34ac riscv: starfive: Add SYS_CACHE_SHIFT_6 to enable SYS_CACHELINE_SIZE by Minda Chen · Mon Aug 07 16:53:37 2023 +0800
  20. 026a932 riscv: define a cache line size for the generic CPU by Heinrich Schuchardt · Fri Jul 21 18:01:18 2023 +0200
  21. 0cbd55b riscv: setup per-hart stack earlier by Bo Gan · Sun Jun 11 16:54:17 2023 -0700
  22. b5f0372 riscv: Rename SiFive CLINT to RISC-V ALINT by Bin Meng · Wed Jun 21 23:11:46 2023 +0800
  23. f69a512 ram: starfive: Read memory size information from EEPROM by Yanhong Wang · Thu Jun 15 17:36:51 2023 +0800
  24. 50e7d71 riscv: Fix alignment of RELA sections in the linker scripts by Bin Meng · Tue Jun 27 09:24:56 2023 +0800
  25. 9307401 dm: Emit the arch_cpu_init_dm() even only before relocation by Simon Glass · Thu May 04 16:50:45 2023 -0600
  26. 4478727 riscv: Update alignment for some sections in linker scripts by Bin Meng · Thu Apr 13 14:20:08 2023 +0800
  27. 604a0c5 riscv: spl: Remove relocation sections by Bin Meng · Thu Apr 13 14:20:07 2023 +0800
  28. 8615b1d riscv: Avoid updating the link register by Bin Meng · Thu Apr 13 14:20:06 2023 +0800
  29. 63d0fe4 riscv: Change to use positive offset to access relocation entries by Bin Meng · Thu Apr 13 14:20:05 2023 +0800
  30. 73449c9 riscv: Optimize loading relocation type by Bin Meng · Thu Apr 13 14:20:01 2023 +0800
  31. 3ccd29e riscv: Optimize source end address calculation in start.S by Bin Meng · Thu Apr 13 14:20:00 2023 +0800
  32. 5203a63 riscv: cpu: jh7110: Add Kconfig for StarFive JH7110 SoC by Yanhong Wang · Wed Mar 29 11:42:18 2023 +0800
  33. e28ec34 riscv: cpu: jh7110: Add support for jh7110 SoC by Yanhong Wang · Wed Mar 29 11:42:08 2023 +0800
  34. 249ce73 riscv: Rename Andes cpu and board names by Leo Yu-Chi Liang · Tue Feb 14 20:42:49 2023 +0800
  35. e440ed4 configs: ae350: Enable v5l2 cache for AE350 platforms in SPL by Yu Chien Peter Lin · Mon Feb 06 16:10:50 2023 +0800
  36. b2ccd1c riscv: ax25: cache.c: Cleanups to L1/L2 cache function used in SPL by Yu Chien Peter Lin · Mon Feb 06 16:10:49 2023 +0800
  37. 82f0f53 riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init() by Yu Chien Peter Lin · Mon Feb 06 16:10:47 2023 +0800
  38. 816979a riscv: Remove redundant Kconfig "RISCV_NDS_CACHE" by Leo Yu-Chi Liang · Mon Feb 06 16:10:44 2023 +0800
  39. 08537f3 riscv: ax25: bypass malloc when spl fit boots from ram by Rick Chen · Wed Jan 04 09:55:43 2023 +0800
  40. c1ec25e riscv: ae350: Enable CCTL_SUEN by Rick Chen · Tue Jan 03 16:17:13 2023 +0800
  41. c9382b1 riscv: cpu: check U-Mode before counteren write by Nikita Shubin · Wed Dec 14 08:58:43 2022 +0300
  42. a35afb8 riscv: Fix detecting FPU support in standard extension by Yu Chien Peter Lin · Sat Nov 05 14:02:14 2022 +0800
  43. 739cd6f riscv: Rename Andes PLIC to PLICSW by Yu Chien Peter Lin · Tue Oct 25 23:03:50 2022 +0800
  44. eff2077 Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-riscv into next by Tom Rini · Mon Sep 26 11:27:30 2022 -0400
  45. 9c4d5c1 riscv: Introduce AVAILABLE_HARTS by Rick Chen · Wed Sep 21 14:34:54 2022 +0800
  46. 7e5e029 spl: introduce SPL_XIP to config by Nikita Shubin · Fri Sep 02 11:47:39 2022 +0300
  47. 4f4f583 board_f: Fix types for board_get_usable_ram_top() by Pali Rohár · Fri Sep 09 17:32:40 2022 +0200
  48. 4150eec riscv: ae350: Fix XIP config boot failure by Leo Yu-Chi Liang · Wed Jun 01 10:01:49 2022 +0800
  49. 66ae7fe riscv: cpu: set gp before board_init_f_init_reserve by Nikita Shubin · Fri May 20 14:41:17 2022 +0300
  50. 5a9095c linker_lists: Rename sections to remove . prefix by Andrew Scull · Mon May 30 10:00:04 2022 +0000
  51. 4ddbade Migrate CUSTOM_SYS_INIT_SP_ADDR to Kconfig using system-constants.h by Tom Rini · Wed May 25 12:16:03 2022 -0400
  52. fc55736 event: Convert arch_cpu_init_dm() to use events by Simon Glass · Fri Mar 04 08:43:05 2022 -0700
  53. 9b9c4d5 riscv: Enable SPI flash env for SiFive Unmatched. by Thomas Skibo · Wed Nov 24 14:32:10 2021 -0800
  54. dc35df4 riscv: Remove OF_PRIOR_STAGE from RISC-V boards by Ilias Apalodimas · Tue Oct 12 00:00:13 2021 +0300
  55. 2795bf2 riscv: ae350: enable Coherence Manager for ae350 by Leo Yu-Chi Liang · Thu Sep 23 10:34:29 2021 +0800
  56. cc382ff sysreset: provide SBI based sysreset driver by Heinrich Schuchardt · Sun Sep 12 21:11:46 2021 +0200
  57. ec34849 board: sifive: use ccache driver instead of helper function by Zong Li · Wed Sep 01 15:01:42 2021 +0800
  58. f1ac8fa riscv: cpu: fu740: Fix typo of date by Zong Li · Mon Aug 02 15:34:14 2021 +0800
  59. bccfc2e i2c: Rename SPL/TPL_I2C_SUPPORT to I2C by Simon Glass · Sat Jul 10 21:14:36 2021 -0600
  60. 9627a8e riscv: sifive: fu740: Support i2c in spl by Zong Li · Wed Jun 30 23:23:47 2021 +0800
  61. 3376055 riscv: sifive: fu740: kconfig: Enable support for Opencores I2C controller by Zong Li · Wed Jun 30 23:23:46 2021 +0800
  62. 26190b8 riscv: cpu: fu740: clear feature disable CSR by Green Wan · Thu May 27 06:52:14 2021 -0700
  63. ecefa5f drivers: clk: add fu740 support by Green Wan · Thu May 27 06:52:08 2021 -0700
  64. 7f33743 riscv: cpu: fu740: Add support for cpu fu740 by Green Wan · Thu May 27 06:52:07 2021 -0700
  65. 4bebdd3 treewide: Convert macro and uses of __section(foo) to __section("foo") by Marek Behún · Thu May 20 13:23:52 2021 +0200
  66. 1255ab8 riscv: qemu: Switch to use binman to generate u-boot.itb by Bin Meng · Mon May 10 20:23:39 2021 +0800
  67. 614b1d8 riscv: Split SiFive CLINT support between SPL and U-Boot proper by Bin Meng · Tue May 11 20:04:12 2021 +0800
  68. b1b3bc0 Revert "riscv: cpu: fu740: clear feature disable CSR" by Bin Meng · Mon May 10 17:08:16 2021 +0800
  69. 968a13f riscv: cpu: fu740: clear feature disable CSR by Green Wan · Sun May 02 23:23:05 2021 -0700
  70. 2612080 riscv: cpu: Add callback to init each core by Green Wan · Sun May 02 23:23:04 2021 -0700
  71. 2f00216 cpu: Rename SPL_CPU_SUPPORT to SPL_CPU by Simon Glass · Mon Mar 15 18:11:18 2021 +1300
  72. b1db71b Merge branch '2021-02-02-drop-asm_global_data-when-unused' by Tom Rini · Mon Feb 15 08:19:40 2021 -0500
  73. 489b25a riscv: Adjust board_get_usable_ram_top() for 32-bit by Bin Meng · Sun Jan 31 20:35:57 2021 +0800
  74. 3ba929a common: Drop asm/global_data.h from common header by Simon Glass · Fri Oct 30 21:38:53 2020 -0600
  75. 4b96c88 riscv: fix the wrong swap value register by Brad Kim · Fri Nov 13 20:47:51 2020 +0900
  76. 4f1b444 riscv: sifive/fu540: kconfig: Enable support for Opencores I2C controller by Pragnesh Patel · Sat Nov 14 14:42:35 2020 +0530
  77. 5a23865 timer: Add _TIMER suffix to Andes PLMT Kconfig by Sean Anderson · Sun Oct 25 21:46:57 2020 -0400
  78. 5bdad9f riscv: Add some comments to start.S by Sean Anderson · Mon Sep 21 07:51:41 2020 -0400
  79. 2c4c7d1 riscv: Ensure gp is NULL or points to valid data by Sean Anderson · Mon Sep 21 07:51:40 2020 -0400
  80. 934b24a riscv: Consolidate fences into AMOs for available_harts_lock by Sean Anderson · Mon Sep 21 07:51:39 2020 -0400
  81. dd1cd70 riscv: Clear pending IPIs on initialization by Sean Anderson · Mon Sep 21 07:51:38 2020 -0400
  82. e8de08b Revert "riscv: Clear pending interrupts before enabling IPIs" by Sean Anderson · Mon Sep 21 07:51:35 2020 -0400
  83. 9baaaef riscv: Rework riscv timer driver to only support S-mode by Sean Anderson · Mon Sep 28 10:52:21 2020 -0400
  84. 54bcf26 riscv: fu540: Use correct API to get L2 cache controller base address by Bin Meng · Tue Aug 18 01:09:20 2020 -0700
  85. 03de50e riscv: sifive: fu540: redundant initialization by Heinrich Schuchardt · Mon Aug 03 23:09:49 2020 +0200
  86. 6b15551 riscv: sifive/fu540: kconfig: Move FU540 driver related options to the SoC level by Bin Meng · Sun Aug 02 23:09:04 2020 -0700
  87. 2b2d9c4 riscv: sifive/fu540: spl: Rename soc_spl_init() by Bin Meng · Sun Aug 02 23:09:03 2020 -0700
  88. 4e3ba2a riscv: Fix linking error when building u-boot-spl with no SMP support by Leo Yu-Chi Liang · Mon Jun 29 16:27:28 2020 +0800
  89. e70ef90 env: Enable SPI flash env for SiFive FU540 by Jagan Teki · Wed Jul 15 15:39:00 2020 +0530
  90. 257875d riscv: Make SiFive HiFive Unleashed board boot again by Bin Meng · Sun Jul 19 23:17:07 2020 -0700
  91. 90fa4e9 Merge branch 'next' by Tom Rini · Mon Jul 06 15:46:38 2020 -0400
  92. 8a52128 riscv: sifive: fu540: enable all cache ways from U-Boot proper by Pragnesh Patel · Fri May 29 12:14:51 2020 +0530
  93. 7f4b666 riscv: Add option to support RISC-V privileged spec 1.9 by Sean Anderson · Wed Jun 24 06:41:19 2020 -0400
  94. b1d0cb3 riscv: Clean up IPI initialization code by Sean Anderson · Wed Jun 24 06:41:18 2020 -0400
  95. 84df2e1 riscv: Clear pending interrupts before enabling IPIs by Sean Anderson · Wed Jun 24 06:41:17 2020 -0400
  96. e00653c riscv: sifive: fu540: add SPL configuration by Pragnesh Patel · Fri May 29 11:33:35 2020 +0530
  97. 25269c0 riscv: cpu: fu540: Add support for cpu fu540 by Pragnesh Patel · Fri May 29 11:33:34 2020 +0530
  98. 45b4ad9d riscv: Add _image_binary_end for SPL by Pragnesh Patel · Fri May 29 11:33:23 2020 +0530
  99. 4dcacfc common: Drop linux/bitops.h from common header by Simon Glass · Sun May 10 11:40:13 2020 -0600
  100. 9758973 common: Drop init.h from common header by Simon Glass · Sun May 10 11:40:02 2020 -0600