| commit | c9382b1073973474d4c350a00d04585f8a94b683 | [log] [tgz] |
|---|---|---|
| author | Nikita Shubin <n.shubin@yadro.com> | Wed Dec 14 08:58:43 2022 +0300 |
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | Wed Feb 01 16:17:13 2023 +0800 |
| tree | 71fa3178e46d5e00e95163f4409cbdca4ee093b8 | |
| parent | eeea2bf1b56bd52a98a8effb0066871673b01ce1 [diff] |
riscv: cpu: check U-Mode before counteren write The Priv ISA states: "In systems without U-mode, the mcounteren register should not exist." Check U-Mode is present in MISA before writing to counteren, otherwise we endup with Illegal Instruction exception on systems without U-Mode. Also make checking MISA default for M-Mode. Signed-off-by: Nikita Shubin <n.shubin@yadro.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>