| commit | 4b96c8811a14f92777f96d3797775cdef7600804 | [log] [tgz] |
|---|---|---|
| author | Brad Kim <brad.kim@semifive.com> | Fri Nov 13 20:47:51 2020 +0900 |
| committer | Andes <uboot@andestech.com> | Mon Dec 14 15:16:34 2020 +0800 |
| tree | b25433aa4126fdba6a61ab50d6afcccdcb60a582 | |
| parent | df486efded91093a991ea1313debdbf5c01f028a [diff] |
riscv: fix the wrong swap value register Not s2 register, t1 register is correct Fortunately, it works because t1 register has a garbage value Signed-off-by: Brad Kim <brad.kim@semifive.com> Reviewed-by: Lukas Auer <lukas@auer.io> Reviewed-by: Leo Liang <ycliang@andestech.com>