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git01.mediatek.com / filogic / uboot / 992562ce875ec2918c463d32f535aaa77b61a5b1 / arch / powerpc / cpu / mpc8xxx / ddr / ctrl_regs.c
  1. 992562c 8xxx: Change all 8*xx_DDR addresses to 8xxx by Andy Fleming · 12 years ago
  2. 82f576f arch/powerpc/cpu/mpc8xxx/: sparse fixes by Kim Phillips · 12 years ago
  3. 98df4d1 powerpc/mpc8xxx: Fix DDR driver handling quad-rank DIMMs and address calculation by York Sun · 12 years ago
  4. 7d69ea3 powerpc/mpc8xxx: Update DDR registers by York Sun · 12 years ago
  5. cd077cf powerpc/mpc8xxx: Fix bug for extended DDR timing by York Sun · 12 years ago
  6. e8dc17b powerpc/mpc8xxx: Enable 3-way and 4-way DDR interleaving by York Sun · 12 years ago
  7. bad8209 powerpc/mpc8xxx: Add support for cas latency 12 and above by York Sun · 12 years ago
  8. d5bbe66 arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c: Fix GCC 4.6 build warning by Kumar Gala · 13 years ago
  9. e12ce98 powerpc/mpc83xx: Migrate from spd_sdram to unified DDR driver by York Sun · 13 years ago
  10. 15f874a powerpc/mpc8xxx: Fix DDR code for empty first DIMM slot and enable DQS_en by York Sun · 13 years ago
  11. 7a16d64 powerpc/mpc8xxx: Extend CWL table by York Sun · 13 years ago
  12. f8691fc powerpc/mpc8xxx: Allow override DDR read-to-write turnaround time by York Sun · 14 years ago
  13. 4513d76 powerpc/8xxx: Fix typo for address hashing message by Kumar Gala · 14 years ago
  14. b78c7bf powerpc/8xxx: Replace fsl_ddr_get_mem_data_rate with get_ddr_freq() by Kumar Gala · 14 years ago
  15. 501b70d powerpc/mpc8xxx: disable rcw_en bit for non-DDR3 by York Sun · 14 years ago
  16. 3673f2c powerpc/mpc8xxx: Fix DDR3 timing_cfg_1 and sdram_mode registers by York Sun · 14 years ago
  17. 27f83be powerpc/8xxx: Add additional cycle to write-to-read turnaound for DDR3 by York Sun · 14 years ago
  18. 65b5be2 powerpc/8xxx: Fix compile warning when build for a DDR1 or DDR2 board by Kumar Gala · 14 years ago
  19. ba0c2eb mpc85xx: Enable unique mode registers and dynamic ODT for DDR3 by York Sun · 14 years ago
  20. 80ad401 8xxx/ddr: add support to only compute the ddr sdram size by Haiying Wang · 14 years ago
  21. 2927c5e Disable unused chip-select for DDR controller interleaving by York Sun · 14 years ago
  22. 5207e77 Fix parameters to support RDIMM for P2020DS by York Sun · 14 years ago
  23. 1714e49 powerpc/8xxx: Improvement to DDR parameters by york · 14 years ago
  24. de87932 powerpc/8xxx: Enable DDR3 RDIMM support by york · 14 years ago
  25. 4260372 powerpc/8xxx: Enabled address hashing for 85xx by york · 14 years ago
  26. f4f93c6 powerpc/8xxx: Enable quad-rank DIMMs. by york · 14 years ago
  27. 93799ca powerpc/8xxx: Fix bug in memctrl interleaving & bank interleaving on cs0~cs4 by york · 14 years ago
  28. 8107926 fsl-ddr: Add extra cycle to turnaround times by Dave Liu · 15 years ago
  29. 88fbf93 Move arch/ppc to arch/powerpc by Stefan Roese · 15 years ago[Renamed from arch/ppc/cpu/mpc8xxx/ddr/ctrl_regs.c]
  30. 29514c7 ppc: Move cpu/$CPU to arch/ppc/cpu/$CPU by Peter Tyser · 15 years ago[Renamed from cpu/mpc8xxx/ddr/ctrl_regs.c]
  31. 3525e1a fsl-ddr: Fix the turnaround timing for TIMING_CFG_4 by Dave Liu · 15 years ago
  32. 625b268 fsl-ddr: setup ODT_RD_CFG & ODT_WR_CFG when we interleave by Dave Liu · 15 years ago
  33. 2d0f125 fsl-ddr: add override for the Rtt_Wr by Dave Liu · 15 years ago
  34. 64ee7df fsl-ddr: add the override for write leveling by Dave Liu · 15 years ago
  35. c7d983a fsl-ddr: Fix power-down timing settings by Dave Liu · 15 years ago
  36. 14f2eb1 ppc/8xxx: Misc DDR related fixes by Kumar Gala · 15 years ago
  37. 24aa71a ppc/8xxx: Remove ddr_pd_cntl register since it doesn't exist by Kumar Gala · 15 years ago
  38. 68ef4bd fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BIT by Kumar Gala · 15 years ago
  39. 4be87b2 fsl-ddr: add the DDR3 SPD infrastructure by Dave Liu · 16 years ago
  40. 82aa953 fsl-ddr: Fix two bugs in the ddr infrastructure by Dave Liu · 16 years ago
  41. 2aad0ae fsl-ddr: make the self refresh idle threshold configurable by Dave Liu · 16 years ago
  42. 4758d53 fsl-ddr: clean up the ddr code for DDR3 controller by Dave Liu · 16 years ago
  43. 5c1bb51 fsl-ddr: update the bit mask for DDR3 controller by Dave Liu · 16 years ago
  44. d90e040 Add debug information for DDR controller registers by Haiying Wang · 16 years ago
  45. 272b596 Make DDR interleaving mode work correctly by Haiying Wang · 16 years ago
  46. 35ad58d Fix compiler warning in mpc8xxx ddr code by Kumar Gala · 16 years ago
  47. 124b082 FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. by Kumar Gala · 16 years ago