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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +05302/*
Bhaskar Upadhaya5e6f5982018-05-23 11:03:30 +05303 * Copyright 2017-2018 NXP
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +05304 */
5
6#include <common.h>
Simon Glass3bbe70c2019-12-28 10:44:54 -07007#include <fdt_support.h>
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +05308#include <i2c.h>
Simon Glass274e0b02020-05-10 11:39:56 -06009#include <asm/cache.h>
Simon Glass97589732020-05-10 11:40:02 -060010#include <init.h>
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +053011#include <asm/io.h>
12#include <asm/arch/clock.h>
13#include <asm/arch/fsl_serdes.h>
Prabhakar Kushwaha74d129b2017-01-30 17:05:35 +053014#ifdef CONFIG_FSL_LS_PPA
15#include <asm/arch/ppa.h>
16#endif
York Sun729f2d12017-03-06 09:02:34 -080017#include <asm/arch/mmu.h>
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +053018#include <asm/arch/soc.h>
Bhaskar Upadhaya5e6f5982018-05-23 11:03:30 +053019#include <fsl_esdhc.h>
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +053020#include <hwconfig.h>
Simon Glass9d1f6192019-08-02 09:44:25 -060021#include <env_internal.h>
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +053022#include <fsl_mmdc.h>
23#include <netdev.h>
Vinitha V Pillaiad698c32018-05-23 11:03:31 +053024#include <fsl_sec.h>
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +053025
26DECLARE_GLOBAL_DATA_PTR;
27
Bhaskar Upadhaya5e6f5982018-05-23 11:03:30 +053028static inline int get_board_version(void)
29{
Pramod Kumar46d752a2018-08-14 09:49:55 +053030 uint32_t val;
31#ifdef CONFIG_TARGET_LS1012AFRDM
32 val = 0;
33#else
34 struct ccsr_gpio *pgpio = (void *)(GPIO2_BASE_ADDR);
Bhaskar Upadhaya5e6f5982018-05-23 11:03:30 +053035
Pramod Kumar46d752a2018-08-14 09:49:55 +053036 val = in_be32(&pgpio->gpdat) & BOARD_REV_MASK;/*Get GPIO2 11,12,14*/
Bhaskar Upadhaya5e6f5982018-05-23 11:03:30 +053037
Pramod Kumar46d752a2018-08-14 09:49:55 +053038#endif
Bhaskar Upadhaya5e6f5982018-05-23 11:03:30 +053039 return val;
40}
41
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +053042int checkboard(void)
43{
Bhaskar Upadhaya5e6f5982018-05-23 11:03:30 +053044#ifdef CONFIG_TARGET_LS1012AFRDM
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +053045 puts("Board: LS1012AFRDM ");
Bhaskar Upadhaya5e6f5982018-05-23 11:03:30 +053046#else
47 int rev;
48
49 rev = get_board_version();
50
51 puts("Board: FRWY-LS1012A ");
52
53 puts("Version");
54
55 switch (rev) {
Pramod Kumar46d752a2018-08-14 09:49:55 +053056 case BOARD_REV_A_B:
57 puts(": RevA/B ");
Bhaskar Upadhaya5e6f5982018-05-23 11:03:30 +053058 break;
Pramod Kumar46d752a2018-08-14 09:49:55 +053059 case BOARD_REV_C:
60 puts(": RevC ");
Bhaskar Upadhaya5e6f5982018-05-23 11:03:30 +053061 break;
62 default:
63 puts(": unknown");
64 break;
65 }
66#endif
67
68 return 0;
69}
70
71#ifdef CONFIG_TARGET_LS1012AFRWY
72int esdhc_status_fixup(void *blob, const char *compat)
73{
74 char esdhc0_path[] = "/soc/esdhc@1560000";
75 char esdhc1_path[] = "/soc/esdhc@1580000";
76
77 do_fixup_by_path(blob, esdhc0_path, "status", "okay",
78 sizeof("okay"), 1);
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +053079
Bhaskar Upadhaya5e6f5982018-05-23 11:03:30 +053080 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
81 sizeof("disabled"), 1);
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +053082 return 0;
83}
Bhaskar Upadhaya5e6f5982018-05-23 11:03:30 +053084#endif
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +053085
Rajesh Bhagat487084e2018-11-05 18:03:08 +000086#ifdef CONFIG_TFABOOT
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +053087int dram_init(void)
88{
Bhaskar Upadhaya5e6f5982018-05-23 11:03:30 +053089#ifdef CONFIG_TARGET_LS1012AFRWY
90 int board_rev;
91#endif
Rajesh Bhagat487084e2018-11-05 18:03:08 +000092
93 gd->ram_size = tfa_get_dram_size();
94
95 if (!gd->ram_size) {
96#ifdef CONFIG_TARGET_LS1012AFRWY
97 board_rev = get_board_version();
98
99 if (board_rev & BOARD_REV_C)
100 gd->ram_size = SYS_SDRAM_SIZE_1024;
101 else
102 gd->ram_size = SYS_SDRAM_SIZE_512;
103#else
104 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
105#endif
106 }
107 return 0;
108}
109#else
110int dram_init(void)
111{
112#ifdef CONFIG_TARGET_LS1012AFRWY
113 int board_rev;
114#endif
Bhaskar Upadhaya5e6f5982018-05-23 11:03:30 +0530115 struct fsl_mmdc_info mparam = {
York Sunc1e979b2016-09-26 08:09:25 -0700116 0x04180000, /* mdctl */
117 0x00030035, /* mdpdc */
118 0x12554000, /* mdotc */
119 0xbabf7954, /* mdcfg0 */
120 0xdb328f64, /* mdcfg1 */
121 0x01ff00db, /* mdcfg2 */
122 0x00001680, /* mdmisc */
123 0x0f3c8000, /* mdref */
124 0x00002000, /* mdrwd */
125 0x00bf1023, /* mdor */
126 0x0000003f, /* mdasp */
127 0x0000022a, /* mpodtctrl */
128 0xa1390003, /* mpzqhwctrl */
129 };
130
Bhaskar Upadhaya5e6f5982018-05-23 11:03:30 +0530131#ifdef CONFIG_TARGET_LS1012AFRWY
132 board_rev = get_board_version();
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +0530133
Pramod Kumar46d752a2018-08-14 09:49:55 +0530134 if (board_rev == BOARD_REV_C) {
Bhaskar Upadhaya5e6f5982018-05-23 11:03:30 +0530135 mparam.mdctl = 0x05180000;
136 gd->ram_size = SYS_SDRAM_SIZE_1024;
137 } else {
138 gd->ram_size = SYS_SDRAM_SIZE_512;
139 }
140#else
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +0530141 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
Bhaskar Upadhaya5e6f5982018-05-23 11:03:30 +0530142#endif
143 mmdc_init(&mparam);
144
York Sun729f2d12017-03-06 09:02:34 -0800145#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
146 /* This will break-before-make MMU for DDR */
147 update_early_mmu_table();
148#endif
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +0530149
150 return 0;
151}
Rajesh Bhagat487084e2018-11-05 18:03:08 +0000152#endif
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +0530153
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +0530154int board_early_init_f(void)
155{
156 fsl_lsch2_early_init_f();
157
158 return 0;
159}
160
161int board_init(void)
162{
Ashish Kumar11234062017-08-11 11:09:14 +0530163 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
164 CONFIG_SYS_CCI400_OFFSET);
165
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +0530166 /*
167 * Set CCI-400 control override register to enable barrier
168 * transaction
169 */
Rajesh Bhagat487084e2018-11-05 18:03:08 +0000170 if (current_el() == 3)
171 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +0530172
173#ifdef CONFIG_ENV_IS_NOWHERE
174 gd->env_addr = (ulong)&default_environment[0];
175#endif
176
Vinitha V Pillaiad698c32018-05-23 11:03:31 +0530177#ifdef CONFIG_FSL_CAAM
178 sec_init();
179#endif
180
Prabhakar Kushwaha74d129b2017-01-30 17:05:35 +0530181#ifdef CONFIG_FSL_LS_PPA
182 ppa_init();
183#endif
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +0530184 return 0;
185}
186
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +0900187int ft_board_setup(void *blob, struct bd_info *bd)
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +0530188{
189 arch_fixup_fdt(blob);
190
191 ft_cpu_setup(blob, bd);
192
193 return 0;
194}