blob: 25d22d25bf80ca7857a050c79af52ade7c8e1a82 [file] [log] [blame]
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +05301/*
2 * Copyright 2016 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <i2c.h>
9#include <asm/io.h>
10#include <asm/arch/clock.h>
11#include <asm/arch/fsl_serdes.h>
Prabhakar Kushwaha74d129b2017-01-30 17:05:35 +053012#ifdef CONFIG_FSL_LS_PPA
13#include <asm/arch/ppa.h>
14#endif
York Sun729f2d12017-03-06 09:02:34 -080015#include <asm/arch/mmu.h>
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +053016#include <asm/arch/soc.h>
17#include <hwconfig.h>
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +053018#include <environment.h>
19#include <fsl_mmdc.h>
20#include <netdev.h>
21
22DECLARE_GLOBAL_DATA_PTR;
23
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +053024int checkboard(void)
25{
26 puts("Board: LS1012AFRDM ");
27
28 return 0;
29}
30
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +053031int dram_init(void)
32{
York Sunc1e979b2016-09-26 08:09:25 -070033 static const struct fsl_mmdc_info mparam = {
34 0x04180000, /* mdctl */
35 0x00030035, /* mdpdc */
36 0x12554000, /* mdotc */
37 0xbabf7954, /* mdcfg0 */
38 0xdb328f64, /* mdcfg1 */
39 0x01ff00db, /* mdcfg2 */
40 0x00001680, /* mdmisc */
41 0x0f3c8000, /* mdref */
42 0x00002000, /* mdrwd */
43 0x00bf1023, /* mdor */
44 0x0000003f, /* mdasp */
45 0x0000022a, /* mpodtctrl */
46 0xa1390003, /* mpzqhwctrl */
47 };
48
49 mmdc_init(&mparam);
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +053050
51 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
York Sun729f2d12017-03-06 09:02:34 -080052#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
53 /* This will break-before-make MMU for DDR */
54 update_early_mmu_table();
55#endif
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +053056
57 return 0;
58}
59
60int board_eth_init(bd_t *bis)
61{
62 return pci_eth_init(bis);
63}
64
65int board_early_init_f(void)
66{
67 fsl_lsch2_early_init_f();
68
69 return 0;
70}
71
72int board_init(void)
73{
74 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
75 /*
76 * Set CCI-400 control override register to enable barrier
77 * transaction
78 */
79 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
80
81#ifdef CONFIG_ENV_IS_NOWHERE
82 gd->env_addr = (ulong)&default_environment[0];
83#endif
84
Prabhakar Kushwaha74d129b2017-01-30 17:05:35 +053085#ifdef CONFIG_FSL_LS_PPA
86 ppa_init();
87#endif
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +053088 return 0;
89}
90
91int ft_board_setup(void *blob, bd_t *bd)
92{
93 arch_fixup_fdt(blob);
94
95 ft_cpu_setup(blob, bd);
96
97 return 0;
98}