blob: 5db1027717fe14284aff257c89b88ff8cc40d2aa [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +05302/*
Bhaskar Upadhaya5e6f5982018-05-23 11:03:30 +05303 * Copyright 2017-2018 NXP
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +05304 */
5
6#include <common.h>
7#include <i2c.h>
8#include <asm/io.h>
9#include <asm/arch/clock.h>
10#include <asm/arch/fsl_serdes.h>
Prabhakar Kushwaha74d129b2017-01-30 17:05:35 +053011#ifdef CONFIG_FSL_LS_PPA
12#include <asm/arch/ppa.h>
13#endif
York Sun729f2d12017-03-06 09:02:34 -080014#include <asm/arch/mmu.h>
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +053015#include <asm/arch/soc.h>
Bhaskar Upadhaya5e6f5982018-05-23 11:03:30 +053016#include <fsl_esdhc.h>
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +053017#include <hwconfig.h>
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +053018#include <environment.h>
19#include <fsl_mmdc.h>
20#include <netdev.h>
Vinitha V Pillaiad698c32018-05-23 11:03:31 +053021#include <fsl_sec.h>
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +053022
23DECLARE_GLOBAL_DATA_PTR;
24
Bhaskar Upadhaya5e6f5982018-05-23 11:03:30 +053025static inline int get_board_version(void)
26{
Pramod Kumar46d752a2018-08-14 09:49:55 +053027 uint32_t val;
28#ifdef CONFIG_TARGET_LS1012AFRDM
29 val = 0;
30#else
31 struct ccsr_gpio *pgpio = (void *)(GPIO2_BASE_ADDR);
Bhaskar Upadhaya5e6f5982018-05-23 11:03:30 +053032
Pramod Kumar46d752a2018-08-14 09:49:55 +053033 val = in_be32(&pgpio->gpdat) & BOARD_REV_MASK;/*Get GPIO2 11,12,14*/
Bhaskar Upadhaya5e6f5982018-05-23 11:03:30 +053034
Pramod Kumar46d752a2018-08-14 09:49:55 +053035#endif
Bhaskar Upadhaya5e6f5982018-05-23 11:03:30 +053036 return val;
37}
38
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +053039int checkboard(void)
40{
Bhaskar Upadhaya5e6f5982018-05-23 11:03:30 +053041#ifdef CONFIG_TARGET_LS1012AFRDM
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +053042 puts("Board: LS1012AFRDM ");
Bhaskar Upadhaya5e6f5982018-05-23 11:03:30 +053043#else
44 int rev;
45
46 rev = get_board_version();
47
48 puts("Board: FRWY-LS1012A ");
49
50 puts("Version");
51
52 switch (rev) {
Pramod Kumar46d752a2018-08-14 09:49:55 +053053 case BOARD_REV_A_B:
54 puts(": RevA/B ");
Bhaskar Upadhaya5e6f5982018-05-23 11:03:30 +053055 break;
Pramod Kumar46d752a2018-08-14 09:49:55 +053056 case BOARD_REV_C:
57 puts(": RevC ");
Bhaskar Upadhaya5e6f5982018-05-23 11:03:30 +053058 break;
59 default:
60 puts(": unknown");
61 break;
62 }
63#endif
64
65 return 0;
66}
67
68#ifdef CONFIG_TARGET_LS1012AFRWY
69int esdhc_status_fixup(void *blob, const char *compat)
70{
71 char esdhc0_path[] = "/soc/esdhc@1560000";
72 char esdhc1_path[] = "/soc/esdhc@1580000";
73
74 do_fixup_by_path(blob, esdhc0_path, "status", "okay",
75 sizeof("okay"), 1);
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +053076
Bhaskar Upadhaya5e6f5982018-05-23 11:03:30 +053077 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
78 sizeof("disabled"), 1);
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +053079 return 0;
80}
Bhaskar Upadhaya5e6f5982018-05-23 11:03:30 +053081#endif
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +053082
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +053083int dram_init(void)
84{
Bhaskar Upadhaya5e6f5982018-05-23 11:03:30 +053085#ifdef CONFIG_TARGET_LS1012AFRWY
86 int board_rev;
87#endif
88 struct fsl_mmdc_info mparam = {
York Sunc1e979b2016-09-26 08:09:25 -070089 0x04180000, /* mdctl */
90 0x00030035, /* mdpdc */
91 0x12554000, /* mdotc */
92 0xbabf7954, /* mdcfg0 */
93 0xdb328f64, /* mdcfg1 */
94 0x01ff00db, /* mdcfg2 */
95 0x00001680, /* mdmisc */
96 0x0f3c8000, /* mdref */
97 0x00002000, /* mdrwd */
98 0x00bf1023, /* mdor */
99 0x0000003f, /* mdasp */
100 0x0000022a, /* mpodtctrl */
101 0xa1390003, /* mpzqhwctrl */
102 };
103
Bhaskar Upadhaya5e6f5982018-05-23 11:03:30 +0530104#ifdef CONFIG_TARGET_LS1012AFRWY
105 board_rev = get_board_version();
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +0530106
Pramod Kumar46d752a2018-08-14 09:49:55 +0530107 if (board_rev == BOARD_REV_C) {
Bhaskar Upadhaya5e6f5982018-05-23 11:03:30 +0530108 mparam.mdctl = 0x05180000;
109 gd->ram_size = SYS_SDRAM_SIZE_1024;
110 } else {
111 gd->ram_size = SYS_SDRAM_SIZE_512;
112 }
113#else
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +0530114 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
Bhaskar Upadhaya5e6f5982018-05-23 11:03:30 +0530115#endif
116 mmdc_init(&mparam);
117
York Sun729f2d12017-03-06 09:02:34 -0800118#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
119 /* This will break-before-make MMU for DDR */
120 update_early_mmu_table();
121#endif
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +0530122
123 return 0;
124}
125
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +0530126int board_early_init_f(void)
127{
128 fsl_lsch2_early_init_f();
129
130 return 0;
131}
132
133int board_init(void)
134{
Ashish Kumar11234062017-08-11 11:09:14 +0530135 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
136 CONFIG_SYS_CCI400_OFFSET);
137
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +0530138 /*
139 * Set CCI-400 control override register to enable barrier
140 * transaction
141 */
142 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
143
144#ifdef CONFIG_ENV_IS_NOWHERE
145 gd->env_addr = (ulong)&default_environment[0];
146#endif
147
Vinitha V Pillaiad698c32018-05-23 11:03:31 +0530148#ifdef CONFIG_FSL_CAAM
149 sec_init();
150#endif
151
Prabhakar Kushwaha74d129b2017-01-30 17:05:35 +0530152#ifdef CONFIG_FSL_LS_PPA
153 ppa_init();
154#endif
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +0530155 return 0;
156}
157
158int ft_board_setup(void *blob, bd_t *bd)
159{
160 arch_fixup_fdt(blob);
161
162 ft_cpu_setup(blob, bd);
163
164 return 0;
165}