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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +05302/*
Bhaskar Upadhaya5e6f5982018-05-23 11:03:30 +05303 * Copyright 2017-2018 NXP
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +05304 */
5
6#include <common.h>
Simon Glass3bbe70c2019-12-28 10:44:54 -07007#include <fdt_support.h>
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +05308#include <i2c.h>
9#include <asm/io.h>
10#include <asm/arch/clock.h>
11#include <asm/arch/fsl_serdes.h>
Prabhakar Kushwaha74d129b2017-01-30 17:05:35 +053012#ifdef CONFIG_FSL_LS_PPA
13#include <asm/arch/ppa.h>
14#endif
York Sun729f2d12017-03-06 09:02:34 -080015#include <asm/arch/mmu.h>
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +053016#include <asm/arch/soc.h>
Bhaskar Upadhaya5e6f5982018-05-23 11:03:30 +053017#include <fsl_esdhc.h>
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +053018#include <hwconfig.h>
Simon Glass9d1f6192019-08-02 09:44:25 -060019#include <env_internal.h>
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +053020#include <fsl_mmdc.h>
21#include <netdev.h>
Vinitha V Pillaiad698c32018-05-23 11:03:31 +053022#include <fsl_sec.h>
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +053023
24DECLARE_GLOBAL_DATA_PTR;
25
Bhaskar Upadhaya5e6f5982018-05-23 11:03:30 +053026static inline int get_board_version(void)
27{
Pramod Kumar46d752a2018-08-14 09:49:55 +053028 uint32_t val;
29#ifdef CONFIG_TARGET_LS1012AFRDM
30 val = 0;
31#else
32 struct ccsr_gpio *pgpio = (void *)(GPIO2_BASE_ADDR);
Bhaskar Upadhaya5e6f5982018-05-23 11:03:30 +053033
Pramod Kumar46d752a2018-08-14 09:49:55 +053034 val = in_be32(&pgpio->gpdat) & BOARD_REV_MASK;/*Get GPIO2 11,12,14*/
Bhaskar Upadhaya5e6f5982018-05-23 11:03:30 +053035
Pramod Kumar46d752a2018-08-14 09:49:55 +053036#endif
Bhaskar Upadhaya5e6f5982018-05-23 11:03:30 +053037 return val;
38}
39
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +053040int checkboard(void)
41{
Bhaskar Upadhaya5e6f5982018-05-23 11:03:30 +053042#ifdef CONFIG_TARGET_LS1012AFRDM
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +053043 puts("Board: LS1012AFRDM ");
Bhaskar Upadhaya5e6f5982018-05-23 11:03:30 +053044#else
45 int rev;
46
47 rev = get_board_version();
48
49 puts("Board: FRWY-LS1012A ");
50
51 puts("Version");
52
53 switch (rev) {
Pramod Kumar46d752a2018-08-14 09:49:55 +053054 case BOARD_REV_A_B:
55 puts(": RevA/B ");
Bhaskar Upadhaya5e6f5982018-05-23 11:03:30 +053056 break;
Pramod Kumar46d752a2018-08-14 09:49:55 +053057 case BOARD_REV_C:
58 puts(": RevC ");
Bhaskar Upadhaya5e6f5982018-05-23 11:03:30 +053059 break;
60 default:
61 puts(": unknown");
62 break;
63 }
64#endif
65
66 return 0;
67}
68
69#ifdef CONFIG_TARGET_LS1012AFRWY
70int esdhc_status_fixup(void *blob, const char *compat)
71{
72 char esdhc0_path[] = "/soc/esdhc@1560000";
73 char esdhc1_path[] = "/soc/esdhc@1580000";
74
75 do_fixup_by_path(blob, esdhc0_path, "status", "okay",
76 sizeof("okay"), 1);
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +053077
Bhaskar Upadhaya5e6f5982018-05-23 11:03:30 +053078 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
79 sizeof("disabled"), 1);
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +053080 return 0;
81}
Bhaskar Upadhaya5e6f5982018-05-23 11:03:30 +053082#endif
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +053083
Rajesh Bhagat487084e2018-11-05 18:03:08 +000084#ifdef CONFIG_TFABOOT
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +053085int dram_init(void)
86{
Bhaskar Upadhaya5e6f5982018-05-23 11:03:30 +053087#ifdef CONFIG_TARGET_LS1012AFRWY
88 int board_rev;
89#endif
Rajesh Bhagat487084e2018-11-05 18:03:08 +000090
91 gd->ram_size = tfa_get_dram_size();
92
93 if (!gd->ram_size) {
94#ifdef CONFIG_TARGET_LS1012AFRWY
95 board_rev = get_board_version();
96
97 if (board_rev & BOARD_REV_C)
98 gd->ram_size = SYS_SDRAM_SIZE_1024;
99 else
100 gd->ram_size = SYS_SDRAM_SIZE_512;
101#else
102 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
103#endif
104 }
105 return 0;
106}
107#else
108int dram_init(void)
109{
110#ifdef CONFIG_TARGET_LS1012AFRWY
111 int board_rev;
112#endif
Bhaskar Upadhaya5e6f5982018-05-23 11:03:30 +0530113 struct fsl_mmdc_info mparam = {
York Sunc1e979b2016-09-26 08:09:25 -0700114 0x04180000, /* mdctl */
115 0x00030035, /* mdpdc */
116 0x12554000, /* mdotc */
117 0xbabf7954, /* mdcfg0 */
118 0xdb328f64, /* mdcfg1 */
119 0x01ff00db, /* mdcfg2 */
120 0x00001680, /* mdmisc */
121 0x0f3c8000, /* mdref */
122 0x00002000, /* mdrwd */
123 0x00bf1023, /* mdor */
124 0x0000003f, /* mdasp */
125 0x0000022a, /* mpodtctrl */
126 0xa1390003, /* mpzqhwctrl */
127 };
128
Bhaskar Upadhaya5e6f5982018-05-23 11:03:30 +0530129#ifdef CONFIG_TARGET_LS1012AFRWY
130 board_rev = get_board_version();
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +0530131
Pramod Kumar46d752a2018-08-14 09:49:55 +0530132 if (board_rev == BOARD_REV_C) {
Bhaskar Upadhaya5e6f5982018-05-23 11:03:30 +0530133 mparam.mdctl = 0x05180000;
134 gd->ram_size = SYS_SDRAM_SIZE_1024;
135 } else {
136 gd->ram_size = SYS_SDRAM_SIZE_512;
137 }
138#else
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +0530139 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
Bhaskar Upadhaya5e6f5982018-05-23 11:03:30 +0530140#endif
141 mmdc_init(&mparam);
142
York Sun729f2d12017-03-06 09:02:34 -0800143#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
144 /* This will break-before-make MMU for DDR */
145 update_early_mmu_table();
146#endif
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +0530147
148 return 0;
149}
Rajesh Bhagat487084e2018-11-05 18:03:08 +0000150#endif
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +0530151
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +0530152int board_early_init_f(void)
153{
154 fsl_lsch2_early_init_f();
155
156 return 0;
157}
158
159int board_init(void)
160{
Ashish Kumar11234062017-08-11 11:09:14 +0530161 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
162 CONFIG_SYS_CCI400_OFFSET);
163
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +0530164 /*
165 * Set CCI-400 control override register to enable barrier
166 * transaction
167 */
Rajesh Bhagat487084e2018-11-05 18:03:08 +0000168 if (current_el() == 3)
169 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +0530170
171#ifdef CONFIG_ENV_IS_NOWHERE
172 gd->env_addr = (ulong)&default_environment[0];
173#endif
174
Vinitha V Pillaiad698c32018-05-23 11:03:31 +0530175#ifdef CONFIG_FSL_CAAM
176 sec_init();
177#endif
178
Prabhakar Kushwaha74d129b2017-01-30 17:05:35 +0530179#ifdef CONFIG_FSL_LS_PPA
180 ppa_init();
181#endif
Prabhakar Kushwaha9e7ee7b2016-06-03 18:41:36 +0530182 return 0;
183}
184
185int ft_board_setup(void *blob, bd_t *bd)
186{
187 arch_fixup_fdt(blob);
188
189 ft_cpu_setup(blob, bd);
190
191 return 0;
192}